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3384f95c DG |
1 | /* |
2 | * QEMU SPAPR PCI BUS definitions | |
3 | * | |
4 | * Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #if !defined(__HW_SPAPR_H__) | |
20 | #error Please include spapr.h before this file! | |
21 | #endif | |
22 | ||
23 | #if !defined(__HW_SPAPR_PCI_H__) | |
24 | #define __HW_SPAPR_PCI_H__ | |
25 | ||
a2cb15b0 MT |
26 | #include "hw/pci/pci.h" |
27 | #include "hw/pci/pci_host.h" | |
0d09e41a | 28 | #include "hw/ppc/xics.h" |
3384f95c | 29 | |
8c9f64df | 30 | #define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge" |
9fc34ada | 31 | #define TYPE_SPAPR_PCI_VFIO_HOST_BRIDGE "spapr-pci-vfio-host-bridge" |
8c9f64df AF |
32 | |
33 | #define SPAPR_PCI_HOST_BRIDGE(obj) \ | |
34 | OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE) | |
35 | ||
9fc34ada AK |
36 | #define SPAPR_PCI_VFIO_HOST_BRIDGE(obj) \ |
37 | OBJECT_CHECK(sPAPRPHBVFIOState, (obj), TYPE_SPAPR_PCI_VFIO_HOST_BRIDGE) | |
38 | ||
da6ccee4 AK |
39 | #define SPAPR_PCI_HOST_BRIDGE_CLASS(klass) \ |
40 | OBJECT_CLASS_CHECK(sPAPRPHBClass, (klass), TYPE_SPAPR_PCI_HOST_BRIDGE) | |
41 | #define SPAPR_PCI_HOST_BRIDGE_GET_CLASS(obj) \ | |
42 | OBJECT_GET_CLASS(sPAPRPHBClass, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE) | |
43 | ||
44 | typedef struct sPAPRPHBClass sPAPRPHBClass; | |
45 | typedef struct sPAPRPHBState sPAPRPHBState; | |
9fc34ada | 46 | typedef struct sPAPRPHBVFIOState sPAPRPHBVFIOState; |
da6ccee4 AK |
47 | |
48 | struct sPAPRPHBClass { | |
49 | PCIHostBridgeClass parent_class; | |
50 | ||
51 | void (*finish_realize)(sPAPRPHBState *sphb, Error **errp); | |
52 | }; | |
53 | ||
9a321e92 AK |
54 | typedef struct spapr_pci_msi { |
55 | uint32_t first_irq; | |
56 | uint32_t num; | |
57 | } spapr_pci_msi; | |
58 | ||
59 | typedef struct spapr_pci_msi_mig { | |
60 | uint32_t key; | |
61 | spapr_pci_msi value; | |
62 | } spapr_pci_msi_mig; | |
63 | ||
da6ccee4 | 64 | struct sPAPRPHBState { |
67c332fd | 65 | PCIHostState parent_obj; |
3384f95c | 66 | |
caae58cb | 67 | int32_t index; |
3384f95c | 68 | uint64_t buid; |
298a9710 | 69 | char *dtbusname; |
3384f95c DG |
70 | |
71 | MemoryRegion memspace, iospace; | |
a8170e5e | 72 | hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size; |
8c46f7ec | 73 | MemoryRegion memwindow, iowindow, msiwindow; |
0ee2c058 | 74 | |
5c4cbcf2 | 75 | uint32_t dma_liobn; |
e00387d5 | 76 | AddressSpace iommu_as; |
cca7fad5 | 77 | MemoryRegion iommu_root; |
3384f95c | 78 | |
1112cf94 | 79 | struct spapr_pci_lsi { |
a307d594 | 80 | uint32_t irq; |
7fb0bd34 | 81 | } lsi_table[PCI_NUM_PINS]; |
3384f95c | 82 | |
9a321e92 AK |
83 | GHashTable *msi; |
84 | /* Temporary cache for migration purposes */ | |
85 | int32_t msi_devs_num; | |
86 | spapr_pci_msi_mig *msi_devs; | |
0ee2c058 | 87 | |
3384f95c | 88 | QLIST_ENTRY(sPAPRPHBState) list; |
da6ccee4 | 89 | }; |
3384f95c | 90 | |
9fc34ada AK |
91 | struct sPAPRPHBVFIOState { |
92 | sPAPRPHBState phb; | |
93 | ||
94 | int32_t iommugroupid; | |
95 | }; | |
96 | ||
caae58cb DG |
97 | #define SPAPR_PCI_BASE_BUID 0x800000020000000ULL |
98 | ||
99 | #define SPAPR_PCI_WINDOW_BASE 0x10000000000ULL | |
100 | #define SPAPR_PCI_WINDOW_SPACING 0x1000000000ULL | |
101 | #define SPAPR_PCI_MMIO_WIN_OFF 0xA0000000 | |
102 | #define SPAPR_PCI_MMIO_WIN_SIZE 0x20000000 | |
103 | #define SPAPR_PCI_IO_WIN_OFF 0x80000000 | |
104 | #define SPAPR_PCI_IO_WIN_SIZE 0x10000 | |
f1c2dc7c AK |
105 | |
106 | #define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL | |
caae58cb DG |
107 | |
108 | #define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL | |
109 | ||
a307d594 AK |
110 | static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin) |
111 | { | |
112 | return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq); | |
113 | } | |
114 | ||
89dfd6e1 | 115 | PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index); |
3384f95c | 116 | |
e0fdbd7c AK |
117 | int spapr_populate_pci_dt(sPAPRPHBState *phb, |
118 | uint32_t xics_phandle, | |
119 | void *fdt); | |
3384f95c | 120 | |
f1c2dc7c AK |
121 | void spapr_pci_msi_init(sPAPREnvironment *spapr, hwaddr addr); |
122 | ||
fa28f71b AK |
123 | void spapr_pci_rtas_init(void); |
124 | ||
3384f95c | 125 | #endif /* __HW_SPAPR_PCI_H__ */ |