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3384f95c DG |
1 | /* |
2 | * QEMU SPAPR PCI BUS definitions | |
3 | * | |
4 | * Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
3384f95c | 19 | |
121d0712 MA |
20 | #ifndef PCI_HOST_SPAPR_H |
21 | #define PCI_HOST_SPAPR_H | |
3384f95c | 22 | |
20668fde | 23 | #include "hw/ppc/spapr.h" |
a2cb15b0 MT |
24 | #include "hw/pci/pci.h" |
25 | #include "hw/pci/pci_host.h" | |
0d09e41a | 26 | #include "hw/ppc/xics.h" |
3384f95c | 27 | |
8c9f64df AF |
28 | #define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge" |
29 | ||
30 | #define SPAPR_PCI_HOST_BRIDGE(obj) \ | |
ce2918cb | 31 | OBJECT_CHECK(SpaprPhbState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE) |
8c9f64df | 32 | |
ae4de14c AK |
33 | #define SPAPR_PCI_DMA_MAX_WINDOWS 2 |
34 | ||
ce2918cb | 35 | typedef struct SpaprPhbState SpaprPhbState; |
da6ccee4 | 36 | |
9a321e92 AK |
37 | typedef struct spapr_pci_msi { |
38 | uint32_t first_irq; | |
39 | uint32_t num; | |
40 | } spapr_pci_msi; | |
41 | ||
42 | typedef struct spapr_pci_msi_mig { | |
43 | uint32_t key; | |
44 | spapr_pci_msi value; | |
45 | } spapr_pci_msi_mig; | |
46 | ||
ce2918cb | 47 | struct SpaprPhbState { |
67c332fd | 48 | PCIHostState parent_obj; |
3384f95c | 49 | |
3e4ac968 | 50 | uint32_t index; |
3384f95c | 51 | uint64_t buid; |
298a9710 | 52 | char *dtbusname; |
7619c7b0 | 53 | bool dr_enabled; |
3384f95c DG |
54 | |
55 | MemoryRegion memspace, iospace; | |
daa23699 DG |
56 | hwaddr mem_win_addr, mem_win_size, mem64_win_addr, mem64_win_size; |
57 | uint64_t mem64_win_pciaddr; | |
58 | hwaddr io_win_addr, io_win_size; | |
59 | MemoryRegion mem32window, mem64window, iowindow, msiwindow; | |
0ee2c058 | 60 | |
ae4de14c | 61 | uint32_t dma_liobn[SPAPR_PCI_DMA_MAX_WINDOWS]; |
f93caaac | 62 | hwaddr dma_win_addr, dma_win_size; |
e00387d5 | 63 | AddressSpace iommu_as; |
cca7fad5 | 64 | MemoryRegion iommu_root; |
3384f95c | 65 | |
1112cf94 | 66 | struct spapr_pci_lsi { |
a307d594 | 67 | uint32_t irq; |
7fb0bd34 | 68 | } lsi_table[PCI_NUM_PINS]; |
3384f95c | 69 | |
9a321e92 AK |
70 | GHashTable *msi; |
71 | /* Temporary cache for migration purposes */ | |
72 | int32_t msi_devs_num; | |
73 | spapr_pci_msi_mig *msi_devs; | |
0ee2c058 | 74 | |
ce2918cb | 75 | QLIST_ENTRY(SpaprPhbState) list; |
ae4de14c AK |
76 | |
77 | bool ddw_enabled; | |
78 | uint64_t page_size_mask; | |
79 | uint64_t dma64_win_addr; | |
4814401f AK |
80 | |
81 | uint32_t numa_node; | |
5c4537bd | 82 | |
82516263 DG |
83 | bool pcie_ecs; /* Allow access to PCIe extended config space? */ |
84 | ||
5c4537bd DG |
85 | /* Fields for migration compatibility hacks */ |
86 | bool pre_2_8_migration; | |
87 | uint32_t mig_liobn; | |
88 | hwaddr mig_mem_win_addr, mig_mem_win_size; | |
89 | hwaddr mig_io_win_addr, mig_io_win_size; | |
ec132efa AK |
90 | hwaddr nv2_gpa_win_addr; |
91 | hwaddr nv2_atsd_win_addr; | |
92 | struct spapr_phb_pci_nvgpu_config *nvgpus; | |
da6ccee4 | 93 | }; |
3384f95c | 94 | |
b194df47 | 95 | #define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL |
daa23699 DG |
96 | #define SPAPR_PCI_MEM32_WIN_SIZE \ |
97 | ((1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET) | |
357d1e3b | 98 | #define SPAPR_PCI_MEM64_WIN_SIZE 0x10000000000ULL /* 1 TiB */ |
b194df47 | 99 | |
1da85c2a | 100 | /* All PCI outbound windows will be within this range */ |
357d1e3b DG |
101 | #define SPAPR_PCI_BASE (1ULL << 45) /* 32 TiB */ |
102 | #define SPAPR_PCI_LIMIT (1ULL << 46) /* 64 TiB */ | |
103 | ||
1da85c2a GK |
104 | #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ |
105 | SPAPR_PCI_MEM64_WIN_SIZE - 1) | |
106 | ||
caae58cb | 107 | #define SPAPR_PCI_IO_WIN_SIZE 0x10000 |
f1c2dc7c AK |
108 | |
109 | #define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL | |
caae58cb | 110 | |
ec132efa AK |
111 | #define SPAPR_PCI_NV2RAM64_WIN_BASE SPAPR_PCI_LIMIT |
112 | #define SPAPR_PCI_NV2RAM64_WIN_SIZE (2 * TiB) /* For up to 6 GPUs 256GB each */ | |
113 | ||
114 | /* Max number of these GPUsper a physical box */ | |
115 | #define NVGPU_MAX_NUM 6 | |
116 | /* Max number of NVLinks per GPU in any physical box */ | |
117 | #define NVGPU_MAX_LINKS 3 | |
118 | ||
119 | /* | |
120 | * GPU RAM starts at 64TiB so huge DMA window to cover it all ends at 128TiB | |
121 | * which is enough. We do not need DMA for ATSD so we put them at 128TiB. | |
122 | */ | |
123 | #define SPAPR_PCI_NV2ATSD_WIN_BASE (128 * TiB) | |
124 | #define SPAPR_PCI_NV2ATSD_WIN_SIZE (NVGPU_MAX_NUM * NVGPU_MAX_LINKS * \ | |
125 | 64 * KiB) | |
126 | ||
ce2918cb | 127 | static inline qemu_irq spapr_phb_lsi_qirq(struct SpaprPhbState *phb, int pin) |
a307d594 | 128 | { |
ce2918cb | 129 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
28e02042 | 130 | |
77183755 | 131 | return spapr_qirq(spapr, phb->lsi_table[pin].irq); |
a307d594 AK |
132 | } |
133 | ||
466e8831 DG |
134 | int spapr_dt_phb(SpaprPhbState *phb, uint32_t intc_phandle, void *fdt, |
135 | uint32_t nr_msis, int *node_offset); | |
3384f95c | 136 | |
fa28f71b AK |
137 | void spapr_pci_rtas_init(void); |
138 | ||
ce2918cb DG |
139 | SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid); |
140 | PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid, | |
46c5874e AK |
141 | uint32_t config_addr); |
142 | ||
46fd0299 | 143 | /* DRC callbacks */ |
31834723 | 144 | void spapr_phb_remove_pci_device_cb(DeviceState *dev); |
ce2918cb | 145 | int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, |
46fd0299 | 146 | void *fdt, int *fdt_start_offset, Error **errp); |
31834723 | 147 | |
fbb4e983 DG |
148 | /* VFIO EEH hooks */ |
149 | #ifdef CONFIG_LINUX | |
ce2918cb DG |
150 | bool spapr_phb_eeh_available(SpaprPhbState *sphb); |
151 | int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb, | |
fbb4e983 | 152 | unsigned int addr, int option); |
ce2918cb DG |
153 | int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state); |
154 | int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option); | |
155 | int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb); | |
fbb4e983 | 156 | void spapr_phb_vfio_reset(DeviceState *qdev); |
ec132efa AK |
157 | void spapr_phb_nvgpu_setup(SpaprPhbState *sphb, Error **errp); |
158 | void spapr_phb_nvgpu_free(SpaprPhbState *sphb); | |
159 | void spapr_phb_nvgpu_populate_dt(SpaprPhbState *sphb, void *fdt, int bus_off, | |
160 | Error **errp); | |
161 | void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, void *fdt); | |
162 | void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt, int offset, | |
163 | SpaprPhbState *sphb); | |
fbb4e983 | 164 | #else |
ce2918cb | 165 | static inline bool spapr_phb_eeh_available(SpaprPhbState *sphb) |
c1fa017c DG |
166 | { |
167 | return false; | |
168 | } | |
ce2918cb | 169 | static inline int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb, |
fbb4e983 DG |
170 | unsigned int addr, int option) |
171 | { | |
172 | return RTAS_OUT_HW_ERROR; | |
173 | } | |
ce2918cb | 174 | static inline int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, |
fbb4e983 DG |
175 | int *state) |
176 | { | |
177 | return RTAS_OUT_HW_ERROR; | |
178 | } | |
ce2918cb | 179 | static inline int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option) |
fbb4e983 DG |
180 | { |
181 | return RTAS_OUT_HW_ERROR; | |
182 | } | |
ce2918cb | 183 | static inline int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb) |
fbb4e983 DG |
184 | { |
185 | return RTAS_OUT_HW_ERROR; | |
186 | } | |
187 | static inline void spapr_phb_vfio_reset(DeviceState *qdev) | |
188 | { | |
189 | } | |
ec132efa AK |
190 | static inline void spapr_phb_nvgpu_setup(SpaprPhbState *sphb, Error **errp) |
191 | { | |
192 | } | |
193 | static inline void spapr_phb_nvgpu_free(SpaprPhbState *sphb) | |
194 | { | |
195 | } | |
196 | static inline void spapr_phb_nvgpu_populate_dt(SpaprPhbState *sphb, void *fdt, | |
197 | int bus_off, Error **errp) | |
198 | { | |
199 | } | |
200 | static inline void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, | |
201 | void *fdt) | |
202 | { | |
203 | } | |
204 | static inline void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt, | |
205 | int offset, | |
206 | SpaprPhbState *sphb) | |
207 | { | |
208 | } | |
fbb4e983 DG |
209 | #endif |
210 | ||
ce2918cb | 211 | void spapr_phb_dma_reset(SpaprPhbState *sphb); |
b3162f22 | 212 | |
ce2918cb | 213 | static inline unsigned spapr_phb_windows_supported(SpaprPhbState *sphb) |
ef28b98d GK |
214 | { |
215 | return sphb->ddw_enabled ? SPAPR_PCI_DMA_MAX_WINDOWS : 1; | |
216 | } | |
217 | ||
121d0712 | 218 | #endif /* PCI_HOST_SPAPR_H */ |