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62be3934 PB |
1 | /* |
2 | * Xilinx PCIe host controller emulation. | |
3 | * | |
4 | * Copyright (c) 2016 Imagination Technologies | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef HW_XILINX_PCIE_H | |
21 | #define HW_XILINX_PCIE_H | |
22 | ||
62be3934 PB |
23 | #include "hw/sysbus.h" |
24 | #include "hw/pci/pci.h" | |
791bf3c8 | 25 | #include "hw/pci/pci_bridge.h" |
62be3934 | 26 | #include "hw/pci/pcie_host.h" |
db1015e9 | 27 | #include "qom/object.h" |
62be3934 PB |
28 | |
29 | #define TYPE_XILINX_PCIE_HOST "xilinx-pcie-host" | |
db1015e9 | 30 | typedef struct XilinxPCIEHost XilinxPCIEHost; |
62be3934 PB |
31 | #define XILINX_PCIE_HOST(obj) \ |
32 | OBJECT_CHECK(XilinxPCIEHost, (obj), TYPE_XILINX_PCIE_HOST) | |
33 | ||
34 | #define TYPE_XILINX_PCIE_ROOT "xilinx-pcie-root" | |
db1015e9 | 35 | typedef struct XilinxPCIERoot XilinxPCIERoot; |
62be3934 PB |
36 | #define XILINX_PCIE_ROOT(obj) \ |
37 | OBJECT_CHECK(XilinxPCIERoot, (obj), TYPE_XILINX_PCIE_ROOT) | |
38 | ||
db1015e9 | 39 | struct XilinxPCIERoot { |
62be3934 | 40 | PCIBridge parent_obj; |
db1015e9 | 41 | }; |
62be3934 PB |
42 | |
43 | typedef struct XilinxPCIEInt { | |
44 | uint32_t fifo_reg1; | |
45 | uint32_t fifo_reg2; | |
46 | } XilinxPCIEInt; | |
47 | ||
db1015e9 | 48 | struct XilinxPCIEHost { |
62be3934 PB |
49 | PCIExpressHost parent_obj; |
50 | ||
51 | char name[16]; | |
52 | ||
53 | uint32_t bus_nr; | |
54 | uint64_t cfg_base, cfg_size; | |
55 | uint64_t mmio_base, mmio_size; | |
56 | bool link_up; | |
57 | qemu_irq irq; | |
58 | ||
59 | MemoryRegion mmio, io; | |
60 | ||
61 | XilinxPCIERoot root; | |
62 | ||
63 | uint32_t intr; | |
64 | uint32_t intr_mask; | |
65 | XilinxPCIEInt intr_fifo[16]; | |
66 | unsigned int intr_fifo_r, intr_fifo_w; | |
67 | uint32_t rpscr; | |
db1015e9 | 68 | }; |
62be3934 PB |
69 | |
70 | #endif /* HW_XILINX_PCIE_H */ |