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28ce5ce6 AJ |
1 | /* |
2 | * Copyright (c) 2009 Laurent Vivier | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
5 | * of this software and associated documentation files (the "Software"), to deal | |
6 | * in the Software without restriction, including without limitation the rights | |
7 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
8 | * copies of the Software, and to permit persons to whom the Software is | |
9 | * furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
19 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
20 | * THE SOFTWARE. | |
21 | */ | |
175de524 | 22 | |
cb9c377f | 23 | #ifndef HW_MAC_DBDMA_H |
175de524 | 24 | #define HW_MAC_DBDMA_H |
28ce5ce6 | 25 | |
022c62cb | 26 | #include "exec/memory.h" |
daf015ef | 27 | #include "qemu/iov.h" |
bc9ca595 | 28 | #include "sysemu/dma.h" |
23c5e4ca | 29 | |
b42ec42d AJ |
30 | typedef struct DBDMA_io DBDMA_io; |
31 | ||
862c9280 | 32 | typedef void (*DBDMA_flush)(DBDMA_io *io); |
b42ec42d AJ |
33 | typedef void (*DBDMA_rw)(DBDMA_io *io); |
34 | typedef void (*DBDMA_end)(DBDMA_io *io); | |
35 | struct DBDMA_io { | |
28ce5ce6 AJ |
36 | void *opaque; |
37 | void *channel; | |
a8170e5e | 38 | hwaddr addr; |
28ce5ce6 AJ |
39 | int len; |
40 | int is_last; | |
b42ec42d AJ |
41 | int is_dma_out; |
42 | DBDMA_end dma_end; | |
03ee3b1e AG |
43 | /* DMA is in progress, don't start another one */ |
44 | bool processing; | |
80fc95d8 | 45 | /* unaligned last sector of a request */ |
ac58fe7b MCA |
46 | uint8_t head_remainder[0x200]; |
47 | uint8_t tail_remainder[0x200]; | |
3e300fa6 | 48 | QEMUIOVector iov; |
bc9ca595 MCA |
49 | /* DMA request */ |
50 | void *dma_mem; | |
51 | dma_addr_t dma_len; | |
52 | DMADirection dir; | |
b42ec42d | 53 | }; |
28ce5ce6 | 54 | |
f2f963fd AG |
55 | /* |
56 | * DBDMA control/status registers. All little-endian. | |
57 | */ | |
58 | ||
59 | #define DBDMA_CONTROL 0x00 | |
60 | #define DBDMA_STATUS 0x01 | |
61 | #define DBDMA_CMDPTR_HI 0x02 | |
62 | #define DBDMA_CMDPTR_LO 0x03 | |
63 | #define DBDMA_INTR_SEL 0x04 | |
64 | #define DBDMA_BRANCH_SEL 0x05 | |
65 | #define DBDMA_WAIT_SEL 0x06 | |
66 | #define DBDMA_XFER_MODE 0x07 | |
67 | #define DBDMA_DATA2PTR_HI 0x08 | |
68 | #define DBDMA_DATA2PTR_LO 0x09 | |
69 | #define DBDMA_RES1 0x0A | |
70 | #define DBDMA_ADDRESS_HI 0x0B | |
71 | #define DBDMA_BRANCH_ADDR_HI 0x0C | |
72 | #define DBDMA_RES2 0x0D | |
73 | #define DBDMA_RES3 0x0E | |
74 | #define DBDMA_RES4 0x0F | |
75 | ||
76 | #define DBDMA_REGS 16 | |
77 | #define DBDMA_SIZE (DBDMA_REGS * sizeof(uint32_t)) | |
78 | ||
79 | #define DBDMA_CHANNEL_SHIFT 7 | |
80 | #define DBDMA_CHANNEL_SIZE (1 << DBDMA_CHANNEL_SHIFT) | |
81 | ||
82 | #define DBDMA_CHANNELS (0x1000 >> DBDMA_CHANNEL_SHIFT) | |
83 | ||
84 | /* Bits in control and status registers */ | |
85 | ||
86 | #define RUN 0x8000 | |
87 | #define PAUSE 0x4000 | |
88 | #define FLUSH 0x2000 | |
89 | #define WAKE 0x1000 | |
90 | #define DEAD 0x0800 | |
91 | #define ACTIVE 0x0400 | |
92 | #define BT 0x0100 | |
93 | #define DEVSTAT 0x00ff | |
94 | ||
95 | /* | |
96 | * DBDMA command structure. These fields are all little-endian! | |
97 | */ | |
98 | ||
99 | typedef struct dbdma_cmd { | |
100 | uint16_t req_count; /* requested byte transfer count */ | |
101 | uint16_t command; /* command word (has bit-fields) */ | |
102 | uint32_t phy_addr; /* physical data address */ | |
103 | uint32_t cmd_dep; /* command-dependent field */ | |
104 | uint16_t res_count; /* residual count after completion */ | |
105 | uint16_t xfer_status; /* transfer status */ | |
106 | } dbdma_cmd; | |
107 | ||
108 | /* DBDMA command values in command field */ | |
109 | ||
110 | #define COMMAND_MASK 0xf000 | |
111 | #define OUTPUT_MORE 0x0000 /* transfer memory data to stream */ | |
112 | #define OUTPUT_LAST 0x1000 /* ditto followed by end marker */ | |
113 | #define INPUT_MORE 0x2000 /* transfer stream data to memory */ | |
114 | #define INPUT_LAST 0x3000 /* ditto, expect end marker */ | |
115 | #define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */ | |
116 | #define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */ | |
117 | #define DBDMA_NOP 0x6000 /* do nothing */ | |
118 | #define DBDMA_STOP 0x7000 /* suspend processing */ | |
119 | ||
120 | /* Key values in command field */ | |
121 | ||
122 | #define KEY_MASK 0x0700 | |
123 | #define KEY_STREAM0 0x0000 /* usual data stream */ | |
124 | #define KEY_STREAM1 0x0100 /* control/status stream */ | |
125 | #define KEY_STREAM2 0x0200 /* device-dependent stream */ | |
126 | #define KEY_STREAM3 0x0300 /* device-dependent stream */ | |
127 | #define KEY_STREAM4 0x0400 /* reserved */ | |
128 | #define KEY_REGS 0x0500 /* device register space */ | |
129 | #define KEY_SYSTEM 0x0600 /* system memory-mapped space */ | |
130 | #define KEY_DEVICE 0x0700 /* device memory-mapped space */ | |
131 | ||
132 | /* Interrupt control values in command field */ | |
133 | ||
134 | #define INTR_MASK 0x0030 | |
135 | #define INTR_NEVER 0x0000 /* don't interrupt */ | |
136 | #define INTR_IFSET 0x0010 /* intr if condition bit is 1 */ | |
137 | #define INTR_IFCLR 0x0020 /* intr if condition bit is 0 */ | |
138 | #define INTR_ALWAYS 0x0030 /* always interrupt */ | |
139 | ||
140 | /* Branch control values in command field */ | |
141 | ||
142 | #define BR_MASK 0x000c | |
143 | #define BR_NEVER 0x0000 /* don't branch */ | |
144 | #define BR_IFSET 0x0004 /* branch if condition bit is 1 */ | |
145 | #define BR_IFCLR 0x0008 /* branch if condition bit is 0 */ | |
146 | #define BR_ALWAYS 0x000c /* always branch */ | |
147 | ||
148 | /* Wait control values in command field */ | |
149 | ||
150 | #define WAIT_MASK 0x0003 | |
151 | #define WAIT_NEVER 0x0000 /* don't wait */ | |
152 | #define WAIT_IFSET 0x0001 /* wait if condition bit is 1 */ | |
153 | #define WAIT_IFCLR 0x0002 /* wait if condition bit is 0 */ | |
154 | #define WAIT_ALWAYS 0x0003 /* always wait */ | |
155 | ||
156 | typedef struct DBDMA_channel { | |
157 | int channel; | |
158 | uint32_t regs[DBDMA_REGS]; | |
159 | qemu_irq irq; | |
160 | DBDMA_io io; | |
161 | DBDMA_rw rw; | |
162 | DBDMA_flush flush; | |
163 | dbdma_cmd current; | |
f2f963fd AG |
164 | } DBDMA_channel; |
165 | ||
166 | typedef struct { | |
167 | MemoryRegion mem; | |
168 | DBDMA_channel channels[DBDMA_CHANNELS]; | |
d2f0ce21 | 169 | QEMUBH *bh; |
f2f963fd AG |
170 | } DBDMAState; |
171 | ||
172 | /* Externally callable functions */ | |
28ce5ce6 AJ |
173 | |
174 | void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq, | |
862c9280 | 175 | DBDMA_rw rw, DBDMA_flush flush, |
28ce5ce6 | 176 | void *opaque); |
d1e562de | 177 | void DBDMA_kick(DBDMAState *dbdma); |
23c5e4ca | 178 | void* DBDMA_init (MemoryRegion **dbdma_mem); |
cb9c377f PB |
179 | |
180 | #endif |