[mirror_qemu.git] / include / hw / ppc / mac_dbdma.h

/*
 * Copyright (c) 2009 Laurent Vivier
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#ifndef HW_MAC_DBDMA_H
#define HW_MAC_DBDMA_H

#include "exec/memory.h"
#include "qemu/iov.h"
#include "sysemu/dma.h"
#include "hw/sysbus.h"
#include "qom/object.h"

typedef struct DBDMA_io DBDMA_io;

typedef void (*DBDMA_flush)(DBDMA_io *io);
typedef void (*DBDMA_rw)(DBDMA_io *io);
typedef void (*DBDMA_end)(DBDMA_io *io);
struct DBDMA_io {
    void *opaque;
    void *channel;
    hwaddr addr;
    int len;
    int is_last;
    int is_dma_out;
    DBDMA_end dma_end;
    /* DMA is in progress, don't start another one */
    bool processing;
    /* DMA request */
    void *dma_mem;
    dma_addr_t dma_len;
    DMADirection dir;
};

/*
 * DBDMA control/status registers.  All little-endian.
 */

#define DBDMA_CONTROL         0x00
#define DBDMA_STATUS          0x01
#define DBDMA_CMDPTR_HI       0x02
#define DBDMA_CMDPTR_LO       0x03
#define DBDMA_INTR_SEL        0x04
#define DBDMA_BRANCH_SEL      0x05
#define DBDMA_WAIT_SEL        0x06
#define DBDMA_XFER_MODE       0x07
#define DBDMA_DATA2PTR_HI     0x08
#define DBDMA_DATA2PTR_LO     0x09
#define DBDMA_RES1            0x0A
#define DBDMA_ADDRESS_HI      0x0B
#define DBDMA_BRANCH_ADDR_HI  0x0C
#define DBDMA_RES2            0x0D
#define DBDMA_RES3            0x0E
#define DBDMA_RES4            0x0F

#define DBDMA_REGS            16
#define DBDMA_SIZE            (DBDMA_REGS * sizeof(uint32_t))

#define DBDMA_CHANNEL_SHIFT   7
#define DBDMA_CHANNEL_SIZE    (1 << DBDMA_CHANNEL_SHIFT)

#define DBDMA_CHANNELS        (0x1000 >> DBDMA_CHANNEL_SHIFT)

/* Bits in control and status registers */

#define RUN        0x8000
#define PAUSE      0x4000
#define FLUSH      0x2000
#define WAKE       0x1000
#define DEAD       0x0800
#define ACTIVE     0x0400
#define BT         0x0100
#define DEVSTAT    0x00ff

/*
 * DBDMA command structure.  These fields are all little-endian!
 */

typedef struct dbdma_cmd {
    uint16_t req_count;          /* requested byte transfer count */
    uint16_t command;            /* command word (has bit-fields) */
    uint32_t phy_addr;           /* physical data address */
    uint32_t cmd_dep;            /* command-dependent field */
    uint16_t res_count;          /* residual count after completion */
    uint16_t xfer_status;        /* transfer status */
} dbdma_cmd;

/* DBDMA command values in command field */

#define COMMAND_MASK    0xf000
#define OUTPUT_MORE     0x0000        /* transfer memory data to stream */
#define OUTPUT_LAST     0x1000        /* ditto followed by end marker */
#define INPUT_MORE      0x2000        /* transfer stream data to memory */
#define INPUT_LAST      0x3000        /* ditto, expect end marker */
#define STORE_WORD      0x4000        /* write word (4 bytes) to device reg */
#define LOAD_WORD       0x5000        /* read word (4 bytes) from device reg */
#define DBDMA_NOP       0x6000        /* do nothing */
#define DBDMA_STOP      0x7000        /* suspend processing */

/* Key values in command field */

#define KEY_MASK        0x0700
#define KEY_STREAM0     0x0000        /* usual data stream */
#define KEY_STREAM1     0x0100        /* control/status stream */
#define KEY_STREAM2     0x0200        /* device-dependent stream */
#define KEY_STREAM3     0x0300        /* device-dependent stream */
#define KEY_STREAM4     0x0400        /* reserved */
#define KEY_REGS        0x0500        /* device register space */
#define KEY_SYSTEM      0x0600        /* system memory-mapped space */
#define KEY_DEVICE      0x0700        /* device memory-mapped space */

/* Interrupt control values in command field */

#define INTR_MASK       0x0030
#define INTR_NEVER      0x0000        /* don't interrupt */
#define INTR_IFSET      0x0010        /* intr if condition bit is 1 */
#define INTR_IFCLR      0x0020        /* intr if condition bit is 0 */
#define INTR_ALWAYS     0x0030        /* always interrupt */

/* Branch control values in command field */

#define BR_MASK         0x000c
#define BR_NEVER        0x0000        /* don't branch */
#define BR_IFSET        0x0004        /* branch if condition bit is 1 */
#define BR_IFCLR        0x0008        /* branch if condition bit is 0 */
#define BR_ALWAYS       0x000c        /* always branch */

/* Wait control values in command field */

#define WAIT_MASK       0x0003
#define WAIT_NEVER      0x0000        /* don't wait */
#define WAIT_IFSET      0x0001        /* wait if condition bit is 1 */
#define WAIT_IFCLR      0x0002        /* wait if condition bit is 0 */
#define WAIT_ALWAYS     0x0003        /* always wait */

typedef struct DBDMA_channel {
    int channel;
    uint32_t regs[DBDMA_REGS];
    qemu_irq irq;
    DBDMA_io io;
    DBDMA_rw rw;
    DBDMA_flush flush;
    dbdma_cmd current;
} DBDMA_channel;

struct DBDMAState {
    SysBusDevice parent_obj;

    MemoryRegion mem;
    DBDMA_channel channels[DBDMA_CHANNELS];
    QEMUBH *bh;
};
typedef struct DBDMAState DBDMAState;

/* Externally callable functions */

void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
                            DBDMA_rw rw, DBDMA_flush flush,
                            void *opaque);
void DBDMA_kick(DBDMAState *dbdma);

#define TYPE_MAC_DBDMA "mac-dbdma"
DECLARE_INSTANCE_CHECKER(DBDMAState, MAC_DBDMA,
                         TYPE_MAC_DBDMA)

#endif
Commit	Line	Data
28ce5ce6 AJ	1	/*
	2	* Copyright (c) 2009 Laurent Vivier
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a copy
	5	* of this software and associated documentation files (the "Software"), to deal
	6	* in the Software without restriction, including without limitation the rights
	7	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	8	* copies of the Software, and to permit persons to whom the Software is
	9	* furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	19	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	20	* THE SOFTWARE.
	21	*/
175de524	22
cb9c377f	23	#ifndef HW_MAC_DBDMA_H
175de524	24	#define HW_MAC_DBDMA_H
28ce5ce6	25
022c62cb	26	#include "exec/memory.h"
daf015ef	27	#include "qemu/iov.h"
bc9ca595	28	#include "sysemu/dma.h"
1d27f351	29	#include "hw/sysbus.h"
db1015e9	30	#include "qom/object.h"
23c5e4ca	31
b42ec42d AJ	32	typedef struct DBDMA_io DBDMA_io;
b42ec42d AJ	33
862c9280	34	typedef void (DBDMA_flush)(DBDMA_io io);
b42ec42d AJ	35	typedef void (DBDMA_rw)(DBDMA_io io);
	36	typedef void (DBDMA_end)(DBDMA_io io);
	37	struct DBDMA_io {
28ce5ce6 AJ	38	void *opaque;
28ce5ce6 AJ	39	void *channel;
a8170e5e	40	hwaddr addr;
28ce5ce6 AJ	41	int len;
28ce5ce6 AJ	42	int is_last;
b42ec42d AJ	43	int is_dma_out;
b42ec42d AJ	44	DBDMA_end dma_end;
03ee3b1e AG	45	/* DMA is in progress, don't start another one */
03ee3b1e AG	46	bool processing;
bc9ca595 MCA	47	/* DMA request */
	48	void *dma_mem;
	49	dma_addr_t dma_len;
	50	DMADirection dir;
b42ec42d	51	};
28ce5ce6	52
f2f963fd AG	53	/*
	54	* DBDMA control/status registers. All little-endian.
	55	*/
	56
	57	#define DBDMA_CONTROL 0x00
	58	#define DBDMA_STATUS 0x01
	59	#define DBDMA_CMDPTR_HI 0x02
	60	#define DBDMA_CMDPTR_LO 0x03
	61	#define DBDMA_INTR_SEL 0x04
	62	#define DBDMA_BRANCH_SEL 0x05
	63	#define DBDMA_WAIT_SEL 0x06
	64	#define DBDMA_XFER_MODE 0x07
	65	#define DBDMA_DATA2PTR_HI 0x08
	66	#define DBDMA_DATA2PTR_LO 0x09
	67	#define DBDMA_RES1 0x0A
	68	#define DBDMA_ADDRESS_HI 0x0B
	69	#define DBDMA_BRANCH_ADDR_HI 0x0C
	70	#define DBDMA_RES2 0x0D
	71	#define DBDMA_RES3 0x0E
	72	#define DBDMA_RES4 0x0F
	73
	74	#define DBDMA_REGS 16
	75	#define DBDMA_SIZE (DBDMA_REGS * sizeof(uint32_t))
	76
	77	#define DBDMA_CHANNEL_SHIFT 7
	78	#define DBDMA_CHANNEL_SIZE (1 << DBDMA_CHANNEL_SHIFT)
	79
	80	#define DBDMA_CHANNELS (0x1000 >> DBDMA_CHANNEL_SHIFT)
	81
	82	/* Bits in control and status registers */
	83
	84	#define RUN 0x8000
	85	#define PAUSE 0x4000
	86	#define FLUSH 0x2000
	87	#define WAKE 0x1000
	88	#define DEAD 0x0800
	89	#define ACTIVE 0x0400
	90	#define BT 0x0100
	91	#define DEVSTAT 0x00ff
	92
	93	/*
	94	* DBDMA command structure. These fields are all little-endian!
	95	*/
	96
	97	typedef struct dbdma_cmd {
	98	uint16_t req_count; /* requested byte transfer count */
	99	uint16_t command; /* command word (has bit-fields) */
	100	uint32_t phy_addr; /* physical data address */
	101	uint32_t cmd_dep; /* command-dependent field */
	102	uint16_t res_count; /* residual count after completion */
	103	uint16_t xfer_status; /* transfer status */
	104	} dbdma_cmd;
	105
	106	/* DBDMA command values in command field */
	107
	108	#define COMMAND_MASK 0xf000
	109	#define OUTPUT_MORE 0x0000 /* transfer memory data to stream */
	110	#define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
	111	#define INPUT_MORE 0x2000 /* transfer stream data to memory */
	112	#define INPUT_LAST 0x3000 /* ditto, expect end marker */
	113	#define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
	114	#define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
	115	#define DBDMA_NOP 0x6000 /* do nothing */
	116	#define DBDMA_STOP 0x7000 /* suspend processing */
117
118	/* Key values in command field */
119
120	#define KEY_MASK 0x0700
121	#define KEY_STREAM0 0x0000 /* usual data stream */
122	#define KEY_STREAM1 0x0100 /* control/status stream */
123	#define KEY_STREAM2 0x0200 /* device-dependent stream */
124	#define KEY_STREAM3 0x0300 /* device-dependent stream */
125	#define KEY_STREAM4 0x0400 /* reserved */
126	#define KEY_REGS 0x0500 /* device register space */
127	#define KEY_SYSTEM 0x0600 /* system memory-mapped space */
128	#define KEY_DEVICE 0x0700 /* device memory-mapped space */
129
130	/* Interrupt control values in command field */
131
132	#define INTR_MASK 0x0030
133	#define INTR_NEVER 0x0000 /* don't interrupt */
134	#define INTR_IFSET 0x0010 /* intr if condition bit is 1 */
135	#define INTR_IFCLR 0x0020 /* intr if condition bit is 0 */
136	#define INTR_ALWAYS 0x0030 /* always interrupt */
137
138	/* Branch control values in command field */
139
140	#define BR_MASK 0x000c
141	#define BR_NEVER 0x0000 /* don't branch */
142	#define BR_IFSET 0x0004 /* branch if condition bit is 1 */
143	#define BR_IFCLR 0x0008 /* branch if condition bit is 0 */
144	#define BR_ALWAYS 0x000c /* always branch */
145
146	/* Wait control values in command field */
147
148	#define WAIT_MASK 0x0003
149	#define WAIT_NEVER 0x0000 /* don't wait */
150	#define WAIT_IFSET 0x0001 /* wait if condition bit is 1 */
151	#define WAIT_IFCLR 0x0002 /* wait if condition bit is 0 */
152	#define WAIT_ALWAYS 0x0003 /* always wait */
153
154	typedef struct DBDMA_channel {
155	int channel;
156	uint32_t regs[DBDMA_REGS];
157	qemu_irq irq;
158	DBDMA_io io;
159	DBDMA_rw rw;
160	DBDMA_flush flush;
161	dbdma_cmd current;
f2f963fd AG	162	} DBDMA_channel;
f2f963fd AG	163
db1015e9	164	struct DBDMAState {
1d27f351 MCA	165	SysBusDevice parent_obj;
1d27f351 MCA	166
f2f963fd AG	167	MemoryRegion mem;
f2f963fd AG	168	DBDMA_channel channels[DBDMA_CHANNELS];
d2f0ce21	169	QEMUBH *bh;
db1015e9 EH	170	};
db1015e9 EH	171	typedef struct DBDMAState DBDMAState;
f2f963fd AG	172
f2f963fd AG	173	/* Externally callable functions */
28ce5ce6 AJ	174
28ce5ce6 AJ	175	void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
862c9280	176	DBDMA_rw rw, DBDMA_flush flush,
28ce5ce6	177	void *opaque);
d1e562de	178	void DBDMA_kick(DBDMAState *dbdma);
cb9c377f	179
1d27f351	180	#define TYPE_MAC_DBDMA "mac-dbdma"
8110fa1d EH	181	DECLARE_INSTANCE_CHECKER(DBDMAState, MAC_DBDMA,
8110fa1d EH	182	TYPE_MAC_DBDMA)
1d27f351	183
cb9c377f	184	#endif