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1 | /* |
2 | * QEMU PowerPC PowerNV various definitions | |
3 | * | |
4 | * Copyright (c) 2014-2016 BenH, IBM Corporation. | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #ifndef _PPC_PNV_H | |
20 | #define _PPC_PNV_H | |
21 | ||
22 | #include "hw/boards.h" | |
e997040e | 23 | #include "hw/sysbus.h" |
a3980bf5 | 24 | #include "hw/ppc/pnv_lpc.h" |
54f59d78 | 25 | #include "hw/ppc/pnv_psi.h" |
0722d05a | 26 | #include "hw/ppc/pnv_occ.h" |
e997040e CLG |
27 | |
28 | #define TYPE_PNV_CHIP "powernv-chip" | |
29 | #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) | |
30 | #define PNV_CHIP_CLASS(klass) \ | |
31 | OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP) | |
32 | #define PNV_CHIP_GET_CLASS(obj) \ | |
33 | OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP) | |
34 | ||
35 | typedef enum PnvChipType { | |
36 | PNV_CHIP_POWER8E, /* AKA Murano (default) */ | |
37 | PNV_CHIP_POWER8, /* AKA Venice */ | |
38 | PNV_CHIP_POWER8NVL, /* AKA Naples */ | |
39 | PNV_CHIP_POWER9, /* AKA Nimbus */ | |
40 | } PnvChipType; | |
41 | ||
42 | typedef struct PnvChip { | |
43 | /*< private >*/ | |
44 | SysBusDevice parent_obj; | |
45 | ||
46 | /*< public >*/ | |
47 | uint32_t chip_id; | |
48 | uint64_t ram_start; | |
49 | uint64_t ram_size; | |
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50 | |
51 | uint32_t nr_cores; | |
52 | uint64_t cores_mask; | |
d2fd9612 | 53 | void *cores; |
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54 | |
55 | hwaddr xscom_base; | |
56 | MemoryRegion xscom_mmio; | |
57 | MemoryRegion xscom; | |
58 | AddressSpace xscom_as; | |
bf5615e7 | 59 | MemoryRegion icp_mmio; |
a3980bf5 BH |
60 | |
61 | PnvLpcController lpc; | |
54f59d78 | 62 | PnvPsi psi; |
0722d05a | 63 | PnvOCC occ; |
e997040e CLG |
64 | } PnvChip; |
65 | ||
66 | typedef struct PnvChipClass { | |
67 | /*< private >*/ | |
68 | SysBusDeviceClass parent_class; | |
69 | ||
70 | /*< public >*/ | |
71 | const char *cpu_model; | |
72 | PnvChipType chip_type; | |
73 | uint64_t chip_cfam_id; | |
397a79e7 | 74 | uint64_t cores_mask; |
631adaff | 75 | |
967b7523 | 76 | hwaddr xscom_base; |
ad521238 | 77 | hwaddr xscom_core_base; |
967b7523 | 78 | |
631adaff | 79 | uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); |
e997040e CLG |
80 | } PnvChipClass; |
81 | ||
82 | #define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E" | |
83 | #define PNV_CHIP_POWER8E(obj) \ | |
84 | OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E) | |
85 | ||
86 | #define TYPE_PNV_CHIP_POWER8 TYPE_PNV_CHIP "-POWER8" | |
87 | #define PNV_CHIP_POWER8(obj) \ | |
88 | OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8) | |
89 | ||
90 | #define TYPE_PNV_CHIP_POWER8NVL TYPE_PNV_CHIP "-POWER8NVL" | |
91 | #define PNV_CHIP_POWER8NVL(obj) \ | |
92 | OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL) | |
93 | ||
94 | #define TYPE_PNV_CHIP_POWER9 TYPE_PNV_CHIP "-POWER9" | |
95 | #define PNV_CHIP_POWER9(obj) \ | |
96 | OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) | |
97 | ||
98 | /* | |
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99 | * This generates a HW chip id depending on an index, as found on a |
100 | * two socket system with dual chip modules : | |
e997040e CLG |
101 | * |
102 | * 0x0, 0x1, 0x10, 0x11 | |
103 | * | |
104 | * 4 chips should be the maximum | |
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105 | * |
106 | * TODO: use a machine property to define the chip ids | |
e997040e CLG |
107 | */ |
108 | #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) | |
9e933f4a | 109 | |
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110 | /* |
111 | * Converts back a HW chip id to an index. This is useful to calculate | |
112 | * the MMIO addresses of some controllers which depend on the chip id. | |
113 | */ | |
114 | #define PNV_CHIP_INDEX(chip) \ | |
115 | (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) | |
116 | ||
9e933f4a BH |
117 | #define TYPE_POWERNV_MACHINE MACHINE_TYPE_NAME("powernv") |
118 | #define POWERNV_MACHINE(obj) \ | |
119 | OBJECT_CHECK(PnvMachineState, (obj), TYPE_POWERNV_MACHINE) | |
120 | ||
121 | typedef struct PnvMachineState { | |
122 | /*< private >*/ | |
123 | MachineState parent_obj; | |
124 | ||
125 | uint32_t initrd_base; | |
126 | long initrd_size; | |
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127 | |
128 | uint32_t num_chips; | |
129 | PnvChip **chips; | |
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130 | |
131 | ISABus *isa_bus; | |
54f59d78 | 132 | uint32_t cpld_irqstate; |
9e933f4a BH |
133 | } PnvMachineState; |
134 | ||
135 | #define PNV_FDT_ADDR 0x01000000 | |
d2fd9612 | 136 | #define PNV_TIMEBASE_FREQ 512000000ULL |
9e933f4a | 137 | |
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138 | /* |
139 | * POWER8 MMIO base addresses | |
140 | */ | |
141 | #define PNV_XSCOM_SIZE 0x800000000ull | |
142 | #define PNV_XSCOM_BASE(chip) \ | |
143 | (chip->xscom_base + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) | |
144 | ||
bf5615e7 CLG |
145 | /* |
146 | * XSCOM 0x20109CA defines the ICP BAR: | |
147 | * | |
148 | * 0:29 : bits 14 to 43 of address to define 1 MB region. | |
149 | * 30 : 1 to enable ICP to receive loads/stores against its BAR region | |
150 | * 31:63 : Constant 0 | |
151 | * | |
152 | * Usually defined as : | |
153 | * | |
154 | * 0xffffe00200000000 -> 0x0003ffff80000000 | |
155 | * 0xffffe00600000000 -> 0x0003ffff80100000 | |
156 | * 0xffffe02200000000 -> 0x0003ffff80800000 | |
157 | * 0xffffe02600000000 -> 0x0003ffff80900000 | |
158 | */ | |
159 | #define PNV_ICP_SIZE 0x0000000000100000ull | |
160 | #define PNV_ICP_BASE(chip) \ | |
161 | (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE) | |
162 | ||
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163 | |
164 | #define PNV_PSIHB_SIZE 0x0000000000100000ull | |
165 | #define PNV_PSIHB_BASE(chip) \ | |
166 | (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE) | |
167 | ||
168 | #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull | |
169 | #define PNV_PSIHB_FSP_BASE(chip) \ | |
170 | (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \ | |
171 | PNV_PSIHB_FSP_SIZE) | |
172 | ||
9e933f4a | 173 | #endif /* _PPC_PNV_H */ |