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9e933f4a BH |
1 | /* |
2 | * QEMU PowerPC PowerNV various definitions | |
3 | * | |
4 | * Copyright (c) 2014-2016 BenH, IBM Corporation. | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #ifndef _PPC_PNV_H | |
20 | #define _PPC_PNV_H | |
21 | ||
22 | #include "hw/boards.h" | |
e997040e | 23 | #include "hw/sysbus.h" |
eaf87a39 | 24 | #include "hw/ipmi/ipmi.h" |
a3980bf5 | 25 | #include "hw/ppc/pnv_lpc.h" |
54f59d78 | 26 | #include "hw/ppc/pnv_psi.h" |
0722d05a | 27 | #include "hw/ppc/pnv_occ.h" |
2dfa91a2 | 28 | #include "hw/ppc/pnv_xive.h" |
5dad902c | 29 | #include "hw/ppc/pnv_core.h" |
e997040e | 30 | |
b168a138 | 31 | #define TYPE_PNV_CHIP "pnv-chip" |
e997040e CLG |
32 | #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) |
33 | #define PNV_CHIP_CLASS(klass) \ | |
34 | OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP) | |
35 | #define PNV_CHIP_GET_CLASS(obj) \ | |
36 | OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP) | |
37 | ||
38 | typedef enum PnvChipType { | |
39 | PNV_CHIP_POWER8E, /* AKA Murano (default) */ | |
40 | PNV_CHIP_POWER8, /* AKA Venice */ | |
41 | PNV_CHIP_POWER8NVL, /* AKA Naples */ | |
42 | PNV_CHIP_POWER9, /* AKA Nimbus */ | |
43 | } PnvChipType; | |
44 | ||
45 | typedef struct PnvChip { | |
46 | /*< private >*/ | |
47 | SysBusDevice parent_obj; | |
48 | ||
49 | /*< public >*/ | |
50 | uint32_t chip_id; | |
51 | uint64_t ram_start; | |
52 | uint64_t ram_size; | |
397a79e7 CLG |
53 | |
54 | uint32_t nr_cores; | |
55 | uint64_t cores_mask; | |
d2fd9612 | 56 | void *cores; |
967b7523 CLG |
57 | |
58 | hwaddr xscom_base; | |
59 | MemoryRegion xscom_mmio; | |
60 | MemoryRegion xscom; | |
61 | AddressSpace xscom_as; | |
64d011d5 CLG |
62 | |
63 | gchar *dt_isa_nodename; | |
77864267 CLG |
64 | } PnvChip; |
65 | ||
66 | #define TYPE_PNV8_CHIP "pnv8-chip" | |
67 | #define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP) | |
68 | ||
69 | typedef struct Pnv8Chip { | |
70 | /*< private >*/ | |
71 | PnvChip parent_obj; | |
72 | ||
73 | /*< public >*/ | |
bf5615e7 | 74 | MemoryRegion icp_mmio; |
a3980bf5 BH |
75 | |
76 | PnvLpcController lpc; | |
ae856055 | 77 | Pnv8Psi psi; |
0722d05a | 78 | PnvOCC occ; |
77864267 CLG |
79 | } Pnv8Chip; |
80 | ||
81 | #define TYPE_PNV9_CHIP "pnv9-chip" | |
82 | #define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP) | |
83 | ||
84 | typedef struct Pnv9Chip { | |
85 | /*< private >*/ | |
86 | PnvChip parent_obj; | |
87 | ||
88 | /*< public >*/ | |
2dfa91a2 | 89 | PnvXive xive; |
c38536bc | 90 | Pnv9Psi psi; |
15376c66 | 91 | PnvLpcController lpc; |
6598a70d | 92 | PnvOCC occ; |
5dad902c CLG |
93 | |
94 | uint32_t nr_quads; | |
95 | PnvQuad *quads; | |
77864267 | 96 | } Pnv9Chip; |
e997040e CLG |
97 | |
98 | typedef struct PnvChipClass { | |
99 | /*< private >*/ | |
100 | SysBusDeviceClass parent_class; | |
101 | ||
102 | /*< public >*/ | |
e997040e CLG |
103 | PnvChipType chip_type; |
104 | uint64_t chip_cfam_id; | |
397a79e7 | 105 | uint64_t cores_mask; |
631adaff | 106 | |
967b7523 CLG |
107 | hwaddr xscom_base; |
108 | ||
77864267 CLG |
109 | DeviceRealize parent_realize; |
110 | ||
631adaff | 111 | uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); |
8fa1f4ef | 112 | void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); |
04026890 | 113 | ISABus *(*isa_create)(PnvChip *chip, Error **errp); |
eb859a27 | 114 | void (*dt_populate)(PnvChip *chip, void *fdt); |
d8e4aad5 | 115 | void (*pic_print_info)(PnvChip *chip, Monitor *mon); |
e997040e CLG |
116 | } PnvChipClass; |
117 | ||
7fd544d8 IM |
118 | #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP |
119 | #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX | |
120 | ||
121 | #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") | |
e997040e CLG |
122 | #define PNV_CHIP_POWER8E(obj) \ |
123 | OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E) | |
124 | ||
7fd544d8 | 125 | #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") |
e997040e CLG |
126 | #define PNV_CHIP_POWER8(obj) \ |
127 | OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8) | |
128 | ||
7fd544d8 | 129 | #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") |
e997040e CLG |
130 | #define PNV_CHIP_POWER8NVL(obj) \ |
131 | OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL) | |
132 | ||
7fd544d8 | 133 | #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") |
e997040e CLG |
134 | #define PNV_CHIP_POWER9(obj) \ |
135 | OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) | |
136 | ||
137 | /* | |
5509db4a CLG |
138 | * This generates a HW chip id depending on an index, as found on a |
139 | * two socket system with dual chip modules : | |
e997040e CLG |
140 | * |
141 | * 0x0, 0x1, 0x10, 0x11 | |
142 | * | |
143 | * 4 chips should be the maximum | |
5509db4a CLG |
144 | * |
145 | * TODO: use a machine property to define the chip ids | |
e997040e CLG |
146 | */ |
147 | #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) | |
9e933f4a | 148 | |
5509db4a CLG |
149 | /* |
150 | * Converts back a HW chip id to an index. This is useful to calculate | |
151 | * the MMIO addresses of some controllers which depend on the chip id. | |
152 | */ | |
153 | #define PNV_CHIP_INDEX(chip) \ | |
154 | (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) | |
155 | ||
b168a138 CLG |
156 | #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") |
157 | #define PNV_MACHINE(obj) \ | |
158 | OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE) | |
9e933f4a BH |
159 | |
160 | typedef struct PnvMachineState { | |
161 | /*< private >*/ | |
162 | MachineState parent_obj; | |
163 | ||
164 | uint32_t initrd_base; | |
165 | long initrd_size; | |
e997040e CLG |
166 | |
167 | uint32_t num_chips; | |
168 | PnvChip **chips; | |
3495b6b6 CLG |
169 | |
170 | ISABus *isa_bus; | |
54f59d78 | 171 | uint32_t cpld_irqstate; |
aeaef83d CLG |
172 | |
173 | IPMIBmc *bmc; | |
bce0b691 | 174 | Notifier powerdown_notifier; |
9e933f4a BH |
175 | } PnvMachineState; |
176 | ||
b3b066e9 CLG |
177 | static inline bool pnv_chip_is_power9(const PnvChip *chip) |
178 | { | |
179 | return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER9; | |
180 | } | |
181 | ||
182 | static inline bool pnv_is_power9(PnvMachineState *pnv) | |
183 | { | |
184 | return pnv_chip_is_power9(pnv->chips[0]); | |
185 | } | |
186 | ||
9e933f4a | 187 | #define PNV_FDT_ADDR 0x01000000 |
d2fd9612 | 188 | #define PNV_TIMEBASE_FREQ 512000000ULL |
9e933f4a | 189 | |
aeaef83d CLG |
190 | /* |
191 | * BMC helpers | |
192 | */ | |
b168a138 | 193 | void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); |
bce0b691 | 194 | void pnv_bmc_powerdown(IPMIBmc *bmc); |
aeaef83d | 195 | |
967b7523 CLG |
196 | /* |
197 | * POWER8 MMIO base addresses | |
198 | */ | |
199 | #define PNV_XSCOM_SIZE 0x800000000ull | |
200 | #define PNV_XSCOM_BASE(chip) \ | |
201 | (chip->xscom_base + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) | |
202 | ||
bf5615e7 CLG |
203 | /* |
204 | * XSCOM 0x20109CA defines the ICP BAR: | |
205 | * | |
206 | * 0:29 : bits 14 to 43 of address to define 1 MB region. | |
207 | * 30 : 1 to enable ICP to receive loads/stores against its BAR region | |
208 | * 31:63 : Constant 0 | |
209 | * | |
210 | * Usually defined as : | |
211 | * | |
212 | * 0xffffe00200000000 -> 0x0003ffff80000000 | |
213 | * 0xffffe00600000000 -> 0x0003ffff80100000 | |
214 | * 0xffffe02200000000 -> 0x0003ffff80800000 | |
215 | * 0xffffe02600000000 -> 0x0003ffff80900000 | |
216 | */ | |
217 | #define PNV_ICP_SIZE 0x0000000000100000ull | |
218 | #define PNV_ICP_BASE(chip) \ | |
219 | (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE) | |
220 | ||
54f59d78 CLG |
221 | |
222 | #define PNV_PSIHB_SIZE 0x0000000000100000ull | |
223 | #define PNV_PSIHB_BASE(chip) \ | |
224 | (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE) | |
225 | ||
226 | #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull | |
227 | #define PNV_PSIHB_FSP_BASE(chip) \ | |
228 | (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \ | |
229 | PNV_PSIHB_FSP_SIZE) | |
230 | ||
2dfa91a2 CLG |
231 | /* |
232 | * POWER9 MMIO base addresses | |
233 | */ | |
234 | #define PNV9_CHIP_BASE(chip, base) \ | |
235 | ((base) + ((uint64_t) (chip)->chip_id << 42)) | |
236 | ||
237 | #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull | |
238 | #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull) | |
239 | ||
240 | #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull | |
241 | #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull) | |
242 | ||
15376c66 CLG |
243 | #define PNV9_LPCM_SIZE 0x0000000100000000ull |
244 | #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull) | |
245 | ||
c38536bc CLG |
246 | #define PNV9_PSIHB_SIZE 0x0000000000100000ull |
247 | #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull) | |
248 | ||
2dfa91a2 CLG |
249 | #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull |
250 | #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull) | |
251 | ||
252 | #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull | |
253 | #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull) | |
254 | ||
c38536bc CLG |
255 | #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull |
256 | #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull) | |
2dfa91a2 | 257 | |
9e933f4a | 258 | #endif /* _PPC_PNV_H */ |