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9e933f4a BH |
1 | /* |
2 | * QEMU PowerPC PowerNV various definitions | |
3 | * | |
4 | * Copyright (c) 2014-2016 BenH, IBM Corporation. | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
a8b991b5 MA |
19 | |
20 | #ifndef PPC_PNV_H | |
21 | #define PPC_PNV_H | |
9e933f4a BH |
22 | |
23 | #include "hw/boards.h" | |
e997040e | 24 | #include "hw/sysbus.h" |
eaf87a39 | 25 | #include "hw/ipmi/ipmi.h" |
a3980bf5 | 26 | #include "hw/ppc/pnv_lpc.h" |
35dde576 | 27 | #include "hw/ppc/pnv_pnor.h" |
54f59d78 | 28 | #include "hw/ppc/pnv_psi.h" |
0722d05a | 29 | #include "hw/ppc/pnv_occ.h" |
3887d241 | 30 | #include "hw/ppc/pnv_homer.h" |
2dfa91a2 | 31 | #include "hw/ppc/pnv_xive.h" |
5dad902c | 32 | #include "hw/ppc/pnv_core.h" |
9ae1329e | 33 | #include "hw/pci-host/pnv_phb3.h" |
4f9924c4 | 34 | #include "hw/pci-host/pnv_phb4.h" |
db1015e9 | 35 | #include "qom/object.h" |
e997040e | 36 | |
b168a138 | 37 | #define TYPE_PNV_CHIP "pnv-chip" |
db1015e9 EH |
38 | typedef struct PnvChip PnvChip; |
39 | typedef struct PnvChipClass PnvChipClass; | |
8110fa1d EH |
40 | DECLARE_OBJ_CHECKERS(PnvChip, PnvChipClass, |
41 | PNV_CHIP, TYPE_PNV_CHIP) | |
e997040e | 42 | |
db1015e9 | 43 | struct PnvChip { |
e997040e CLG |
44 | /*< private >*/ |
45 | SysBusDevice parent_obj; | |
46 | ||
47 | /*< public >*/ | |
48 | uint32_t chip_id; | |
49 | uint64_t ram_start; | |
50 | uint64_t ram_size; | |
397a79e7 CLG |
51 | |
52 | uint32_t nr_cores; | |
764f9b25 | 53 | uint32_t nr_threads; |
397a79e7 | 54 | uint64_t cores_mask; |
4fa28f23 | 55 | PnvCore **cores; |
967b7523 | 56 | |
4f9924c4 BH |
57 | uint32_t num_phbs; |
58 | ||
967b7523 CLG |
59 | MemoryRegion xscom_mmio; |
60 | MemoryRegion xscom; | |
61 | AddressSpace xscom_as; | |
64d011d5 CLG |
62 | |
63 | gchar *dt_isa_nodename; | |
db1015e9 | 64 | }; |
77864267 CLG |
65 | |
66 | #define TYPE_PNV8_CHIP "pnv8-chip" | |
db1015e9 | 67 | typedef struct Pnv8Chip Pnv8Chip; |
8110fa1d EH |
68 | DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP, |
69 | TYPE_PNV8_CHIP) | |
77864267 | 70 | |
db1015e9 | 71 | struct Pnv8Chip { |
77864267 CLG |
72 | /*< private >*/ |
73 | PnvChip parent_obj; | |
74 | ||
75 | /*< public >*/ | |
bf5615e7 | 76 | MemoryRegion icp_mmio; |
a3980bf5 BH |
77 | |
78 | PnvLpcController lpc; | |
ae856055 | 79 | Pnv8Psi psi; |
0722d05a | 80 | PnvOCC occ; |
3887d241 | 81 | PnvHomer homer; |
245cdb7f | 82 | |
9ae1329e CLG |
83 | #define PNV8_CHIP_PHB3_MAX 4 |
84 | PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX]; | |
85 | ||
245cdb7f | 86 | XICSFabric *xics; |
db1015e9 | 87 | }; |
77864267 CLG |
88 | |
89 | #define TYPE_PNV9_CHIP "pnv9-chip" | |
db1015e9 | 90 | typedef struct Pnv9Chip Pnv9Chip; |
8110fa1d EH |
91 | DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP, |
92 | TYPE_PNV9_CHIP) | |
77864267 | 93 | |
db1015e9 | 94 | struct Pnv9Chip { |
77864267 CLG |
95 | /*< private >*/ |
96 | PnvChip parent_obj; | |
97 | ||
98 | /*< public >*/ | |
2dfa91a2 | 99 | PnvXive xive; |
c38536bc | 100 | Pnv9Psi psi; |
15376c66 | 101 | PnvLpcController lpc; |
6598a70d | 102 | PnvOCC occ; |
3887d241 | 103 | PnvHomer homer; |
5dad902c CLG |
104 | |
105 | uint32_t nr_quads; | |
106 | PnvQuad *quads; | |
4f9924c4 BH |
107 | |
108 | #define PNV9_CHIP_MAX_PEC 3 | |
109 | PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; | |
db1015e9 | 110 | }; |
e997040e | 111 | |
5014c602 CLG |
112 | /* |
113 | * A SMT8 fused core is a pair of SMT4 cores. | |
114 | */ | |
115 | #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) | |
5373c61d | 116 | #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) |
5014c602 | 117 | |
2b548a42 | 118 | #define TYPE_PNV10_CHIP "pnv10-chip" |
db1015e9 | 119 | typedef struct Pnv10Chip Pnv10Chip; |
8110fa1d EH |
120 | DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP, |
121 | TYPE_PNV10_CHIP) | |
2b548a42 | 122 | |
db1015e9 | 123 | struct Pnv10Chip { |
2b548a42 CLG |
124 | /*< private >*/ |
125 | PnvChip parent_obj; | |
8b50ce85 CLG |
126 | |
127 | /*< public >*/ | |
128 | Pnv9Psi psi; | |
2661f6ab | 129 | PnvLpcController lpc; |
db1015e9 | 130 | }; |
2b548a42 | 131 | |
db1015e9 | 132 | struct PnvChipClass { |
e997040e CLG |
133 | /*< private >*/ |
134 | SysBusDeviceClass parent_class; | |
135 | ||
136 | /*< public >*/ | |
e997040e | 137 | uint64_t chip_cfam_id; |
397a79e7 | 138 | uint64_t cores_mask; |
4f9924c4 | 139 | uint32_t num_phbs; |
631adaff | 140 | |
77864267 CLG |
141 | DeviceRealize parent_realize; |
142 | ||
631adaff | 143 | uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); |
8fa1f4ef | 144 | void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); |
d49e8a9b | 145 | void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); |
0990ce6a | 146 | void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); |
85913070 | 147 | void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); |
04026890 | 148 | ISABus *(*isa_create)(PnvChip *chip, Error **errp); |
eb859a27 | 149 | void (*dt_populate)(PnvChip *chip, void *fdt); |
d8e4aad5 | 150 | void (*pic_print_info)(PnvChip *chip, Monitor *mon); |
c4b2c40c | 151 | uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); |
70c059e9 | 152 | uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); |
db1015e9 | 153 | }; |
e997040e | 154 | |
7fd544d8 IM |
155 | #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP |
156 | #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX | |
157 | ||
158 | #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") | |
8110fa1d EH |
159 | DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E, |
160 | TYPE_PNV_CHIP_POWER8E) | |
e997040e | 161 | |
7fd544d8 | 162 | #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") |
8110fa1d EH |
163 | DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8, |
164 | TYPE_PNV_CHIP_POWER8) | |
e997040e | 165 | |
7fd544d8 | 166 | #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") |
8110fa1d EH |
167 | DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL, |
168 | TYPE_PNV_CHIP_POWER8NVL) | |
e997040e | 169 | |
7fd544d8 | 170 | #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") |
8110fa1d EH |
171 | DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9, |
172 | TYPE_PNV_CHIP_POWER9) | |
e997040e | 173 | |
2b548a42 | 174 | #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v1.0") |
8110fa1d EH |
175 | DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10, |
176 | TYPE_PNV_CHIP_POWER10) | |
2b548a42 | 177 | |
e997040e | 178 | /* |
5509db4a CLG |
179 | * This generates a HW chip id depending on an index, as found on a |
180 | * two socket system with dual chip modules : | |
e997040e CLG |
181 | * |
182 | * 0x0, 0x1, 0x10, 0x11 | |
183 | * | |
184 | * 4 chips should be the maximum | |
5509db4a CLG |
185 | * |
186 | * TODO: use a machine property to define the chip ids | |
e997040e CLG |
187 | */ |
188 | #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) | |
9e933f4a | 189 | |
5509db4a CLG |
190 | /* |
191 | * Converts back a HW chip id to an index. This is useful to calculate | |
192 | * the MMIO addresses of some controllers which depend on the chip id. | |
193 | */ | |
194 | #define PNV_CHIP_INDEX(chip) \ | |
195 | (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) | |
196 | ||
119eaa9d CLG |
197 | PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); |
198 | ||
b168a138 | 199 | #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") |
db1015e9 EH |
200 | typedef struct PnvMachineClass PnvMachineClass; |
201 | typedef struct PnvMachineState PnvMachineState; | |
8110fa1d EH |
202 | DECLARE_OBJ_CHECKERS(PnvMachineState, PnvMachineClass, |
203 | PNV_MACHINE, TYPE_PNV_MACHINE) | |
d76f2da7 | 204 | |
7a90c6a1 | 205 | |
db1015e9 | 206 | struct PnvMachineClass { |
d76f2da7 GK |
207 | /*< private >*/ |
208 | MachineClass parent_class; | |
209 | ||
210 | /*< public >*/ | |
211 | const char *compat; | |
212 | int compat_size; | |
7a90c6a1 GK |
213 | |
214 | void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt); | |
db1015e9 | 215 | }; |
9e933f4a | 216 | |
7a90c6a1 | 217 | struct PnvMachineState { |
9e933f4a BH |
218 | /*< private >*/ |
219 | MachineState parent_obj; | |
220 | ||
221 | uint32_t initrd_base; | |
222 | long initrd_size; | |
e997040e CLG |
223 | |
224 | uint32_t num_chips; | |
225 | PnvChip **chips; | |
3495b6b6 CLG |
226 | |
227 | ISABus *isa_bus; | |
54f59d78 | 228 | uint32_t cpld_irqstate; |
aeaef83d CLG |
229 | |
230 | IPMIBmc *bmc; | |
bce0b691 | 231 | Notifier powerdown_notifier; |
35dde576 CLG |
232 | |
233 | PnvPnor *pnor; | |
08c3f3a7 CLG |
234 | |
235 | hwaddr fw_load_addr; | |
7a90c6a1 | 236 | }; |
9e933f4a BH |
237 | |
238 | #define PNV_FDT_ADDR 0x01000000 | |
d2fd9612 | 239 | #define PNV_TIMEBASE_FREQ 512000000ULL |
9e933f4a | 240 | |
aeaef83d CLG |
241 | /* |
242 | * BMC helpers | |
243 | */ | |
b168a138 | 244 | void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); |
bce0b691 | 245 | void pnv_bmc_powerdown(IPMIBmc *bmc); |
d8137bb7 | 246 | IPMIBmc *pnv_bmc_create(PnvPnor *pnor); |
25f3170b CLG |
247 | IPMIBmc *pnv_bmc_find(Error **errp); |
248 | void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); | |
aeaef83d | 249 | |
967b7523 CLG |
250 | /* |
251 | * POWER8 MMIO base addresses | |
252 | */ | |
253 | #define PNV_XSCOM_SIZE 0x800000000ull | |
254 | #define PNV_XSCOM_BASE(chip) \ | |
c29a0b0f | 255 | (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) |
967b7523 | 256 | |
8f092316 CLG |
257 | #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull |
258 | #define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull | |
3a1b70b6 CLG |
259 | #define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \ |
260 | PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip))) | |
7454558c | 261 | |
8f092316 | 262 | #define PNV_HOMER_SIZE 0x0000000000400000ull |
7454558c B |
263 | #define PNV_HOMER_BASE(chip) \ |
264 | (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE) | |
265 | ||
266 | ||
bf5615e7 CLG |
267 | /* |
268 | * XSCOM 0x20109CA defines the ICP BAR: | |
269 | * | |
270 | * 0:29 : bits 14 to 43 of address to define 1 MB region. | |
271 | * 30 : 1 to enable ICP to receive loads/stores against its BAR region | |
272 | * 31:63 : Constant 0 | |
273 | * | |
274 | * Usually defined as : | |
275 | * | |
276 | * 0xffffe00200000000 -> 0x0003ffff80000000 | |
277 | * 0xffffe00600000000 -> 0x0003ffff80100000 | |
278 | * 0xffffe02200000000 -> 0x0003ffff80800000 | |
279 | * 0xffffe02600000000 -> 0x0003ffff80900000 | |
280 | */ | |
281 | #define PNV_ICP_SIZE 0x0000000000100000ull | |
282 | #define PNV_ICP_BASE(chip) \ | |
283 | (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE) | |
284 | ||
54f59d78 CLG |
285 | |
286 | #define PNV_PSIHB_SIZE 0x0000000000100000ull | |
287 | #define PNV_PSIHB_BASE(chip) \ | |
288 | (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE) | |
289 | ||
290 | #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull | |
291 | #define PNV_PSIHB_FSP_BASE(chip) \ | |
292 | (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \ | |
293 | PNV_PSIHB_FSP_SIZE) | |
294 | ||
2dfa91a2 CLG |
295 | /* |
296 | * POWER9 MMIO base addresses | |
297 | */ | |
298 | #define PNV9_CHIP_BASE(chip, base) \ | |
299 | ((base) + ((uint64_t) (chip)->chip_id << 42)) | |
300 | ||
301 | #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull | |
302 | #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull) | |
303 | ||
304 | #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull | |
305 | #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull) | |
306 | ||
15376c66 CLG |
307 | #define PNV9_LPCM_SIZE 0x0000000100000000ull |
308 | #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull) | |
309 | ||
c38536bc CLG |
310 | #define PNV9_PSIHB_SIZE 0x0000000000100000ull |
311 | #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull) | |
312 | ||
2dfa91a2 CLG |
313 | #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull |
314 | #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull) | |
315 | ||
316 | #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull | |
317 | #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull) | |
318 | ||
c38536bc CLG |
319 | #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull |
320 | #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull) | |
2dfa91a2 | 321 | |
709044fd CLG |
322 | #define PNV9_XSCOM_SIZE 0x0000000400000000ull |
323 | #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) | |
324 | ||
8f092316 CLG |
325 | #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull |
326 | #define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull | |
3a1b70b6 CLG |
327 | #define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \ |
328 | PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip))) | |
7454558c | 329 | |
8f092316 | 330 | #define PNV9_HOMER_SIZE 0x0000000000400000ull |
7454558c B |
331 | #define PNV9_HOMER_BASE(chip) \ |
332 | (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE) | |
2b548a42 CLG |
333 | |
334 | /* | |
335 | * POWER10 MMIO base addresses - 16TB stride per chip | |
336 | */ | |
337 | #define PNV10_CHIP_BASE(chip, base) \ | |
338 | ((base) + ((uint64_t) (chip)->chip_id << 44)) | |
339 | ||
340 | #define PNV10_XSCOM_SIZE 0x0000000400000000ull | |
341 | #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull) | |
342 | ||
2661f6ab CLG |
343 | #define PNV10_LPCM_SIZE 0x0000000100000000ull |
344 | #define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull) | |
345 | ||
8b50ce85 CLG |
346 | #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull |
347 | #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull) | |
348 | ||
349 | #define PNV10_PSIHB_SIZE 0x0000000000100000ull | |
350 | #define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull) | |
351 | ||
a8b991b5 | 352 | #endif /* PPC_PNV_H */ |