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9e933f4a BH |
1 | /* |
2 | * QEMU PowerPC PowerNV various definitions | |
3 | * | |
4 | * Copyright (c) 2014-2016 BenH, IBM Corporation. | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
f70c5966 | 9 | * version 2.1 of the License, or (at your option) any later version. |
9e933f4a BH |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
a8b991b5 MA |
19 | |
20 | #ifndef PPC_PNV_H | |
21 | #define PPC_PNV_H | |
9e933f4a BH |
22 | |
23 | #include "hw/boards.h" | |
e997040e | 24 | #include "hw/sysbus.h" |
eaf87a39 | 25 | #include "hw/ipmi/ipmi.h" |
a3980bf5 | 26 | #include "hw/ppc/pnv_lpc.h" |
35dde576 | 27 | #include "hw/ppc/pnv_pnor.h" |
54f59d78 | 28 | #include "hw/ppc/pnv_psi.h" |
0722d05a | 29 | #include "hw/ppc/pnv_occ.h" |
3887d241 | 30 | #include "hw/ppc/pnv_homer.h" |
2dfa91a2 | 31 | #include "hw/ppc/pnv_xive.h" |
5dad902c | 32 | #include "hw/ppc/pnv_core.h" |
9ae1329e | 33 | #include "hw/pci-host/pnv_phb3.h" |
4f9924c4 | 34 | #include "hw/pci-host/pnv_phb4.h" |
db1015e9 | 35 | #include "qom/object.h" |
e997040e | 36 | |
b168a138 | 37 | #define TYPE_PNV_CHIP "pnv-chip" |
c821774a | 38 | OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass, |
30b5707c | 39 | PNV_CHIP) |
e997040e | 40 | |
db1015e9 | 41 | struct PnvChip { |
e997040e CLG |
42 | /*< private >*/ |
43 | SysBusDevice parent_obj; | |
44 | ||
45 | /*< public >*/ | |
46 | uint32_t chip_id; | |
47 | uint64_t ram_start; | |
48 | uint64_t ram_size; | |
397a79e7 CLG |
49 | |
50 | uint32_t nr_cores; | |
764f9b25 | 51 | uint32_t nr_threads; |
397a79e7 | 52 | uint64_t cores_mask; |
4fa28f23 | 53 | PnvCore **cores; |
967b7523 | 54 | |
422fd92e | 55 | uint32_t num_pecs; |
4f9924c4 | 56 | |
967b7523 CLG |
57 | MemoryRegion xscom_mmio; |
58 | MemoryRegion xscom; | |
59 | AddressSpace xscom_as; | |
64d011d5 | 60 | |
032c226b | 61 | MemoryRegion *fw_mr; |
64d011d5 | 62 | gchar *dt_isa_nodename; |
db1015e9 | 63 | }; |
77864267 CLG |
64 | |
65 | #define TYPE_PNV8_CHIP "pnv8-chip" | |
db1015e9 | 66 | typedef struct Pnv8Chip Pnv8Chip; |
8110fa1d EH |
67 | DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP, |
68 | TYPE_PNV8_CHIP) | |
77864267 | 69 | |
db1015e9 | 70 | struct Pnv8Chip { |
77864267 CLG |
71 | /*< private >*/ |
72 | PnvChip parent_obj; | |
73 | ||
74 | /*< public >*/ | |
bf5615e7 | 75 | MemoryRegion icp_mmio; |
a3980bf5 BH |
76 | |
77 | PnvLpcController lpc; | |
ae856055 | 78 | Pnv8Psi psi; |
0722d05a | 79 | PnvOCC occ; |
3887d241 | 80 | PnvHomer homer; |
245cdb7f | 81 | |
9ae1329e CLG |
82 | #define PNV8_CHIP_PHB3_MAX 4 |
83 | PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX]; | |
eb93c828 | 84 | uint32_t num_phbs; |
9ae1329e | 85 | |
245cdb7f | 86 | XICSFabric *xics; |
db1015e9 | 87 | }; |
77864267 CLG |
88 | |
89 | #define TYPE_PNV9_CHIP "pnv9-chip" | |
db1015e9 | 90 | typedef struct Pnv9Chip Pnv9Chip; |
8110fa1d EH |
91 | DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP, |
92 | TYPE_PNV9_CHIP) | |
77864267 | 93 | |
db1015e9 | 94 | struct Pnv9Chip { |
77864267 CLG |
95 | /*< private >*/ |
96 | PnvChip parent_obj; | |
97 | ||
98 | /*< public >*/ | |
2dfa91a2 | 99 | PnvXive xive; |
c38536bc | 100 | Pnv9Psi psi; |
15376c66 | 101 | PnvLpcController lpc; |
6598a70d | 102 | PnvOCC occ; |
3887d241 | 103 | PnvHomer homer; |
5dad902c CLG |
104 | |
105 | uint32_t nr_quads; | |
106 | PnvQuad *quads; | |
4f9924c4 BH |
107 | |
108 | #define PNV9_CHIP_MAX_PEC 3 | |
109 | PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; | |
db1015e9 | 110 | }; |
e997040e | 111 | |
5014c602 CLG |
112 | /* |
113 | * A SMT8 fused core is a pair of SMT4 cores. | |
114 | */ | |
115 | #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) | |
5373c61d | 116 | #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) |
5014c602 | 117 | |
2b548a42 | 118 | #define TYPE_PNV10_CHIP "pnv10-chip" |
db1015e9 | 119 | typedef struct Pnv10Chip Pnv10Chip; |
8110fa1d EH |
120 | DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP, |
121 | TYPE_PNV10_CHIP) | |
2b548a42 | 122 | |
db1015e9 | 123 | struct Pnv10Chip { |
2b548a42 CLG |
124 | /*< private >*/ |
125 | PnvChip parent_obj; | |
8b50ce85 CLG |
126 | |
127 | /*< public >*/ | |
128 | Pnv9Psi psi; | |
2661f6ab | 129 | PnvLpcController lpc; |
db1015e9 | 130 | }; |
2b548a42 | 131 | |
db1015e9 | 132 | struct PnvChipClass { |
e997040e CLG |
133 | /*< private >*/ |
134 | SysBusDeviceClass parent_class; | |
135 | ||
136 | /*< public >*/ | |
e997040e | 137 | uint64_t chip_cfam_id; |
397a79e7 | 138 | uint64_t cores_mask; |
422fd92e | 139 | uint32_t num_pecs; |
eb93c828 | 140 | uint32_t num_phbs; |
631adaff | 141 | |
77864267 CLG |
142 | DeviceRealize parent_realize; |
143 | ||
631adaff | 144 | uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); |
8fa1f4ef | 145 | void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); |
d49e8a9b | 146 | void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); |
0990ce6a | 147 | void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); |
85913070 | 148 | void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); |
04026890 | 149 | ISABus *(*isa_create)(PnvChip *chip, Error **errp); |
eb859a27 | 150 | void (*dt_populate)(PnvChip *chip, void *fdt); |
d8e4aad5 | 151 | void (*pic_print_info)(PnvChip *chip, Monitor *mon); |
c4b2c40c | 152 | uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); |
70c059e9 | 153 | uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); |
db1015e9 | 154 | }; |
e997040e | 155 | |
7fd544d8 IM |
156 | #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP |
157 | #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX | |
158 | ||
159 | #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") | |
8110fa1d EH |
160 | DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E, |
161 | TYPE_PNV_CHIP_POWER8E) | |
e997040e | 162 | |
7fd544d8 | 163 | #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") |
8110fa1d EH |
164 | DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8, |
165 | TYPE_PNV_CHIP_POWER8) | |
e997040e | 166 | |
7fd544d8 | 167 | #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") |
8110fa1d EH |
168 | DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL, |
169 | TYPE_PNV_CHIP_POWER8NVL) | |
e997040e | 170 | |
7fd544d8 | 171 | #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") |
8110fa1d EH |
172 | DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9, |
173 | TYPE_PNV_CHIP_POWER9) | |
e997040e | 174 | |
6bc8c046 | 175 | #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v2.0") |
8110fa1d EH |
176 | DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10, |
177 | TYPE_PNV_CHIP_POWER10) | |
2b548a42 | 178 | |
119eaa9d | 179 | PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); |
a71cd51e | 180 | void pnv_phb_attach_root_port(PCIHostState *pci, const char *name); |
c29dd003 | 181 | void pnv_chip_parent_fixup(PnvChip *chip, Object *obj, int index); |
119eaa9d | 182 | |
b168a138 | 183 | #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") |
db1015e9 EH |
184 | typedef struct PnvMachineClass PnvMachineClass; |
185 | typedef struct PnvMachineState PnvMachineState; | |
8110fa1d EH |
186 | DECLARE_OBJ_CHECKERS(PnvMachineState, PnvMachineClass, |
187 | PNV_MACHINE, TYPE_PNV_MACHINE) | |
d76f2da7 | 188 | |
7a90c6a1 | 189 | |
db1015e9 | 190 | struct PnvMachineClass { |
d76f2da7 GK |
191 | /*< private >*/ |
192 | MachineClass parent_class; | |
193 | ||
194 | /*< public >*/ | |
195 | const char *compat; | |
196 | int compat_size; | |
7a90c6a1 GK |
197 | |
198 | void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt); | |
db1015e9 | 199 | }; |
9e933f4a | 200 | |
7a90c6a1 | 201 | struct PnvMachineState { |
9e933f4a BH |
202 | /*< private >*/ |
203 | MachineState parent_obj; | |
204 | ||
205 | uint32_t initrd_base; | |
206 | long initrd_size; | |
e997040e CLG |
207 | |
208 | uint32_t num_chips; | |
209 | PnvChip **chips; | |
3495b6b6 CLG |
210 | |
211 | ISABus *isa_bus; | |
54f59d78 | 212 | uint32_t cpld_irqstate; |
aeaef83d CLG |
213 | |
214 | IPMIBmc *bmc; | |
bce0b691 | 215 | Notifier powerdown_notifier; |
35dde576 CLG |
216 | |
217 | PnvPnor *pnor; | |
08c3f3a7 CLG |
218 | |
219 | hwaddr fw_load_addr; | |
7a90c6a1 | 220 | }; |
9e933f4a | 221 | |
1f6a88ff CLG |
222 | PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id); |
223 | ||
9e933f4a | 224 | #define PNV_FDT_ADDR 0x01000000 |
d2fd9612 | 225 | #define PNV_TIMEBASE_FREQ 512000000ULL |
9e933f4a | 226 | |
aeaef83d CLG |
227 | /* |
228 | * BMC helpers | |
229 | */ | |
b168a138 | 230 | void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); |
bce0b691 | 231 | void pnv_bmc_powerdown(IPMIBmc *bmc); |
d8137bb7 | 232 | IPMIBmc *pnv_bmc_create(PnvPnor *pnor); |
25f3170b CLG |
233 | IPMIBmc *pnv_bmc_find(Error **errp); |
234 | void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); | |
aeaef83d | 235 | |
967b7523 CLG |
236 | /* |
237 | * POWER8 MMIO base addresses | |
238 | */ | |
239 | #define PNV_XSCOM_SIZE 0x800000000ull | |
240 | #define PNV_XSCOM_BASE(chip) \ | |
c29a0b0f | 241 | (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) |
967b7523 | 242 | |
8f092316 CLG |
243 | #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull |
244 | #define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull | |
3a1b70b6 | 245 | #define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \ |
ab17a3fe | 246 | PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id)) |
7454558c | 247 | |
8f092316 | 248 | #define PNV_HOMER_SIZE 0x0000000000400000ull |
7454558c | 249 | #define PNV_HOMER_BASE(chip) \ |
ab17a3fe | 250 | (0x7ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE) |
7454558c B |
251 | |
252 | ||
bf5615e7 CLG |
253 | /* |
254 | * XSCOM 0x20109CA defines the ICP BAR: | |
255 | * | |
256 | * 0:29 : bits 14 to 43 of address to define 1 MB region. | |
257 | * 30 : 1 to enable ICP to receive loads/stores against its BAR region | |
258 | * 31:63 : Constant 0 | |
259 | * | |
260 | * Usually defined as : | |
261 | * | |
262 | * 0xffffe00200000000 -> 0x0003ffff80000000 | |
263 | * 0xffffe00600000000 -> 0x0003ffff80100000 | |
264 | * 0xffffe02200000000 -> 0x0003ffff80800000 | |
265 | * 0xffffe02600000000 -> 0x0003ffff80900000 | |
266 | */ | |
267 | #define PNV_ICP_SIZE 0x0000000000100000ull | |
268 | #define PNV_ICP_BASE(chip) \ | |
ab17a3fe | 269 | (0x0003ffff80000000ull + (uint64_t) (chip)->chip_id * PNV_ICP_SIZE) |
bf5615e7 | 270 | |
54f59d78 CLG |
271 | |
272 | #define PNV_PSIHB_SIZE 0x0000000000100000ull | |
273 | #define PNV_PSIHB_BASE(chip) \ | |
ab17a3fe | 274 | (0x0003fffe80000000ull + (uint64_t)(chip)->chip_id * PNV_PSIHB_SIZE) |
54f59d78 CLG |
275 | |
276 | #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull | |
277 | #define PNV_PSIHB_FSP_BASE(chip) \ | |
ab17a3fe | 278 | (0x0003ffe000000000ull + (uint64_t)(chip)->chip_id * \ |
54f59d78 CLG |
279 | PNV_PSIHB_FSP_SIZE) |
280 | ||
2dfa91a2 CLG |
281 | /* |
282 | * POWER9 MMIO base addresses | |
283 | */ | |
284 | #define PNV9_CHIP_BASE(chip, base) \ | |
285 | ((base) + ((uint64_t) (chip)->chip_id << 42)) | |
286 | ||
287 | #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull | |
288 | #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull) | |
289 | ||
290 | #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull | |
291 | #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull) | |
292 | ||
15376c66 CLG |
293 | #define PNV9_LPCM_SIZE 0x0000000100000000ull |
294 | #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull) | |
295 | ||
c38536bc CLG |
296 | #define PNV9_PSIHB_SIZE 0x0000000000100000ull |
297 | #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull) | |
298 | ||
2dfa91a2 CLG |
299 | #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull |
300 | #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull) | |
301 | ||
302 | #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull | |
303 | #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull) | |
304 | ||
c38536bc CLG |
305 | #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull |
306 | #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull) | |
2dfa91a2 | 307 | |
709044fd CLG |
308 | #define PNV9_XSCOM_SIZE 0x0000000400000000ull |
309 | #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) | |
310 | ||
8f092316 CLG |
311 | #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull |
312 | #define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull | |
3a1b70b6 | 313 | #define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \ |
ab17a3fe | 314 | PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id)) |
7454558c | 315 | |
8f092316 | 316 | #define PNV9_HOMER_SIZE 0x0000000000400000ull |
7454558c | 317 | #define PNV9_HOMER_BASE(chip) \ |
ab17a3fe | 318 | (0x203ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV9_HOMER_SIZE) |
2b548a42 CLG |
319 | |
320 | /* | |
321 | * POWER10 MMIO base addresses - 16TB stride per chip | |
322 | */ | |
323 | #define PNV10_CHIP_BASE(chip, base) \ | |
324 | ((base) + ((uint64_t) (chip)->chip_id << 44)) | |
325 | ||
326 | #define PNV10_XSCOM_SIZE 0x0000000400000000ull | |
327 | #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull) | |
328 | ||
2661f6ab CLG |
329 | #define PNV10_LPCM_SIZE 0x0000000100000000ull |
330 | #define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull) | |
331 | ||
8b50ce85 CLG |
332 | #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull |
333 | #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull) | |
334 | ||
335 | #define PNV10_PSIHB_SIZE 0x0000000000100000ull | |
336 | #define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull) | |
337 | ||
a8b991b5 | 338 | #endif /* PPC_PNV_H */ |