]>
Commit | Line | Data |
---|---|---|
9e933f4a BH |
1 | /* |
2 | * QEMU PowerPC PowerNV various definitions | |
3 | * | |
4 | * Copyright (c) 2014-2016 BenH, IBM Corporation. | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #ifndef _PPC_PNV_H | |
20 | #define _PPC_PNV_H | |
21 | ||
22 | #include "hw/boards.h" | |
e997040e | 23 | #include "hw/sysbus.h" |
967b7523 | 24 | #include "hw/ppc/pnv_xscom.h" |
a3980bf5 | 25 | #include "hw/ppc/pnv_lpc.h" |
e997040e CLG |
26 | |
27 | #define TYPE_PNV_CHIP "powernv-chip" | |
28 | #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) | |
29 | #define PNV_CHIP_CLASS(klass) \ | |
30 | OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP) | |
31 | #define PNV_CHIP_GET_CLASS(obj) \ | |
32 | OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP) | |
33 | ||
34 | typedef enum PnvChipType { | |
35 | PNV_CHIP_POWER8E, /* AKA Murano (default) */ | |
36 | PNV_CHIP_POWER8, /* AKA Venice */ | |
37 | PNV_CHIP_POWER8NVL, /* AKA Naples */ | |
38 | PNV_CHIP_POWER9, /* AKA Nimbus */ | |
39 | } PnvChipType; | |
40 | ||
41 | typedef struct PnvChip { | |
42 | /*< private >*/ | |
43 | SysBusDevice parent_obj; | |
44 | ||
45 | /*< public >*/ | |
46 | uint32_t chip_id; | |
47 | uint64_t ram_start; | |
48 | uint64_t ram_size; | |
397a79e7 CLG |
49 | |
50 | uint32_t nr_cores; | |
51 | uint64_t cores_mask; | |
d2fd9612 | 52 | void *cores; |
967b7523 CLG |
53 | |
54 | hwaddr xscom_base; | |
55 | MemoryRegion xscom_mmio; | |
56 | MemoryRegion xscom; | |
57 | AddressSpace xscom_as; | |
a3980bf5 BH |
58 | |
59 | PnvLpcController lpc; | |
e997040e CLG |
60 | } PnvChip; |
61 | ||
62 | typedef struct PnvChipClass { | |
63 | /*< private >*/ | |
64 | SysBusDeviceClass parent_class; | |
65 | ||
66 | /*< public >*/ | |
67 | const char *cpu_model; | |
68 | PnvChipType chip_type; | |
69 | uint64_t chip_cfam_id; | |
397a79e7 | 70 | uint64_t cores_mask; |
631adaff | 71 | |
967b7523 CLG |
72 | hwaddr xscom_base; |
73 | ||
631adaff | 74 | uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); |
e997040e CLG |
75 | } PnvChipClass; |
76 | ||
77 | #define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E" | |
78 | #define PNV_CHIP_POWER8E(obj) \ | |
79 | OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E) | |
80 | ||
81 | #define TYPE_PNV_CHIP_POWER8 TYPE_PNV_CHIP "-POWER8" | |
82 | #define PNV_CHIP_POWER8(obj) \ | |
83 | OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8) | |
84 | ||
85 | #define TYPE_PNV_CHIP_POWER8NVL TYPE_PNV_CHIP "-POWER8NVL" | |
86 | #define PNV_CHIP_POWER8NVL(obj) \ | |
87 | OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL) | |
88 | ||
89 | #define TYPE_PNV_CHIP_POWER9 TYPE_PNV_CHIP "-POWER9" | |
90 | #define PNV_CHIP_POWER9(obj) \ | |
91 | OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) | |
92 | ||
93 | /* | |
94 | * This generates a HW chip id depending on an index: | |
95 | * | |
96 | * 0x0, 0x1, 0x10, 0x11 | |
97 | * | |
98 | * 4 chips should be the maximum | |
99 | */ | |
100 | #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) | |
9e933f4a BH |
101 | |
102 | #define TYPE_POWERNV_MACHINE MACHINE_TYPE_NAME("powernv") | |
103 | #define POWERNV_MACHINE(obj) \ | |
104 | OBJECT_CHECK(PnvMachineState, (obj), TYPE_POWERNV_MACHINE) | |
105 | ||
106 | typedef struct PnvMachineState { | |
107 | /*< private >*/ | |
108 | MachineState parent_obj; | |
109 | ||
110 | uint32_t initrd_base; | |
111 | long initrd_size; | |
e997040e CLG |
112 | |
113 | uint32_t num_chips; | |
114 | PnvChip **chips; | |
9e933f4a BH |
115 | } PnvMachineState; |
116 | ||
117 | #define PNV_FDT_ADDR 0x01000000 | |
d2fd9612 | 118 | #define PNV_TIMEBASE_FREQ 512000000ULL |
9e933f4a | 119 | |
967b7523 CLG |
120 | /* |
121 | * POWER8 MMIO base addresses | |
122 | */ | |
123 | #define PNV_XSCOM_SIZE 0x800000000ull | |
124 | #define PNV_XSCOM_BASE(chip) \ | |
125 | (chip->xscom_base + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) | |
126 | ||
9e933f4a | 127 | #endif /* _PPC_PNV_H */ |