[mirror_qemu.git] / include / hw / ppc / pnv.h

/*
 * QEMU PowerPC PowerNV various definitions
 *
 * Copyright (c) 2014-2016 BenH, IBM Corporation.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef PPC_PNV_H
#define PPC_PNV_H

#include "hw/boards.h"
#include "hw/sysbus.h"
#include "hw/ipmi/ipmi.h"
#include "hw/ppc/pnv_lpc.h"
#include "hw/ppc/pnv_psi.h"
#include "hw/ppc/pnv_occ.h"
#include "hw/ppc/pnv_homer.h"
#include "hw/ppc/pnv_xive.h"
#include "hw/ppc/pnv_core.h"

#define TYPE_PNV_CHIP "pnv-chip"
#define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
#define PNV_CHIP_CLASS(klass) \
     OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP)
#define PNV_CHIP_GET_CLASS(obj) \
     OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP)

typedef enum PnvChipType {
    PNV_CHIP_POWER8E,     /* AKA Murano (default) */
    PNV_CHIP_POWER8,      /* AKA Venice */
    PNV_CHIP_POWER8NVL,   /* AKA Naples */
    PNV_CHIP_POWER9,      /* AKA Nimbus */
} PnvChipType;

typedef struct PnvChip {
    /*< private >*/
    SysBusDevice parent_obj;

    /*< public >*/
    uint32_t     chip_id;
    uint64_t     ram_start;
    uint64_t     ram_size;

    uint32_t     nr_cores;
    uint64_t     cores_mask;
    void         *cores;

    MemoryRegion xscom_mmio;
    MemoryRegion xscom;
    AddressSpace xscom_as;

    gchar        *dt_isa_nodename;
} PnvChip;

#define TYPE_PNV8_CHIP "pnv8-chip"
#define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP)

typedef struct Pnv8Chip {
    /*< private >*/
    PnvChip      parent_obj;

    /*< public >*/
    MemoryRegion icp_mmio;

    PnvLpcController lpc;
    Pnv8Psi      psi;
    PnvOCC       occ;
    PnvHomer     homer;
} Pnv8Chip;

#define TYPE_PNV9_CHIP "pnv9-chip"
#define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP)

typedef struct Pnv9Chip {
    /*< private >*/
    PnvChip      parent_obj;

    /*< public >*/
    PnvXive      xive;
    Pnv9Psi      psi;
    PnvLpcController lpc;
    PnvOCC       occ;
    PnvHomer     homer;

    uint32_t     nr_quads;
    PnvQuad      *quads;
} Pnv9Chip;

typedef struct PnvChipClass {
    /*< private >*/
    SysBusDeviceClass parent_class;

    /*< public >*/
    PnvChipType  chip_type;
    uint64_t     chip_cfam_id;
    uint64_t     cores_mask;

    DeviceRealize parent_realize;

    uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
    void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
    ISABus *(*isa_create)(PnvChip *chip, Error **errp);
    void (*dt_populate)(PnvChip *chip, void *fdt);
    void (*pic_print_info)(PnvChip *chip, Monitor *mon);
} PnvChipClass;

#define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
#define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX

#define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
#define PNV_CHIP_POWER8E(obj) \
    OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E)

#define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
#define PNV_CHIP_POWER8(obj) \
    OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8)

#define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
#define PNV_CHIP_POWER8NVL(obj) \
    OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL)

#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0")
#define PNV_CHIP_POWER9(obj) \
    OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)

/*
 * This generates a HW chip id depending on an index, as found on a
 * two socket system with dual chip modules :
 *
 *    0x0, 0x1, 0x10, 0x11
 *
 * 4 chips should be the maximum
 *
 * TODO: use a machine property to define the chip ids
 */
#define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1))

/*
 * Converts back a HW chip id to an index. This is useful to calculate
 * the MMIO addresses of some controllers which depend on the chip id.
 */
#define PNV_CHIP_INDEX(chip)                                    \
    (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))

#define TYPE_PNV_MACHINE       MACHINE_TYPE_NAME("powernv")
#define PNV_MACHINE(obj) \
    OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE)

typedef struct PnvMachineState {
    /*< private >*/
    MachineState parent_obj;

    uint32_t     initrd_base;
    long         initrd_size;

    uint32_t     num_chips;
    PnvChip      **chips;

    ISABus       *isa_bus;
    uint32_t     cpld_irqstate;

    IPMIBmc      *bmc;
    Notifier     powerdown_notifier;
} PnvMachineState;

static inline bool pnv_chip_is_power9(const PnvChip *chip)
{
    return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER9;
}

static inline bool pnv_is_power9(PnvMachineState *pnv)
{
    return pnv_chip_is_power9(pnv->chips[0]);
}

#define PNV_FDT_ADDR          0x01000000
#define PNV_TIMEBASE_FREQ     512000000ULL

/*
 * BMC helpers
 */
void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
void pnv_bmc_powerdown(IPMIBmc *bmc);

/*
 * POWER8 MMIO base addresses
 */
#define PNV_XSCOM_SIZE        0x800000000ull
#define PNV_XSCOM_BASE(chip)                                            \
    (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)

#define PNV_OCC_COMMON_AREA_SIZE    0x0000000000700000ull
#define PNV_OCC_COMMON_AREA(chip)                                       \
    (0x7fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \
                         PNV_OCC_COMMON_AREA_SIZE))

#define PNV_HOMER_SIZE              0x0000000000300000ull
#define PNV_HOMER_BASE(chip)                                            \
    (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE)


/*
 * XSCOM 0x20109CA defines the ICP BAR:
 *
 * 0:29   : bits 14 to 43 of address to define 1 MB region.
 * 30     : 1 to enable ICP to receive loads/stores against its BAR region
 * 31:63  : Constant 0
 *
 * Usually defined as :
 *
 *      0xffffe00200000000 -> 0x0003ffff80000000
 *      0xffffe00600000000 -> 0x0003ffff80100000
 *      0xffffe02200000000 -> 0x0003ffff80800000
 *      0xffffe02600000000 -> 0x0003ffff80900000
 */
#define PNV_ICP_SIZE         0x0000000000100000ull
#define PNV_ICP_BASE(chip)                                              \
    (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE)


#define PNV_PSIHB_SIZE       0x0000000000100000ull
#define PNV_PSIHB_BASE(chip) \
    (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE)

#define PNV_PSIHB_FSP_SIZE   0x0000000100000000ull
#define PNV_PSIHB_FSP_BASE(chip) \
    (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \
     PNV_PSIHB_FSP_SIZE)

/*
 * POWER9 MMIO base addresses
 */
#define PNV9_CHIP_BASE(chip, base)   \
    ((base) + ((uint64_t) (chip)->chip_id << 42))

#define PNV9_XIVE_VC_SIZE            0x0000008000000000ull
#define PNV9_XIVE_VC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006010000000000ull)

#define PNV9_XIVE_PC_SIZE            0x0000001000000000ull
#define PNV9_XIVE_PC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006018000000000ull)

#define PNV9_LPCM_SIZE               0x0000000100000000ull
#define PNV9_LPCM_BASE(chip)         PNV9_CHIP_BASE(chip, 0x0006030000000000ull)

#define PNV9_PSIHB_SIZE              0x0000000000100000ull
#define PNV9_PSIHB_BASE(chip)        PNV9_CHIP_BASE(chip, 0x0006030203000000ull)

#define PNV9_XIVE_IC_SIZE            0x0000000000080000ull
#define PNV9_XIVE_IC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006030203100000ull)

#define PNV9_XIVE_TM_SIZE            0x0000000000040000ull
#define PNV9_XIVE_TM_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006030203180000ull)

#define PNV9_PSIHB_ESB_SIZE          0x0000000000010000ull
#define PNV9_PSIHB_ESB_BASE(chip)    PNV9_CHIP_BASE(chip, 0x00060302031c0000ull)

#define PNV9_XSCOM_SIZE              0x0000000400000000ull
#define PNV9_XSCOM_BASE(chip)        PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)

#define PNV9_OCC_COMMON_AREA_SIZE    0x0000000000700000ull
#define PNV9_OCC_COMMON_AREA(chip)                                      \
    (0x203fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \
                           PNV9_OCC_COMMON_AREA_SIZE))

#define PNV9_HOMER_SIZE              0x0000000000300000ull
#define PNV9_HOMER_BASE(chip)                                           \
    (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE)
#endif /* PPC_PNV_H */
Commit	Line	Data
9e933f4a BH	1	/*
	2	* QEMU PowerPC PowerNV various definitions
	3	*
	4	* Copyright (c) 2014-2016 BenH, IBM Corporation.
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
a8b991b5 MA	19
	20	#ifndef PPC_PNV_H
	21	#define PPC_PNV_H
9e933f4a BH	22
9e933f4a BH	23	#include "hw/boards.h"
e997040e	24	#include "hw/sysbus.h"
eaf87a39	25	#include "hw/ipmi/ipmi.h"
a3980bf5	26	#include "hw/ppc/pnv_lpc.h"
54f59d78	27	#include "hw/ppc/pnv_psi.h"
0722d05a	28	#include "hw/ppc/pnv_occ.h"
3887d241	29	#include "hw/ppc/pnv_homer.h"
2dfa91a2	30	#include "hw/ppc/pnv_xive.h"
5dad902c	31	#include "hw/ppc/pnv_core.h"
e997040e	32
b168a138	33	#define TYPE_PNV_CHIP "pnv-chip"
e997040e CLG	34	#define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
	35	#define PNV_CHIP_CLASS(klass) \
	36	OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP)
	37	#define PNV_CHIP_GET_CLASS(obj) \
	38	OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP)
	39
	40	typedef enum PnvChipType {
	41	PNV_CHIP_POWER8E, /* AKA Murano (default) */
	42	PNV_CHIP_POWER8, /* AKA Venice */
	43	PNV_CHIP_POWER8NVL, /* AKA Naples */
	44	PNV_CHIP_POWER9, /* AKA Nimbus */
	45	} PnvChipType;
	46
	47	typedef struct PnvChip {
	48	/< private >/
	49	SysBusDevice parent_obj;
	50
	51	/< public >/
	52	uint32_t chip_id;
	53	uint64_t ram_start;
	54	uint64_t ram_size;
397a79e7 CLG	55
	56	uint32_t nr_cores;
	57	uint64_t cores_mask;
d2fd9612	58	void *cores;
967b7523	59
967b7523 CLG	60	MemoryRegion xscom_mmio;
	61	MemoryRegion xscom;
	62	AddressSpace xscom_as;
64d011d5 CLG	63
64d011d5 CLG	64	gchar *dt_isa_nodename;
77864267 CLG	65	} PnvChip;
	66
	67	#define TYPE_PNV8_CHIP "pnv8-chip"
	68	#define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP)
	69
	70	typedef struct Pnv8Chip {
	71	/< private >/
	72	PnvChip parent_obj;
	73
	74	/< public >/
bf5615e7	75	MemoryRegion icp_mmio;
a3980bf5 BH	76
a3980bf5 BH	77	PnvLpcController lpc;
ae856055	78	Pnv8Psi psi;
0722d05a	79	PnvOCC occ;
3887d241	80	PnvHomer homer;
77864267 CLG	81	} Pnv8Chip;
	82
	83	#define TYPE_PNV9_CHIP "pnv9-chip"
	84	#define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP)
	85
	86	typedef struct Pnv9Chip {
	87	/< private >/
	88	PnvChip parent_obj;
	89
	90	/< public >/
2dfa91a2	91	PnvXive xive;
c38536bc	92	Pnv9Psi psi;
15376c66	93	PnvLpcController lpc;
6598a70d	94	PnvOCC occ;
3887d241	95	PnvHomer homer;
5dad902c CLG	96
	97	uint32_t nr_quads;
	98	PnvQuad *quads;
77864267	99	} Pnv9Chip;
e997040e CLG	100
	101	typedef struct PnvChipClass {
	102	/< private >/
	103	SysBusDeviceClass parent_class;
	104
	105	/< public >/
e997040e CLG	106	PnvChipType chip_type;
e997040e CLG	107	uint64_t chip_cfam_id;
397a79e7	108	uint64_t cores_mask;
631adaff	109
77864267 CLG	110	DeviceRealize parent_realize;
77864267 CLG	111
631adaff	112	uint32_t (core_pir)(PnvChip chip, uint32_t core_id);
8fa1f4ef	113	void (intc_create)(PnvChip chip, PowerPCCPU cpu, Error *errp);
04026890	114	ISABus (isa_create)(PnvChip chip, Error *errp);
eb859a27	115	void (dt_populate)(PnvChip chip, void *fdt);
d8e4aad5	116	void (pic_print_info)(PnvChip chip, Monitor *mon);
e997040e CLG	117	} PnvChipClass;
e997040e CLG	118
7fd544d8 IM	119	#define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
	120	#define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
	121
	122	#define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
e997040e CLG	123	#define PNV_CHIP_POWER8E(obj) \
	124	OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E)
	125
7fd544d8	126	#define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
e997040e CLG	127	#define PNV_CHIP_POWER8(obj) \
	128	OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8)
	129
7fd544d8	130	#define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
e997040e CLG	131	#define PNV_CHIP_POWER8NVL(obj) \
	132	OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL)
	133
7fd544d8	134	#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0")
e997040e CLG	135	#define PNV_CHIP_POWER9(obj) \
	136	OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)
	137
	138	/*
5509db4a CLG	139	* This generates a HW chip id depending on an index, as found on a
5509db4a CLG	140	* two socket system with dual chip modules :
e997040e CLG	141	*
	142	* 0x0, 0x1, 0x10, 0x11
	143	*
	144	* 4 chips should be the maximum
5509db4a CLG	145	*
5509db4a CLG	146	* TODO: use a machine property to define the chip ids
e997040e CLG	147	*/
e997040e CLG	148	#define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) \| ((i) & 0x1))
9e933f4a	149
5509db4a CLG	150	/*
	151	* Converts back a HW chip id to an index. This is useful to calculate
	152	* the MMIO addresses of some controllers which depend on the chip id.
	153	*/
	154	#define PNV_CHIP_INDEX(chip) \
	155	(((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
	156
b168a138 CLG	157	#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
	158	#define PNV_MACHINE(obj) \
	159	OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE)
9e933f4a BH	160
	161	typedef struct PnvMachineState {
	162	/< private >/
	163	MachineState parent_obj;
	164
	165	uint32_t initrd_base;
	166	long initrd_size;
e997040e CLG	167
	168	uint32_t num_chips;
	169	PnvChip **chips;
3495b6b6 CLG	170
3495b6b6 CLG	171	ISABus *isa_bus;
54f59d78	172	uint32_t cpld_irqstate;
aeaef83d CLG	173
aeaef83d CLG	174	IPMIBmc *bmc;
bce0b691	175	Notifier powerdown_notifier;
9e933f4a BH	176	} PnvMachineState;
9e933f4a BH	177
b3b066e9 CLG	178	static inline bool pnv_chip_is_power9(const PnvChip *chip)
	179	{
	180	return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER9;
	181	}
	182
	183	static inline bool pnv_is_power9(PnvMachineState *pnv)
	184	{
	185	return pnv_chip_is_power9(pnv->chips[0]);
	186	}
	187
9e933f4a	188	#define PNV_FDT_ADDR 0x01000000
d2fd9612	189	#define PNV_TIMEBASE_FREQ 512000000ULL
9e933f4a	190
aeaef83d CLG	191	/*
	192	* BMC helpers
	193	*/
b168a138	194	void pnv_dt_bmc_sensors(IPMIBmc bmc, void fdt);
bce0b691	195	void pnv_bmc_powerdown(IPMIBmc *bmc);
aeaef83d	196
967b7523 CLG	197	/*
	198	* POWER8 MMIO base addresses
	199	*/
	200	#define PNV_XSCOM_SIZE 0x800000000ull
	201	#define PNV_XSCOM_BASE(chip) \
c29a0b0f	202	(0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
967b7523	203
7454558c B	204	#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000700000ull
	205	#define PNV_OCC_COMMON_AREA(chip) \
	206	(0x7fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \
	207	PNV_OCC_COMMON_AREA_SIZE))
	208
	209	#define PNV_HOMER_SIZE 0x0000000000300000ull
	210	#define PNV_HOMER_BASE(chip) \
	211	(0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE)
	212
	213
bf5615e7 CLG	214	/*
	215	* XSCOM 0x20109CA defines the ICP BAR:
	216	*
	217	* 0:29 : bits 14 to 43 of address to define 1 MB region.
	218	* 30 : 1 to enable ICP to receive loads/stores against its BAR region
	219	* 31:63 : Constant 0
	220	*
	221	* Usually defined as :
	222	*
	223	* 0xffffe00200000000 -> 0x0003ffff80000000
	224	* 0xffffe00600000000 -> 0x0003ffff80100000
	225	* 0xffffe02200000000 -> 0x0003ffff80800000
	226	* 0xffffe02600000000 -> 0x0003ffff80900000
	227	*/
	228	#define PNV_ICP_SIZE 0x0000000000100000ull
	229	#define PNV_ICP_BASE(chip) \
	230	(0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE)
	231
54f59d78 CLG	232
	233	#define PNV_PSIHB_SIZE 0x0000000000100000ull
	234	#define PNV_PSIHB_BASE(chip) \
	235	(0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE)
	236
	237	#define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull
	238	#define PNV_PSIHB_FSP_BASE(chip) \
	239	(0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \
	240	PNV_PSIHB_FSP_SIZE)
	241
2dfa91a2 CLG	242	/*
	243	* POWER9 MMIO base addresses
	244	*/
	245	#define PNV9_CHIP_BASE(chip, base) \
	246	((base) + ((uint64_t) (chip)->chip_id << 42))
	247
	248	#define PNV9_XIVE_VC_SIZE 0x0000008000000000ull
	249	#define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull)
	250
	251	#define PNV9_XIVE_PC_SIZE 0x0000001000000000ull
	252	#define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull)
	253
15376c66 CLG	254	#define PNV9_LPCM_SIZE 0x0000000100000000ull
	255	#define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull)
	256
c38536bc CLG	257	#define PNV9_PSIHB_SIZE 0x0000000000100000ull
	258	#define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull)
	259
2dfa91a2 CLG	260	#define PNV9_XIVE_IC_SIZE 0x0000000000080000ull
	261	#define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull)
	262
	263	#define PNV9_XIVE_TM_SIZE 0x0000000000040000ull
	264	#define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull)
	265
c38536bc CLG	266	#define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull
c38536bc CLG	267	#define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull)
2dfa91a2	268
709044fd CLG	269	#define PNV9_XSCOM_SIZE 0x0000000400000000ull
	270	#define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)
	271
7454558c B	272	#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000700000ull
	273	#define PNV9_OCC_COMMON_AREA(chip) \
	274	(0x203fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \
	275	PNV9_OCC_COMMON_AREA_SIZE))
	276
	277	#define PNV9_HOMER_SIZE 0x0000000000300000ull
	278	#define PNV9_HOMER_BASE(chip) \
	279	(0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE)
a8b991b5	280	#endif /* PPC_PNV_H */