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9e933f4a BH |
1 | /* |
2 | * QEMU PowerPC PowerNV various definitions | |
3 | * | |
4 | * Copyright (c) 2014-2016 BenH, IBM Corporation. | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
a8b991b5 MA |
19 | |
20 | #ifndef PPC_PNV_H | |
21 | #define PPC_PNV_H | |
9e933f4a BH |
22 | |
23 | #include "hw/boards.h" | |
e997040e | 24 | #include "hw/sysbus.h" |
eaf87a39 | 25 | #include "hw/ipmi/ipmi.h" |
a3980bf5 | 26 | #include "hw/ppc/pnv_lpc.h" |
35dde576 | 27 | #include "hw/ppc/pnv_pnor.h" |
54f59d78 | 28 | #include "hw/ppc/pnv_psi.h" |
0722d05a | 29 | #include "hw/ppc/pnv_occ.h" |
3887d241 | 30 | #include "hw/ppc/pnv_homer.h" |
2dfa91a2 | 31 | #include "hw/ppc/pnv_xive.h" |
5dad902c | 32 | #include "hw/ppc/pnv_core.h" |
e997040e | 33 | |
b168a138 | 34 | #define TYPE_PNV_CHIP "pnv-chip" |
e997040e CLG |
35 | #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) |
36 | #define PNV_CHIP_CLASS(klass) \ | |
37 | OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP) | |
38 | #define PNV_CHIP_GET_CLASS(obj) \ | |
39 | OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP) | |
40 | ||
41 | typedef enum PnvChipType { | |
42 | PNV_CHIP_POWER8E, /* AKA Murano (default) */ | |
43 | PNV_CHIP_POWER8, /* AKA Venice */ | |
44 | PNV_CHIP_POWER8NVL, /* AKA Naples */ | |
45 | PNV_CHIP_POWER9, /* AKA Nimbus */ | |
2b548a42 | 46 | PNV_CHIP_POWER10, /* AKA TBD */ |
e997040e CLG |
47 | } PnvChipType; |
48 | ||
49 | typedef struct PnvChip { | |
50 | /*< private >*/ | |
51 | SysBusDevice parent_obj; | |
52 | ||
53 | /*< public >*/ | |
54 | uint32_t chip_id; | |
55 | uint64_t ram_start; | |
56 | uint64_t ram_size; | |
397a79e7 CLG |
57 | |
58 | uint32_t nr_cores; | |
59 | uint64_t cores_mask; | |
4fa28f23 | 60 | PnvCore **cores; |
967b7523 | 61 | |
967b7523 CLG |
62 | MemoryRegion xscom_mmio; |
63 | MemoryRegion xscom; | |
64 | AddressSpace xscom_as; | |
64d011d5 CLG |
65 | |
66 | gchar *dt_isa_nodename; | |
77864267 CLG |
67 | } PnvChip; |
68 | ||
69 | #define TYPE_PNV8_CHIP "pnv8-chip" | |
70 | #define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP) | |
71 | ||
72 | typedef struct Pnv8Chip { | |
73 | /*< private >*/ | |
74 | PnvChip parent_obj; | |
75 | ||
76 | /*< public >*/ | |
bf5615e7 | 77 | MemoryRegion icp_mmio; |
a3980bf5 BH |
78 | |
79 | PnvLpcController lpc; | |
ae856055 | 80 | Pnv8Psi psi; |
0722d05a | 81 | PnvOCC occ; |
3887d241 | 82 | PnvHomer homer; |
77864267 CLG |
83 | } Pnv8Chip; |
84 | ||
85 | #define TYPE_PNV9_CHIP "pnv9-chip" | |
86 | #define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP) | |
87 | ||
88 | typedef struct Pnv9Chip { | |
89 | /*< private >*/ | |
90 | PnvChip parent_obj; | |
91 | ||
92 | /*< public >*/ | |
2dfa91a2 | 93 | PnvXive xive; |
c38536bc | 94 | Pnv9Psi psi; |
15376c66 | 95 | PnvLpcController lpc; |
6598a70d | 96 | PnvOCC occ; |
3887d241 | 97 | PnvHomer homer; |
5dad902c CLG |
98 | |
99 | uint32_t nr_quads; | |
100 | PnvQuad *quads; | |
77864267 | 101 | } Pnv9Chip; |
e997040e | 102 | |
5014c602 CLG |
103 | /* |
104 | * A SMT8 fused core is a pair of SMT4 cores. | |
105 | */ | |
106 | #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) | |
5373c61d | 107 | #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) |
5014c602 | 108 | |
2b548a42 CLG |
109 | #define TYPE_PNV10_CHIP "pnv10-chip" |
110 | #define PNV10_CHIP(obj) OBJECT_CHECK(Pnv10Chip, (obj), TYPE_PNV10_CHIP) | |
111 | ||
112 | typedef struct Pnv10Chip { | |
113 | /*< private >*/ | |
114 | PnvChip parent_obj; | |
8b50ce85 CLG |
115 | |
116 | /*< public >*/ | |
117 | Pnv9Psi psi; | |
2661f6ab | 118 | PnvLpcController lpc; |
2b548a42 CLG |
119 | } Pnv10Chip; |
120 | ||
e997040e CLG |
121 | typedef struct PnvChipClass { |
122 | /*< private >*/ | |
123 | SysBusDeviceClass parent_class; | |
124 | ||
125 | /*< public >*/ | |
e997040e CLG |
126 | PnvChipType chip_type; |
127 | uint64_t chip_cfam_id; | |
397a79e7 | 128 | uint64_t cores_mask; |
631adaff | 129 | |
77864267 CLG |
130 | DeviceRealize parent_realize; |
131 | ||
631adaff | 132 | uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); |
8fa1f4ef | 133 | void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); |
d49e8a9b | 134 | void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); |
0990ce6a | 135 | void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); |
04026890 | 136 | ISABus *(*isa_create)(PnvChip *chip, Error **errp); |
eb859a27 | 137 | void (*dt_populate)(PnvChip *chip, void *fdt); |
d8e4aad5 | 138 | void (*pic_print_info)(PnvChip *chip, Monitor *mon); |
e997040e CLG |
139 | } PnvChipClass; |
140 | ||
7fd544d8 IM |
141 | #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP |
142 | #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX | |
143 | ||
144 | #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") | |
e997040e CLG |
145 | #define PNV_CHIP_POWER8E(obj) \ |
146 | OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E) | |
147 | ||
7fd544d8 | 148 | #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") |
e997040e CLG |
149 | #define PNV_CHIP_POWER8(obj) \ |
150 | OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8) | |
151 | ||
7fd544d8 | 152 | #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") |
e997040e CLG |
153 | #define PNV_CHIP_POWER8NVL(obj) \ |
154 | OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL) | |
155 | ||
7fd544d8 | 156 | #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") |
e997040e CLG |
157 | #define PNV_CHIP_POWER9(obj) \ |
158 | OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) | |
159 | ||
2b548a42 CLG |
160 | #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v1.0") |
161 | #define PNV_CHIP_POWER10(obj) \ | |
162 | OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER10) | |
163 | ||
e997040e | 164 | /* |
5509db4a CLG |
165 | * This generates a HW chip id depending on an index, as found on a |
166 | * two socket system with dual chip modules : | |
e997040e CLG |
167 | * |
168 | * 0x0, 0x1, 0x10, 0x11 | |
169 | * | |
170 | * 4 chips should be the maximum | |
5509db4a CLG |
171 | * |
172 | * TODO: use a machine property to define the chip ids | |
e997040e CLG |
173 | */ |
174 | #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) | |
9e933f4a | 175 | |
5509db4a CLG |
176 | /* |
177 | * Converts back a HW chip id to an index. This is useful to calculate | |
178 | * the MMIO addresses of some controllers which depend on the chip id. | |
179 | */ | |
180 | #define PNV_CHIP_INDEX(chip) \ | |
181 | (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) | |
182 | ||
119eaa9d CLG |
183 | PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); |
184 | ||
b168a138 CLG |
185 | #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") |
186 | #define PNV_MACHINE(obj) \ | |
187 | OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE) | |
d76f2da7 GK |
188 | #define PNV_MACHINE_GET_CLASS(obj) \ |
189 | OBJECT_GET_CLASS(PnvMachineClass, obj, TYPE_PNV_MACHINE) | |
190 | #define PNV_MACHINE_CLASS(klass) \ | |
191 | OBJECT_CLASS_CHECK(PnvMachineClass, klass, TYPE_PNV_MACHINE) | |
192 | ||
193 | typedef struct PnvMachineClass { | |
194 | /*< private >*/ | |
195 | MachineClass parent_class; | |
196 | ||
197 | /*< public >*/ | |
198 | const char *compat; | |
199 | int compat_size; | |
200 | } PnvMachineClass; | |
9e933f4a BH |
201 | |
202 | typedef struct PnvMachineState { | |
203 | /*< private >*/ | |
204 | MachineState parent_obj; | |
205 | ||
206 | uint32_t initrd_base; | |
207 | long initrd_size; | |
e997040e CLG |
208 | |
209 | uint32_t num_chips; | |
210 | PnvChip **chips; | |
3495b6b6 CLG |
211 | |
212 | ISABus *isa_bus; | |
54f59d78 | 213 | uint32_t cpld_irqstate; |
aeaef83d CLG |
214 | |
215 | IPMIBmc *bmc; | |
bce0b691 | 216 | Notifier powerdown_notifier; |
35dde576 CLG |
217 | |
218 | PnvPnor *pnor; | |
9e933f4a BH |
219 | } PnvMachineState; |
220 | ||
b3b066e9 CLG |
221 | static inline bool pnv_chip_is_power9(const PnvChip *chip) |
222 | { | |
223 | return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER9; | |
224 | } | |
225 | ||
226 | static inline bool pnv_is_power9(PnvMachineState *pnv) | |
227 | { | |
228 | return pnv_chip_is_power9(pnv->chips[0]); | |
229 | } | |
230 | ||
5373c61d CLG |
231 | PnvChip *pnv_get_chip(uint32_t chip_id); |
232 | ||
9e933f4a | 233 | #define PNV_FDT_ADDR 0x01000000 |
d2fd9612 | 234 | #define PNV_TIMEBASE_FREQ 512000000ULL |
9e933f4a | 235 | |
2b548a42 CLG |
236 | static inline bool pnv_chip_is_power10(const PnvChip *chip) |
237 | { | |
238 | return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER10; | |
239 | } | |
240 | ||
241 | static inline bool pnv_is_power10(PnvMachineState *pnv) | |
242 | { | |
243 | return pnv_chip_is_power10(pnv->chips[0]); | |
244 | } | |
245 | ||
aeaef83d CLG |
246 | /* |
247 | * BMC helpers | |
248 | */ | |
b168a138 | 249 | void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); |
bce0b691 | 250 | void pnv_bmc_powerdown(IPMIBmc *bmc); |
e2392d43 | 251 | IPMIBmc *pnv_bmc_create(void); |
aeaef83d | 252 | |
967b7523 CLG |
253 | /* |
254 | * POWER8 MMIO base addresses | |
255 | */ | |
256 | #define PNV_XSCOM_SIZE 0x800000000ull | |
257 | #define PNV_XSCOM_BASE(chip) \ | |
c29a0b0f | 258 | (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) |
967b7523 | 259 | |
8f092316 CLG |
260 | #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull |
261 | #define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull | |
3a1b70b6 CLG |
262 | #define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \ |
263 | PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip))) | |
7454558c | 264 | |
8f092316 | 265 | #define PNV_HOMER_SIZE 0x0000000000400000ull |
7454558c B |
266 | #define PNV_HOMER_BASE(chip) \ |
267 | (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE) | |
268 | ||
269 | ||
bf5615e7 CLG |
270 | /* |
271 | * XSCOM 0x20109CA defines the ICP BAR: | |
272 | * | |
273 | * 0:29 : bits 14 to 43 of address to define 1 MB region. | |
274 | * 30 : 1 to enable ICP to receive loads/stores against its BAR region | |
275 | * 31:63 : Constant 0 | |
276 | * | |
277 | * Usually defined as : | |
278 | * | |
279 | * 0xffffe00200000000 -> 0x0003ffff80000000 | |
280 | * 0xffffe00600000000 -> 0x0003ffff80100000 | |
281 | * 0xffffe02200000000 -> 0x0003ffff80800000 | |
282 | * 0xffffe02600000000 -> 0x0003ffff80900000 | |
283 | */ | |
284 | #define PNV_ICP_SIZE 0x0000000000100000ull | |
285 | #define PNV_ICP_BASE(chip) \ | |
286 | (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE) | |
287 | ||
54f59d78 CLG |
288 | |
289 | #define PNV_PSIHB_SIZE 0x0000000000100000ull | |
290 | #define PNV_PSIHB_BASE(chip) \ | |
291 | (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE) | |
292 | ||
293 | #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull | |
294 | #define PNV_PSIHB_FSP_BASE(chip) \ | |
295 | (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \ | |
296 | PNV_PSIHB_FSP_SIZE) | |
297 | ||
2dfa91a2 CLG |
298 | /* |
299 | * POWER9 MMIO base addresses | |
300 | */ | |
301 | #define PNV9_CHIP_BASE(chip, base) \ | |
302 | ((base) + ((uint64_t) (chip)->chip_id << 42)) | |
303 | ||
304 | #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull | |
305 | #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull) | |
306 | ||
307 | #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull | |
308 | #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull) | |
309 | ||
15376c66 CLG |
310 | #define PNV9_LPCM_SIZE 0x0000000100000000ull |
311 | #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull) | |
312 | ||
c38536bc CLG |
313 | #define PNV9_PSIHB_SIZE 0x0000000000100000ull |
314 | #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull) | |
315 | ||
2dfa91a2 CLG |
316 | #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull |
317 | #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull) | |
318 | ||
319 | #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull | |
320 | #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull) | |
321 | ||
c38536bc CLG |
322 | #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull |
323 | #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull) | |
2dfa91a2 | 324 | |
709044fd CLG |
325 | #define PNV9_XSCOM_SIZE 0x0000000400000000ull |
326 | #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) | |
327 | ||
8f092316 CLG |
328 | #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull |
329 | #define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull | |
3a1b70b6 CLG |
330 | #define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \ |
331 | PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip))) | |
7454558c | 332 | |
8f092316 | 333 | #define PNV9_HOMER_SIZE 0x0000000000400000ull |
7454558c B |
334 | #define PNV9_HOMER_BASE(chip) \ |
335 | (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE) | |
2b548a42 CLG |
336 | |
337 | /* | |
338 | * POWER10 MMIO base addresses - 16TB stride per chip | |
339 | */ | |
340 | #define PNV10_CHIP_BASE(chip, base) \ | |
341 | ((base) + ((uint64_t) (chip)->chip_id << 44)) | |
342 | ||
343 | #define PNV10_XSCOM_SIZE 0x0000000400000000ull | |
344 | #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull) | |
345 | ||
2661f6ab CLG |
346 | #define PNV10_LPCM_SIZE 0x0000000100000000ull |
347 | #define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull) | |
348 | ||
8b50ce85 CLG |
349 | #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull |
350 | #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull) | |
351 | ||
352 | #define PNV10_PSIHB_SIZE 0x0000000000100000ull | |
353 | #define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull) | |
354 | ||
a8b991b5 | 355 | #endif /* PPC_PNV_H */ |