projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 9fdf0c29 DG |
1 | #if !defined(__HW_SPAPR_H__) |
| 2 | #define __HW_SPAPR_H__ | |
| 3 | ||
| 9c17d615 | 4 | #include "sysemu/dma.h" |
| 28e02042 | 5 | #include "hw/boards.h" |
| 0d09e41a | 6 | #include "hw/ppc/xics.h" |
| 31fe14d1 | 7 | #include "hw/ppc/spapr_drc.h" |
| 277f9acf | 8 | |
| 4040ab72 | 9 | struct VIOsPAPRBus; |
| 3384f95c | 10 | struct sPAPRPHBState; |
| 639e8102 | 11 | struct sPAPRNVRAM; |
| 46503c2b | 12 | typedef struct sPAPRConfigureConnectorState sPAPRConfigureConnectorState; |
| 31fe14d1 | 13 | typedef struct sPAPREventLogEntry sPAPREventLogEntry; |
| 4040ab72 | 14 | |
| 4be21d56 | 15 | #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL |
| 1b718907 | 16 | #define SPAPR_ENTRY_POINT 0x100 |
| 4be21d56 | 17 | |
| 183930c0 | 18 | typedef struct sPAPRMachineClass sPAPRMachineClass; |
| 28e02042 DG |
19 | typedef struct sPAPRMachineState sPAPRMachineState; |
| 20 | ||
| 21 | #define TYPE_SPAPR_MACHINE "spapr-machine" | |
| 22 | #define SPAPR_MACHINE(obj) \ | |
| 23 | OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) | |
| 183930c0 DG |
24 | #define SPAPR_MACHINE_GET_CLASS(obj) \ |
| 25 | OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE) | |
| 26 | #define SPAPR_MACHINE_CLASS(klass) \ | |
| 27 | OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE) | |
| 28 | ||
| 29 | /** | |
| 30 | * sPAPRMachineClass: | |
| 31 | */ | |
| 32 | struct sPAPRMachineClass { | |
| 33 | /*< private >*/ | |
| 34 | MachineClass parent_class; | |
| 35 | ||
| 36 | /*< public >*/ | |
| 37 | }; | |
| 28e02042 DG |
38 | |
| 39 | /** | |
| 40 | * sPAPRMachineState: | |
| 41 | */ | |
| 42 | struct sPAPRMachineState { | |
| 43 | /*< private >*/ | |
| 44 | MachineState parent_obj; | |
| 45 | ||
| 4040ab72 | 46 | struct VIOsPAPRBus *vio_bus; |
| 3384f95c | 47 | QLIST_HEAD(, sPAPRPHBState) phbs; |
| 639e8102 | 48 | struct sPAPRNVRAM *nvram; |
| c04d6cfa | 49 | XICSState *icp; |
| 28df36a1 | 50 | DeviceState *rtc; |
| a3467baa DG |
51 | |
| 52 | void *htab; | |
| 4be21d56 | 53 | uint32_t htab_shift; |
| a8170e5e | 54 | hwaddr rma_size; |
| 7f763a5d | 55 | int vrma_adjust; |
| a8170e5e | 56 | hwaddr fdt_addr, rtas_addr; |
| b7d1f77a BH |
57 | ssize_t rtas_size; |
| 58 | void *rtas_blob; | |
| a3467baa | 59 | void *fdt_skel; |
| 880ae7de | 60 | uint64_t rtc_offset; /* Now used only during incoming migration */ |
| 98a8b524 | 61 | struct PPCTimebase tb; |
| 3fc5acde | 62 | bool has_graphics; |
| 74d042e5 | 63 | |
| 31fe14d1 | 64 | uint32_t check_exception_irq; |
| 74d042e5 | 65 | Notifier epow_notifier; |
| 31fe14d1 | 66 | QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; |
| 4be21d56 DG |
67 | |
| 68 | /* Migration state */ | |
| 69 | int htab_save_index; | |
| 70 | bool htab_first_pass; | |
| e68cb8b4 | 71 | int htab_fd; |
| 01a57972 | 72 | bool htab_fd_stale; |
| 46503c2b MR |
73 | |
| 74 | /* RTAS state */ | |
| 75 | QTAILQ_HEAD(, sPAPRConfigureConnectorState) ccs_list; | |
| 28e02042 DG |
76 | |
| 77 | /*< public >*/ | |
| 78 | char *kvm_type; | |
| 79 | }; | |
| 9fdf0c29 DG |
80 | |
| 81 | #define H_SUCCESS 0 | |
| 82 | #define H_BUSY 1 /* Hardware busy -- retry later */ | |
| 83 | #define H_CLOSED 2 /* Resource closed */ | |
| 84 | #define H_NOT_AVAILABLE 3 | |
| 85 | #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ | |
| 86 | #define H_PARTIAL 5 | |
| 87 | #define H_IN_PROGRESS 14 /* Kind of like busy */ | |
| 88 | #define H_PAGE_REGISTERED 15 | |
| 89 | #define H_PARTIAL_STORE 16 | |
| 90 | #define H_PENDING 17 /* returned from H_POLL_PENDING */ | |
| 91 | #define H_CONTINUE 18 /* Returned from H_Join on success */ | |
| 92 | #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ | |
| 93 | #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ | |
| 94 | is a good time to retry */ | |
| 95 | #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ | |
| 96 | is a good time to retry */ | |
| 97 | #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ | |
| 98 | is a good time to retry */ | |
| 99 | #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ | |
| 100 | is a good time to retry */ | |
| 101 | #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ | |
| 102 | is a good time to retry */ | |
| 103 | #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ | |
| 104 | is a good time to retry */ | |
| 105 | #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ | |
| 106 | #define H_HARDWARE -1 /* Hardware error */ | |
| 107 | #define H_FUNCTION -2 /* Function not supported */ | |
| 108 | #define H_PRIVILEGE -3 /* Caller not privileged */ | |
| 109 | #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ | |
| 110 | #define H_BAD_MODE -5 /* Illegal msr value */ | |
| 111 | #define H_PTEG_FULL -6 /* PTEG is full */ | |
| 112 | #define H_NOT_FOUND -7 /* PTE was not found" */ | |
| 113 | #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ | |
| 114 | #define H_NO_MEM -9 | |
| 115 | #define H_AUTHORITY -10 | |
| 116 | #define H_PERMISSION -11 | |
| 117 | #define H_DROPPED -12 | |
| 118 | #define H_SOURCE_PARM -13 | |
| 119 | #define H_DEST_PARM -14 | |
| 120 | #define H_REMOTE_PARM -15 | |
| 121 | #define H_RESOURCE -16 | |
| 122 | #define H_ADAPTER_PARM -17 | |
| 123 | #define H_RH_PARM -18 | |
| 124 | #define H_RCQ_PARM -19 | |
| 125 | #define H_SCQ_PARM -20 | |
| 126 | #define H_EQ_PARM -21 | |
| 127 | #define H_RT_PARM -22 | |
| 128 | #define H_ST_PARM -23 | |
| 129 | #define H_SIGT_PARM -24 | |
| 130 | #define H_TOKEN_PARM -25 | |
| 131 | #define H_MLENGTH_PARM -27 | |
| 132 | #define H_MEM_PARM -28 | |
| 133 | #define H_MEM_ACCESS_PARM -29 | |
| 134 | #define H_ATTR_PARM -30 | |
| 135 | #define H_PORT_PARM -31 | |
| 136 | #define H_MCG_PARM -32 | |
| 137 | #define H_VL_PARM -33 | |
| 138 | #define H_TSIZE_PARM -34 | |
| 139 | #define H_TRACE_PARM -35 | |
| 140 | ||
| 141 | #define H_MASK_PARM -37 | |
| 142 | #define H_MCG_FULL -38 | |
| 143 | #define H_ALIAS_EXIST -39 | |
| 144 | #define H_P_COUNTER -40 | |
| 145 | #define H_TABLE_FULL -41 | |
| 146 | #define H_ALT_TABLE -42 | |
| 147 | #define H_MR_CONDITION -43 | |
| 148 | #define H_NOT_ENOUGH_RESOURCES -44 | |
| 149 | #define H_R_STATE -45 | |
| 150 | #define H_RESCINDEND -46 | |
| 42561bf2 AB |
151 | #define H_P2 -55 |
| 152 | #define H_P3 -56 | |
| 153 | #define H_P4 -57 | |
| 154 | #define H_P5 -58 | |
| 155 | #define H_P6 -59 | |
| 156 | #define H_P7 -60 | |
| 157 | #define H_P8 -61 | |
| 158 | #define H_P9 -62 | |
| 159 | #define H_UNSUPPORTED_FLAG -256 | |
| 9fdf0c29 DG |
160 | #define H_MULTI_THREADS_ACTIVE -9005 |
| 161 | ||
| 162 | ||
| 163 | /* Long Busy is a condition that can be returned by the firmware | |
| 164 | * when a call cannot be completed now, but the identical call | |
| 165 | * should be retried later. This prevents calls blocking in the | |
| 166 | * firmware for long periods of time. Annoyingly the firmware can return | |
| 167 | * a range of return codes, hinting at how long we should wait before | |
| 168 | * retrying. If you don't care for the hint, the macro below is a good | |
| 169 | * way to check for the long_busy return codes | |
| 170 | */ | |
| 171 | #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ | |
| 172 | && (x <= H_LONG_BUSY_END_RANGE)) | |
| 173 | ||
| 174 | /* Flags */ | |
| 175 | #define H_LARGE_PAGE (1ULL<<(63-16)) | |
| 176 | #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ | |
| 177 | #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ | |
| 178 | #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ | |
| 179 | #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) | |
| 180 | #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) | |
| 181 | #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) | |
| 182 | #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) | |
| 183 | #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE | |
| 184 | #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ | |
| 185 | #define H_ANDCOND (1ULL<<(63-33)) | |
| 186 | #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ | |
| 187 | #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ | |
| 188 | #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ | |
| 189 | #define H_COPY_PAGE (1ULL<<(63-49)) | |
| 190 | #define H_N (1ULL<<(63-61)) | |
| 191 | #define H_PP1 (1ULL<<(63-62)) | |
| 192 | #define H_PP2 (1ULL<<(63-63)) | |
| 193 | ||
| a46622fd AK |
194 | /* Values for 2nd argument to H_SET_MODE */ |
| 195 | #define H_SET_MODE_RESOURCE_SET_CIABR 1 | |
| 196 | #define H_SET_MODE_RESOURCE_SET_DAWR 2 | |
| 197 | #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 | |
| 198 | #define H_SET_MODE_RESOURCE_LE 4 | |
| 199 | ||
| 200 | /* Flags for H_SET_MODE_RESOURCE_LE */ | |
| 42561bf2 AB |
201 | #define H_SET_MODE_ENDIAN_BIG 0 |
| 202 | #define H_SET_MODE_ENDIAN_LITTLE 1 | |
| 203 | ||
| d5ac4f54 AK |
204 | /* Flags for H_SET_MODE_RESOURCE_ADDR_TRANS_MODE */ |
| 205 | #define H_SET_MODE_ADDR_TRANS_NONE 0 | |
| 206 | #define H_SET_MODE_ADDR_TRANS_0001_8000 2 | |
| 207 | #define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000 3 | |
| 208 | ||
| 9fdf0c29 DG |
209 | /* VASI States */ |
| 210 | #define H_VASI_INVALID 0 | |
| 211 | #define H_VASI_ENABLED 1 | |
| 212 | #define H_VASI_ABORTED 2 | |
| 213 | #define H_VASI_SUSPENDING 3 | |
| 214 | #define H_VASI_SUSPENDED 4 | |
| 215 | #define H_VASI_RESUMED 5 | |
| 216 | #define H_VASI_COMPLETED 6 | |
| 217 | ||
| 218 | /* DABRX flags */ | |
| 219 | #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) | |
| 220 | #define H_DABRX_KERNEL (1ULL<<(63-62)) | |
| 221 | #define H_DABRX_USER (1ULL<<(63-63)) | |
| 222 | ||
| 66a0a2cb | 223 | /* Each control block has to be on a 4K boundary */ |
| 9fdf0c29 DG |
224 | #define H_CB_ALIGNMENT 4096 |
| 225 | ||
| 226 | /* pSeries hypervisor opcodes */ | |
| 227 | #define H_REMOVE 0x04 | |
| 228 | #define H_ENTER 0x08 | |
| 229 | #define H_READ 0x0c | |
| 230 | #define H_CLEAR_MOD 0x10 | |
| 231 | #define H_CLEAR_REF 0x14 | |
| 232 | #define H_PROTECT 0x18 | |
| 233 | #define H_GET_TCE 0x1c | |
| 234 | #define H_PUT_TCE 0x20 | |
| 235 | #define H_SET_SPRG0 0x24 | |
| 236 | #define H_SET_DABR 0x28 | |
| 237 | #define H_PAGE_INIT 0x2c | |
| 238 | #define H_SET_ASR 0x30 | |
| 239 | #define H_ASR_ON 0x34 | |
| 240 | #define H_ASR_OFF 0x38 | |
| 241 | #define H_LOGICAL_CI_LOAD 0x3c | |
| 242 | #define H_LOGICAL_CI_STORE 0x40 | |
| 243 | #define H_LOGICAL_CACHE_LOAD 0x44 | |
| 244 | #define H_LOGICAL_CACHE_STORE 0x48 | |
| 245 | #define H_LOGICAL_ICBI 0x4c | |
| 246 | #define H_LOGICAL_DCBF 0x50 | |
| 247 | #define H_GET_TERM_CHAR 0x54 | |
| 248 | #define H_PUT_TERM_CHAR 0x58 | |
| 249 | #define H_REAL_TO_LOGICAL 0x5c | |
| 250 | #define H_HYPERVISOR_DATA 0x60 | |
| 251 | #define H_EOI 0x64 | |
| 252 | #define H_CPPR 0x68 | |
| 253 | #define H_IPI 0x6c | |
| 254 | #define H_IPOLL 0x70 | |
| 255 | #define H_XIRR 0x74 | |
| 256 | #define H_PERFMON 0x7c | |
| 257 | #define H_MIGRATE_DMA 0x78 | |
| 258 | #define H_REGISTER_VPA 0xDC | |
| 259 | #define H_CEDE 0xE0 | |
| 260 | #define H_CONFER 0xE4 | |
| 261 | #define H_PROD 0xE8 | |
| 262 | #define H_GET_PPP 0xEC | |
| 263 | #define H_SET_PPP 0xF0 | |
| 264 | #define H_PURR 0xF4 | |
| 265 | #define H_PIC 0xF8 | |
| 266 | #define H_REG_CRQ 0xFC | |
| 267 | #define H_FREE_CRQ 0x100 | |
| 268 | #define H_VIO_SIGNAL 0x104 | |
| 269 | #define H_SEND_CRQ 0x108 | |
| 270 | #define H_COPY_RDMA 0x110 | |
| 271 | #define H_REGISTER_LOGICAL_LAN 0x114 | |
| 272 | #define H_FREE_LOGICAL_LAN 0x118 | |
| 273 | #define H_ADD_LOGICAL_LAN_BUFFER 0x11C | |
| 274 | #define H_SEND_LOGICAL_LAN 0x120 | |
| 275 | #define H_BULK_REMOVE 0x124 | |
| 276 | #define H_MULTICAST_CTRL 0x130 | |
| 277 | #define H_SET_XDABR 0x134 | |
| 278 | #define H_STUFF_TCE 0x138 | |
| 279 | #define H_PUT_TCE_INDIRECT 0x13C | |
| 280 | #define H_CHANGE_LOGICAL_LAN_MAC 0x14C | |
| 281 | #define H_VTERM_PARTNER_INFO 0x150 | |
| 282 | #define H_REGISTER_VTERM 0x154 | |
| 283 | #define H_FREE_VTERM 0x158 | |
| 284 | #define H_RESET_EVENTS 0x15C | |
| 285 | #define H_ALLOC_RESOURCE 0x160 | |
| 286 | #define H_FREE_RESOURCE 0x164 | |
| 287 | #define H_MODIFY_QP 0x168 | |
| 288 | #define H_QUERY_QP 0x16C | |
| 289 | #define H_REREGISTER_PMR 0x170 | |
| 290 | #define H_REGISTER_SMR 0x174 | |
| 291 | #define H_QUERY_MR 0x178 | |
| 292 | #define H_QUERY_MW 0x17C | |
| 293 | #define H_QUERY_HCA 0x180 | |
| 294 | #define H_QUERY_PORT 0x184 | |
| 295 | #define H_MODIFY_PORT 0x188 | |
| 296 | #define H_DEFINE_AQP1 0x18C | |
| 297 | #define H_GET_TRACE_BUFFER 0x190 | |
| 298 | #define H_DEFINE_AQP0 0x194 | |
| 299 | #define H_RESIZE_MR 0x198 | |
| 300 | #define H_ATTACH_MCQP 0x19C | |
| 301 | #define H_DETACH_MCQP 0x1A0 | |
| 302 | #define H_CREATE_RPT 0x1A4 | |
| 303 | #define H_REMOVE_RPT 0x1A8 | |
| 304 | #define H_REGISTER_RPAGES 0x1AC | |
| 305 | #define H_DISABLE_AND_GETC 0x1B0 | |
| 306 | #define H_ERROR_DATA 0x1B4 | |
| 307 | #define H_GET_HCA_INFO 0x1B8 | |
| 308 | #define H_GET_PERF_COUNT 0x1BC | |
| 309 | #define H_MANAGE_TRACE 0x1C0 | |
| 310 | #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 | |
| 311 | #define H_QUERY_INT_STATE 0x1E4 | |
| 312 | #define H_POLL_PENDING 0x1D8 | |
| 313 | #define H_ILLAN_ATTRIBUTES 0x244 | |
| 314 | #define H_MODIFY_HEA_QP 0x250 | |
| 315 | #define H_QUERY_HEA_QP 0x254 | |
| 316 | #define H_QUERY_HEA 0x258 | |
| 317 | #define H_QUERY_HEA_PORT 0x25C | |
| 318 | #define H_MODIFY_HEA_PORT 0x260 | |
| 319 | #define H_REG_BCMC 0x264 | |
| 320 | #define H_DEREG_BCMC 0x268 | |
| 321 | #define H_REGISTER_HEA_RPAGES 0x26C | |
| 322 | #define H_DISABLE_AND_GET_HEA 0x270 | |
| 323 | #define H_GET_HEA_INFO 0x274 | |
| 324 | #define H_ALLOC_HEA_RESOURCE 0x278 | |
| 325 | #define H_ADD_CONN 0x284 | |
| 326 | #define H_DEL_CONN 0x288 | |
| 327 | #define H_JOIN 0x298 | |
| 328 | #define H_VASI_STATE 0x2A4 | |
| 329 | #define H_ENABLE_CRQ 0x2B0 | |
| 330 | #define H_GET_EM_PARMS 0x2B8 | |
| 331 | #define H_SET_MPP 0x2D0 | |
| 332 | #define H_GET_MPP 0x2D4 | |
| 5d87e4b7 | 333 | #define H_XIRR_X 0x2FC |
| 42561bf2 AB |
334 | #define H_SET_MODE 0x31C |
| 335 | #define MAX_HCALL_OPCODE H_SET_MODE | |
| 9fdf0c29 | 336 | |
| 39ac8455 DG |
337 | /* The hcalls above are standardized in PAPR and implemented by pHyp |
| 338 | * as well. | |
| 339 | * | |
| 340 | * We also need some hcalls which are specific to qemu / KVM-on-POWER. | |
| 341 | * So far we just need one for H_RTAS, but in future we'll need more | |
| 342 | * for extensions like virtio. We put those into the 0xf000-0xfffc | |
| 343 | * range which is reserved by PAPR for "platform-specific" hcalls. | |
| 344 | */ | |
| 345 | #define KVMPPC_HCALL_BASE 0xf000 | |
| 346 | #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) | |
| c73e3771 | 347 | #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) |
| 2a6593cb AK |
348 | /* Client Architecture support */ |
| 349 | #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) | |
| 350 | #define KVMPPC_HCALL_MAX KVMPPC_H_CAS | |
| 39ac8455 | 351 | |
| 2a6593cb AK |
352 | typedef struct sPAPRDeviceTreeUpdateHeader { |
| 353 | uint32_t version_id; | |
| 354 | } sPAPRDeviceTreeUpdateHeader; | |
| 355 | ||
| 9fdf0c29 | 356 | #define hcall_dprintf(fmt, ...) \ |
| aaf87c66 TH |
357 | do { \ |
| 358 | qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ | |
| 359 | } while (0) | |
| 9fdf0c29 | 360 | |
| 28e02042 | 361 | typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, |
| 9fdf0c29 DG |
362 | target_ulong opcode, |
| 363 | target_ulong *args); | |
| 364 | ||
| 365 | void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); | |
| aa100fa4 | 366 | target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, |
| 9fdf0c29 DG |
367 | target_ulong *args); |
| 368 | ||
| ff9d2afa | 369 | int spapr_allocate_irq(int hint, bool lsi); |
| f1c2dc7c | 370 | int spapr_allocate_irq_block(int num, bool lsi, bool msi); |
| d07fee7e | 371 | |
| ee954280 GS |
372 | /* ibm,set-eeh-option */ |
| 373 | #define RTAS_EEH_DISABLE 0 | |
| 374 | #define RTAS_EEH_ENABLE 1 | |
| 375 | #define RTAS_EEH_THAW_IO 2 | |
| 376 | #define RTAS_EEH_THAW_DMA 3 | |
| 377 | ||
| 378 | /* ibm,get-config-addr-info2 */ | |
| 379 | #define RTAS_GET_PE_ADDR 0 | |
| 380 | #define RTAS_GET_PE_MODE 1 | |
| 381 | #define RTAS_PE_MODE_NONE 0 | |
| 382 | #define RTAS_PE_MODE_NOT_SHARED 1 | |
| 383 | #define RTAS_PE_MODE_SHARED 2 | |
| 384 | ||
| 385 | /* ibm,read-slot-reset-state2 */ | |
| 386 | #define RTAS_EEH_PE_STATE_NORMAL 0 | |
| 387 | #define RTAS_EEH_PE_STATE_RESET 1 | |
| 388 | #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 | |
| 389 | #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 | |
| 390 | #define RTAS_EEH_PE_STATE_UNAVAIL 5 | |
| 391 | #define RTAS_EEH_NOT_SUPPORT 0 | |
| 392 | #define RTAS_EEH_SUPPORT 1 | |
| 393 | #define RTAS_EEH_PE_UNAVAIL_INFO 1000 | |
| 394 | #define RTAS_EEH_PE_RECOVER_INFO 0 | |
| 395 | ||
| 396 | /* ibm,set-slot-reset */ | |
| 397 | #define RTAS_SLOT_RESET_DEACTIVATE 0 | |
| 398 | #define RTAS_SLOT_RESET_HOT 1 | |
| 399 | #define RTAS_SLOT_RESET_FUNDAMENTAL 3 | |
| 400 | ||
| 401 | /* ibm,slot-error-detail */ | |
| 402 | #define RTAS_SLOT_TEMP_ERR_LOG 1 | |
| 403 | #define RTAS_SLOT_PERM_ERR_LOG 2 | |
| 404 | ||
| a64d325d AK |
405 | /* RTAS return codes */ |
| 406 | #define RTAS_OUT_SUCCESS 0 | |
| 407 | #define RTAS_OUT_NO_ERRORS_FOUND 1 | |
| 408 | #define RTAS_OUT_HW_ERROR -1 | |
| 409 | #define RTAS_OUT_BUSY -2 | |
| 410 | #define RTAS_OUT_PARAM_ERROR -3 | |
| 3ada6b11 AK |
411 | #define RTAS_OUT_NOT_SUPPORTED -3 |
| 412 | #define RTAS_OUT_NOT_AUTHORIZED -9002 | |
| a64d325d | 413 | |
| 3a3b8502 AK |
414 | /* RTAS tokens */ |
| 415 | #define RTAS_TOKEN_BASE 0x2000 | |
| 416 | ||
| 417 | #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) | |
| 418 | #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) | |
| 419 | #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) | |
| 420 | #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) | |
| 421 | #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) | |
| 422 | #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) | |
| 423 | #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) | |
| 424 | #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) | |
| 425 | #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) | |
| 426 | #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) | |
| 427 | #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) | |
| 428 | #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) | |
| 429 | #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) | |
| 430 | #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) | |
| 431 | #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) | |
| 432 | #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) | |
| 433 | #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) | |
| 434 | #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) | |
| 435 | #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) | |
| 436 | #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) | |
| 437 | #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) | |
| 438 | #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) | |
| 439 | #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) | |
| 440 | #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) | |
| 441 | #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) | |
| 442 | #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) | |
| 443 | #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) | |
| 444 | #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) | |
| 445 | #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) | |
| 446 | #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) | |
| 447 | #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) | |
| 448 | #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) | |
| ee954280 GS |
449 | #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) |
| 450 | #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) | |
| 451 | #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) | |
| 452 | #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) | |
| 453 | #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) | |
| 454 | #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) | |
| 455 | ||
| 456 | #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x26) | |
| 3a3b8502 | 457 | |
| 3052d951 | 458 | /* RTAS ibm,get-system-parameter token values */ |
| 3b50d897 | 459 | #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 |
| 3052d951 | 460 | #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 |
| b907d7b0 | 461 | #define RTAS_SYSPARM_UUID 48 |
| 3052d951 | 462 | |
| 8c8639df MD |
463 | /* RTAS indicator/sensor types |
| 464 | * | |
| 465 | * as defined by PAPR+ 2.7 7.3.5.4, Table 41 | |
| 466 | * | |
| 467 | * NOTE: currently only DR-related sensors are implemented here | |
| 468 | */ | |
| 469 | #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 | |
| 470 | #define RTAS_SENSOR_TYPE_DR 9002 | |
| 471 | #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 | |
| 472 | #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE | |
| 473 | ||
| 3052d951 S |
474 | /* Possible values for the platform-processor-diagnostics-run-mode parameter |
| 475 | * of the RTAS ibm,get-system-parameter call. | |
| 476 | */ | |
| 477 | #define DIAGNOSTICS_RUN_MODE_DISABLED 0 | |
| 478 | #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 | |
| 479 | #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 | |
| 480 | #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 | |
| 481 | ||
| 4fe822e0 AK |
482 | static inline uint64_t ppc64_phys_to_real(uint64_t addr) |
| 483 | { | |
| 484 | return addr & ~0xF000000000000000ULL; | |
| 485 | } | |
| 486 | ||
| 39ac8455 DG |
487 | static inline uint32_t rtas_ld(target_ulong phys, int n) |
| 488 | { | |
| fdfba1a2 | 489 | return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); |
| 39ac8455 DG |
490 | } |
| 491 | ||
| a14aa92b GS |
492 | static inline uint64_t rtas_ldq(target_ulong phys, int n) |
| 493 | { | |
| 494 | return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); | |
| 495 | } | |
| 496 | ||
| 39ac8455 DG |
497 | static inline void rtas_st(target_ulong phys, int n, uint32_t val) |
| 498 | { | |
| ab1da857 | 499 | stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); |
| 39ac8455 DG |
500 | } |
| 501 | ||
| ab316865 MR |
502 | static inline void rtas_st_buffer_direct(target_ulong phys, |
| 503 | target_ulong phys_len, | |
| 504 | uint8_t *buffer, uint16_t buffer_len) | |
| 505 | { | |
| 506 | cpu_physical_memory_write(ppc64_phys_to_real(phys), buffer, | |
| 507 | MIN(buffer_len, phys_len)); | |
| 508 | } | |
| ce3fa1ec S |
509 | |
| 510 | static inline void rtas_st_buffer(target_ulong phys, target_ulong phys_len, | |
| 511 | uint8_t *buffer, uint16_t buffer_len) | |
| 512 | { | |
| 513 | if (phys_len < 2) { | |
| 514 | return; | |
| 515 | } | |
| 516 | stw_be_phys(&address_space_memory, | |
| 517 | ppc64_phys_to_real(phys), buffer_len); | |
| ab316865 | 518 | rtas_st_buffer_direct(phys + 2, phys_len - 2, buffer, buffer_len); |
| ce3fa1ec S |
519 | } |
| 520 | ||
| 28e02042 | 521 | typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, |
| 210b580b | 522 | uint32_t token, |
| 39ac8455 DG |
523 | uint32_t nargs, target_ulong args, |
| 524 | uint32_t nret, target_ulong rets); | |
| 3a3b8502 | 525 | void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); |
| 28e02042 | 526 | target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm, |
| 39ac8455 DG |
527 | uint32_t token, uint32_t nargs, target_ulong args, |
| 528 | uint32_t nret, target_ulong rets); | |
| a8170e5e AK |
529 | int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr, |
| 530 | hwaddr rtas_size); | |
| 39ac8455 | 531 | |
| ad0ebb91 DG |
532 | #define SPAPR_TCE_PAGE_SHIFT 12 |
| 533 | #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) | |
| 534 | #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) | |
| 535 | ||
| ad0ebb91 | 536 | #define SPAPR_VIO_BASE_LIOBN 0x00000000 |
| 4290ca49 | 537 | #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) |
| c8545818 AK |
538 | #define SPAPR_PCI_LIOBN(phb_index, window_num) \ |
| 539 | (0x80000000 | ((phb_index) << 8) | (window_num)) | |
| d9d96a3c | 540 | #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) |
| c8545818 | 541 | #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) |
| ad0ebb91 | 542 | |
| 74d042e5 DG |
543 | #define RTAS_ERROR_LOG_MAX 2048 |
| 544 | ||
| 79853e18 TD |
545 | #define RTAS_EVENT_SCAN_RATE 1 |
| 546 | ||
| 2b7dc949 | 547 | typedef struct sPAPRTCETable sPAPRTCETable; |
| 74d042e5 | 548 | |
| a83000f5 AL |
549 | #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" |
| 550 | #define SPAPR_TCE_TABLE(obj) \ | |
| 551 | OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) | |
| 552 | ||
| 553 | struct sPAPRTCETable { | |
| 554 | DeviceState parent; | |
| 555 | uint32_t liobn; | |
| a83000f5 | 556 | uint32_t nb_table; |
| 1b8eceee | 557 | uint64_t bus_offset; |
| 650f33ad | 558 | uint32_t page_shift; |
| a83000f5 AL |
559 | uint64_t *table; |
| 560 | bool bypass; | |
| 9bb62a07 | 561 | bool vfio_accel; |
| a83000f5 AL |
562 | int fd; |
| 563 | MemoryRegion iommu; | |
| ee9a569a | 564 | struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ |
| a83000f5 AL |
565 | QLIST_ENTRY(sPAPRTCETable) list; |
| 566 | }; | |
| 567 | ||
| f9ce8e0a | 568 | sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn); |
| 31fe14d1 NF |
569 | |
| 570 | struct sPAPREventLogEntry { | |
| 571 | int log_type; | |
| 79853e18 | 572 | bool exception; |
| 31fe14d1 NF |
573 | void *data; |
| 574 | QTAILQ_ENTRY(sPAPREventLogEntry) next; | |
| 575 | }; | |
| 576 | ||
| 28e02042 | 577 | void spapr_events_init(sPAPRMachineState *sm); |
| 74d042e5 | 578 | void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq); |
| 28e02042 DG |
579 | int spapr_h_cas_compose_response(sPAPRMachineState *sm, |
| 580 | target_ulong addr, target_ulong size); | |
| 84af6d9f | 581 | sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, |
| 1b8eceee | 582 | uint64_t bus_offset, |
| 650f33ad | 583 | uint32_t page_shift, |
| 9bb62a07 AK |
584 | uint32_t nb_table, |
| 585 | bool vfio_accel); | |
| a84bb436 | 586 | MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); |
| ad0ebb91 | 587 | int spapr_dma_dt(void *fdt, int node_off, const char *propname, |
| 5c4cbcf2 AK |
588 | uint32_t liobn, uint64_t window, uint32_t size); |
| 589 | int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, | |
| 2b7dc949 | 590 | sPAPRTCETable *tcet); |
| eefaccc0 | 591 | void spapr_pci_switch_vga(bool big_endian); |
| 31fe14d1 NF |
592 | void spapr_hotplug_req_add_event(sPAPRDRConnector *drc); |
| 593 | void spapr_hotplug_req_remove_event(sPAPRDRConnector *drc); | |
| 28df36a1 | 594 | |
| 46503c2b MR |
595 | /* rtas-configure-connector state */ |
| 596 | struct sPAPRConfigureConnectorState { | |
| 597 | uint32_t drc_index; | |
| 598 | int fdt_offset; | |
| 599 | int fdt_depth; | |
| 600 | QTAILQ_ENTRY(sPAPRConfigureConnectorState) next; | |
| 601 | }; | |
| 602 | ||
| 603 | void spapr_ccs_reset_hook(void *opaque); | |
| 604 | ||
| 28df36a1 DG |
605 | #define TYPE_SPAPR_RTC "spapr-rtc" |
| 606 | ||
| 607 | void spapr_rtc_read(DeviceState *dev, struct tm *tm, uint32_t *ns); | |
| 880ae7de | 608 | int spapr_rtc_import_offset(DeviceState *dev, int64_t legacy_offset); |
| ad0ebb91 | 609 | |
| db4ef288 BR |
610 | #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */ |
| 611 | ||
| 9fdf0c29 | 612 | #endif /* !defined (__HW_SPAPR_H__) */ |