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82cffa2e CLG |
1 | /* |
2 | * QEMU PowerPC sPAPR IRQ backend definitions | |
3 | * | |
4 | * Copyright (c) 2018, IBM Corporation. | |
5 | * | |
6 | * This code is licensed under the GPL version 2 or later. See the | |
7 | * COPYING file in the top-level directory. | |
8 | */ | |
9 | ||
10 | #ifndef HW_SPAPR_IRQ_H | |
11 | #define HW_SPAPR_IRQ_H | |
12 | ||
ec150c7e | 13 | #include "target/ppc/cpu-qom.h" |
db1015e9 | 14 | #include "qom/object.h" |
ec150c7e | 15 | |
82cffa2e CLG |
16 | /* |
17 | * IRQ range offsets per device type | |
18 | */ | |
dcc345b6 | 19 | #define SPAPR_IRQ_IPI 0x0 |
82cffa2e | 20 | |
ad8de986 DG |
21 | #define SPAPR_XIRQ_BASE XICS_IRQ_BASE /* 0x1000 */ |
22 | #define SPAPR_IRQ_EPOW (SPAPR_XIRQ_BASE + 0x0000) | |
23 | #define SPAPR_IRQ_HOTPLUG (SPAPR_XIRQ_BASE + 0x0001) | |
24 | #define SPAPR_IRQ_VIO (SPAPR_XIRQ_BASE + 0x0100) /* 256 VIO devices */ | |
25 | #define SPAPR_IRQ_PCI_LSI (SPAPR_XIRQ_BASE + 0x0200) /* 32+ PHBs devices */ | |
26 | ||
27 | /* Offset of the dynamic range covered by the bitmap allocator */ | |
28 | #define SPAPR_IRQ_MSI (SPAPR_XIRQ_BASE + 0x0300) | |
29 | ||
30 | #define SPAPR_NR_XIRQS 0x1000 | |
82cffa2e | 31 | |
82d1e74f | 32 | struct SpaprMachineState; |
82cffa2e | 33 | |
150e25f8 DG |
34 | typedef struct SpaprInterruptController SpaprInterruptController; |
35 | ||
36 | #define TYPE_SPAPR_INTC "spapr-interrupt-controller" | |
37 | #define SPAPR_INTC(obj) \ | |
38 | INTERFACE_CHECK(SpaprInterruptController, (obj), TYPE_SPAPR_INTC) | |
db1015e9 | 39 | typedef struct SpaprInterruptControllerClass SpaprInterruptControllerClass; |
8110fa1d EH |
40 | DECLARE_CLASS_CHECKERS(SpaprInterruptControllerClass, SPAPR_INTC, |
41 | TYPE_SPAPR_INTC) | |
150e25f8 | 42 | |
db1015e9 | 43 | struct SpaprInterruptControllerClass { |
150e25f8 | 44 | InterfaceClass parent; |
ebd6be08 | 45 | |
4ffb7496 GK |
46 | int (*activate)(SpaprInterruptController *intc, uint32_t nr_servers, |
47 | Error **errp); | |
81106ddd DG |
48 | void (*deactivate)(SpaprInterruptController *intc); |
49 | ||
ebd6be08 DG |
50 | /* |
51 | * These methods will typically be called on all intcs, active and | |
52 | * inactive | |
53 | */ | |
54 | int (*cpu_intc_create)(SpaprInterruptController *intc, | |
55 | PowerPCCPU *cpu, Error **errp); | |
d49e8a9b | 56 | void (*cpu_intc_reset)(SpaprInterruptController *intc, PowerPCCPU *cpu); |
0990ce6a | 57 | void (*cpu_intc_destroy)(SpaprInterruptController *intc, PowerPCCPU *cpu); |
0b0e52b1 DG |
58 | int (*claim_irq)(SpaprInterruptController *intc, int irq, bool lsi, |
59 | Error **errp); | |
60 | void (*free_irq)(SpaprInterruptController *intc, int irq); | |
7bcdbcca DG |
61 | |
62 | /* These methods should only be called on the active intc */ | |
63 | void (*set_irq)(SpaprInterruptController *intc, int irq, int val); | |
328d8eb2 | 64 | void (*print_info)(SpaprInterruptController *intc, Monitor *mon); |
05289273 DG |
65 | void (*dt)(SpaprInterruptController *intc, uint32_t nr_servers, |
66 | void *fdt, uint32_t phandle); | |
605994e5 | 67 | int (*post_load)(SpaprInterruptController *intc, int version_id); |
db1015e9 | 68 | }; |
150e25f8 | 69 | |
82d1e74f | 70 | void spapr_irq_update_active_intc(struct SpaprMachineState *spapr); |
81106ddd | 71 | |
82d1e74f | 72 | int spapr_irq_cpu_intc_create(struct SpaprMachineState *spapr, |
ebd6be08 | 73 | PowerPCCPU *cpu, Error **errp); |
82d1e74f EH |
74 | void spapr_irq_cpu_intc_reset(struct SpaprMachineState *spapr, PowerPCCPU *cpu); |
75 | void spapr_irq_cpu_intc_destroy(struct SpaprMachineState *spapr, PowerPCCPU *cpu); | |
76 | void spapr_irq_print_info(struct SpaprMachineState *spapr, Monitor *mon); | |
77 | void spapr_irq_dt(struct SpaprMachineState *spapr, uint32_t nr_servers, | |
05289273 | 78 | void *fdt, uint32_t phandle); |
ebd6be08 | 79 | |
82d1e74f EH |
80 | uint32_t spapr_irq_nr_msis(struct SpaprMachineState *spapr); |
81 | int spapr_irq_msi_alloc(struct SpaprMachineState *spapr, uint32_t num, bool align, | |
82cffa2e | 82 | Error **errp); |
82d1e74f | 83 | void spapr_irq_msi_free(struct SpaprMachineState *spapr, int irq, uint32_t num); |
82cffa2e | 84 | |
ce2918cb | 85 | typedef struct SpaprIrq { |
ca62823b DG |
86 | bool xics; |
87 | bool xive; | |
ce2918cb | 88 | } SpaprIrq; |
ef01ed9d | 89 | |
ce2918cb DG |
90 | extern SpaprIrq spapr_irq_xics; |
91 | extern SpaprIrq spapr_irq_xics_legacy; | |
92 | extern SpaprIrq spapr_irq_xive; | |
93 | extern SpaprIrq spapr_irq_dual; | |
ef01ed9d | 94 | |
82d1e74f EH |
95 | void spapr_irq_init(struct SpaprMachineState *spapr, Error **errp); |
96 | int spapr_irq_claim(struct SpaprMachineState *spapr, int irq, bool lsi, Error **errp); | |
97 | void spapr_irq_free(struct SpaprMachineState *spapr, int irq, int num); | |
98 | qemu_irq spapr_qirq(struct SpaprMachineState *spapr, int irq); | |
99 | int spapr_irq_post_load(struct SpaprMachineState *spapr, int version_id); | |
100 | void spapr_irq_reset(struct SpaprMachineState *spapr, Error **errp); | |
101 | int spapr_irq_get_phandle(struct SpaprMachineState *spapr, void *fdt, Error **errp); | |
4ffb7496 GK |
102 | |
103 | typedef int (*SpaprInterruptControllerInitKvm)(SpaprInterruptController *, | |
104 | uint32_t, Error **); | |
105 | ||
106 | int spapr_irq_init_kvm(SpaprInterruptControllerInitKvm fn, | |
567192d4 | 107 | SpaprInterruptController *intc, |
4ffb7496 | 108 | uint32_t nr_servers, |
567192d4 | 109 | Error **errp); |
ef01ed9d CLG |
110 | |
111 | /* | |
112 | * XICS legacy routines | |
113 | */ | |
82d1e74f | 114 | int spapr_irq_find(struct SpaprMachineState *spapr, int num, bool align, Error **errp); |
ef01ed9d CLG |
115 | #define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp) |
116 | ||
82cffa2e | 117 | #endif |