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b20b7b7a MR |
1 | /* |
2 | * QEMU SPAPR Option/Architecture Vector Definitions | |
3 | * | |
4 | * Each architecture option is organized/documented by the following | |
5 | * in LoPAPR 1.1, Table 244: | |
6 | * | |
7 | * <vector number>: the bit-vector in which the option is located | |
8 | * <vector byte>: the byte offset of the vector entry | |
9 | * <vector bit>: the bit offset within the vector entry | |
10 | * | |
11 | * where each vector entry can be one or more bytes. | |
12 | * | |
13 | * Firmware expects a somewhat literal encoding of this bit-vector | |
14 | * structure, where each entry is stored in little-endian so that the | |
15 | * byte ordering reflects that of the documentation, but where each bit | |
16 | * offset is from "left-to-right" in the traditional representation of | |
17 | * a byte value where the MSB is the left-most bit. Thus, each | |
18 | * individual byte encodes the option bits in reverse order of the | |
19 | * documented bit. | |
20 | * | |
21 | * These definitions/helpers attempt to abstract away this internal | |
22 | * representation so that we can define/set/test for individual option | |
23 | * bits using only the documented values. This is done mainly by relying | |
24 | * on a bitmap to approximate the documented "bit-vector" structure and | |
25 | * handling conversations to-from the internal representation under the | |
26 | * covers. | |
27 | * | |
28 | * Copyright IBM Corp. 2016 | |
29 | * | |
30 | * Authors: | |
31 | * Michael Roth <mdroth@linux.vnet.ibm.com> | |
32 | * | |
33 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
34 | * See the COPYING file in the top-level directory. | |
35 | */ | |
a8b991b5 MA |
36 | |
37 | #ifndef SPAPR_OVEC_H | |
38 | #define SPAPR_OVEC_H | |
b20b7b7a MR |
39 | |
40 | #include "cpu.h" | |
41 | ||
ce2918cb | 42 | typedef struct SpaprOptionVector SpaprOptionVector; |
b20b7b7a MR |
43 | |
44 | #define OV_BIT(byte, bit) ((byte - 1) * BITS_PER_BYTE + bit) | |
45 | ||
e957f6a9 SB |
46 | /* option vector 1 */ |
47 | #define OV1_PPC_3_00 OV_BIT(3, 0) /* guest supports PowerPC 3.00? */ | |
48 | ||
facdb8b6 MR |
49 | /* option vector 5 */ |
50 | #define OV5_DRCONF_MEMORY OV_BIT(2, 2) | |
417ece33 | 51 | #define OV5_FORM1_AFFINITY OV_BIT(5, 0) |
e0eb84d4 | 52 | #define OV5_FORM2_AFFINITY OV_BIT(5, 2) |
ffbb1705 | 53 | #define OV5_HP_EVT OV_BIT(6, 5) |
2772cf6b | 54 | #define OV5_HPT_RESIZE OV_BIT(6, 7) |
a324d6f1 | 55 | #define OV5_DRMEM_V2 OV_BIT(22, 0) |
21f3f8db CLG |
56 | #define OV5_XIVE_BOTH OV_BIT(23, 0) |
57 | #define OV5_XIVE_EXPLOIT OV_BIT(23, 1) /* 1=exploitation 0=legacy */ | |
facdb8b6 | 58 | |
9fb4541f SB |
59 | /* ISA 3.00 MMU features: */ |
60 | #define OV5_MMU_BOTH OV_BIT(24, 0) /* Radix and hash */ | |
61 | #define OV5_MMU_RADIX_300 OV_BIT(24, 1) /* 1=Radix only, 0=Hash only */ | |
62 | #define OV5_MMU_RADIX_GTSE OV_BIT(26, 1) /* Radix GTSE */ | |
63 | ||
b20b7b7a | 64 | /* interfaces */ |
ce2918cb DG |
65 | SpaprOptionVector *spapr_ovec_new(void); |
66 | SpaprOptionVector *spapr_ovec_clone(SpaprOptionVector *ov_orig); | |
67 | void spapr_ovec_intersect(SpaprOptionVector *ov, | |
68 | SpaprOptionVector *ov1, | |
69 | SpaprOptionVector *ov2); | |
d1d32d62 | 70 | bool spapr_ovec_subset(SpaprOptionVector *ov1, SpaprOptionVector *ov2); |
ce2918cb DG |
71 | void spapr_ovec_cleanup(SpaprOptionVector *ov); |
72 | void spapr_ovec_set(SpaprOptionVector *ov, long bitnr); | |
73 | void spapr_ovec_clear(SpaprOptionVector *ov, long bitnr); | |
74 | bool spapr_ovec_test(SpaprOptionVector *ov, long bitnr); | |
73598c75 | 75 | bool spapr_ovec_empty(SpaprOptionVector *ov); |
ce2918cb | 76 | SpaprOptionVector *spapr_ovec_parse_vector(target_ulong table_addr, int vector); |
91335a5e DG |
77 | int spapr_dt_ovec(void *fdt, int fdt_offset, |
78 | SpaprOptionVector *ov, const char *name); | |
b20b7b7a | 79 | |
62ef3760 MR |
80 | /* migration */ |
81 | extern const VMStateDescription vmstate_spapr_ovec; | |
82 | ||
a8b991b5 | 83 | #endif /* SPAPR_OVEC_H */ |