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b5cec4c5 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics | |
5 | * | |
6 | * Copyright (c) 2010,2011 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
2a6a4076 MA |
27 | |
28 | #ifndef XICS_H | |
29 | #define XICS_H | |
b5cec4c5 | 30 | |
147ff807 | 31 | #include "hw/qdev.h" |
5c6b487d | 32 | #include "target/ppc/cpu-qom.h" |
c04d6cfa | 33 | |
b5cec4c5 | 34 | #define XICS_IPI 0x2 |
c04d6cfa AL |
35 | #define XICS_BUID 0x1 |
36 | #define XICS_IRQ_BASE (XICS_BUID << 12) | |
37 | ||
38 | /* | |
39 | * We currently only support one BUID which is our interrupt base | |
40 | * (the kernel implementation supports more but we don't exploit | |
41 | * that yet) | |
42 | */ | |
d1b5682d | 43 | typedef struct ICPStateClass ICPStateClass; |
c04d6cfa | 44 | typedef struct ICPState ICPState; |
99285aae | 45 | typedef struct PnvICPState PnvICPState; |
d1b5682d | 46 | typedef struct ICSStateClass ICSStateClass; |
c04d6cfa AL |
47 | typedef struct ICSState ICSState; |
48 | typedef struct ICSIRQState ICSIRQState; | |
2cd908d0 | 49 | typedef struct XICSFabric XICSFabric; |
c04d6cfa | 50 | |
c04d6cfa AL |
51 | #define TYPE_ICP "icp" |
52 | #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP) | |
53 | ||
11ad93f6 DG |
54 | #define TYPE_KVM_ICP "icp-kvm" |
55 | #define KVM_ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_KVM_ICP) | |
56 | ||
99285aae CLG |
57 | #define TYPE_PNV_ICP "pnv-icp" |
58 | #define PNV_ICP(obj) OBJECT_CHECK(PnvICPState, (obj), TYPE_PNV_ICP) | |
59 | ||
d1b5682d AK |
60 | #define ICP_CLASS(klass) \ |
61 | OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP) | |
62 | #define ICP_GET_CLASS(obj) \ | |
63 | OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP) | |
64 | ||
65 | struct ICPStateClass { | |
66 | DeviceClass parent_class; | |
67 | ||
100f7388 GK |
68 | void (*realize)(ICPState *icp, Error **errp); |
69 | void (*pre_save)(ICPState *icp); | |
70 | int (*post_load)(ICPState *icp, int version_id); | |
a4d4edce | 71 | void (*reset)(ICPState *icp); |
d1b5682d AK |
72 | }; |
73 | ||
c04d6cfa AL |
74 | struct ICPState { |
75 | /*< private >*/ | |
76 | DeviceState parent_obj; | |
77 | /*< public >*/ | |
11ad93f6 | 78 | CPUState *cs; |
cc706a53 | 79 | ICSState *xirr_owner; |
c04d6cfa AL |
80 | uint32_t xirr; |
81 | uint8_t pending_priority; | |
82 | uint8_t mfrr; | |
83 | qemu_irq output; | |
d49c603b | 84 | |
2cd908d0 | 85 | XICSFabric *xics; |
c04d6cfa AL |
86 | }; |
87 | ||
ad265631 | 88 | #define ICP_PROP_XICS "xics" |
9ed65663 | 89 | #define ICP_PROP_CPU "cpu" |
ad265631 | 90 | |
99285aae CLG |
91 | struct PnvICPState { |
92 | ICPState parent_obj; | |
93 | ||
94 | MemoryRegion mmio; | |
95 | uint32_t links[3]; | |
96 | }; | |
97 | ||
d4d7a59a BH |
98 | #define TYPE_ICS_BASE "ics-base" |
99 | #define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_BASE) | |
c04d6cfa | 100 | |
d4d7a59a BH |
101 | /* Retain ics for sPAPR for migration from existing sPAPR guests */ |
102 | #define TYPE_ICS_SIMPLE "ics" | |
103 | #define ICS_SIMPLE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SIMPLE) | |
11ad93f6 | 104 | |
d4d7a59a BH |
105 | #define TYPE_ICS_KVM "icskvm" |
106 | #define ICS_KVM(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_KVM) | |
107 | ||
108 | #define ICS_BASE_CLASS(klass) \ | |
109 | OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS_BASE) | |
110 | #define ICS_BASE_GET_CLASS(obj) \ | |
111 | OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS_BASE) | |
d1b5682d AK |
112 | |
113 | struct ICSStateClass { | |
114 | DeviceClass parent_class; | |
115 | ||
100f7388 | 116 | void (*realize)(ICSState *s, Error **errp); |
d1b5682d AK |
117 | void (*pre_save)(ICSState *s); |
118 | int (*post_load)(ICSState *s, int version_id); | |
d4d7a59a BH |
119 | void (*reject)(ICSState *s, uint32_t irq); |
120 | void (*resend)(ICSState *s); | |
121 | void (*eoi)(ICSState *s, uint32_t irq); | |
d1b5682d AK |
122 | }; |
123 | ||
c04d6cfa AL |
124 | struct ICSState { |
125 | /*< private >*/ | |
126 | DeviceState parent_obj; | |
127 | /*< public >*/ | |
128 | uint32_t nr_irqs; | |
129 | uint32_t offset; | |
130 | qemu_irq *qirqs; | |
c04d6cfa | 131 | ICSIRQState *irqs; |
b4f27d71 | 132 | XICSFabric *xics; |
c04d6cfa | 133 | }; |
b5cec4c5 | 134 | |
ad265631 GK |
135 | #define ICS_PROP_XICS "xics" |
136 | ||
9c7027ba BH |
137 | static inline bool ics_valid_irq(ICSState *ics, uint32_t nr) |
138 | { | |
15ed653f | 139 | return (ics->offset != 0) && (nr >= ics->offset) |
9c7027ba BH |
140 | && (nr < (ics->offset + ics->nr_irqs)); |
141 | } | |
142 | ||
c04d6cfa AL |
143 | struct ICSIRQState { |
144 | uint32_t server; | |
145 | uint8_t priority; | |
146 | uint8_t saved_priority; | |
147 | #define XICS_STATUS_ASSERTED 0x1 | |
148 | #define XICS_STATUS_SENT 0x2 | |
149 | #define XICS_STATUS_REJECTED 0x4 | |
150 | #define XICS_STATUS_MASKED_PENDING 0x8 | |
229e16fd SB |
151 | #define XICS_STATUS_PRESENTED 0x10 |
152 | #define XICS_STATUS_QUEUED 0x20 | |
c04d6cfa | 153 | uint8_t status; |
4af88944 AK |
154 | /* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */ |
155 | #define XICS_FLAGS_IRQ_LSI 0x1 | |
156 | #define XICS_FLAGS_IRQ_MSI 0x2 | |
157 | #define XICS_FLAGS_IRQ_MASK 0x3 | |
158 | uint8_t flags; | |
c04d6cfa | 159 | }; |
b5cec4c5 | 160 | |
eeb61d4f | 161 | struct XICSFabric { |
51b18005 | 162 | Object parent; |
eeb61d4f | 163 | }; |
51b18005 CLG |
164 | |
165 | #define TYPE_XICS_FABRIC "xics-fabric" | |
166 | #define XICS_FABRIC(obj) \ | |
167 | OBJECT_CHECK(XICSFabric, (obj), TYPE_XICS_FABRIC) | |
168 | #define XICS_FABRIC_CLASS(klass) \ | |
169 | OBJECT_CLASS_CHECK(XICSFabricClass, (klass), TYPE_XICS_FABRIC) | |
170 | #define XICS_FABRIC_GET_CLASS(obj) \ | |
171 | OBJECT_GET_CLASS(XICSFabricClass, (obj), TYPE_XICS_FABRIC) | |
172 | ||
173 | typedef struct XICSFabricClass { | |
174 | InterfaceClass parent; | |
175 | ICSState *(*ics_get)(XICSFabric *xi, int irq); | |
176 | void (*ics_resend)(XICSFabric *xi); | |
b2fc59aa | 177 | ICPState *(*icp_get)(XICSFabric *xi, int server); |
51b18005 CLG |
178 | } XICSFabricClass; |
179 | ||
161deaf2 | 180 | #define XICS_IRQS_SPAPR 1024 |
9dbae977 | 181 | |
681bfade CLG |
182 | int spapr_ics_alloc(ICSState *ics, int irq_hint, bool lsi, Error **errp); |
183 | int spapr_ics_alloc_block(ICSState *ics, int num, bool lsi, bool align, | |
cc706a53 | 184 | Error **errp); |
681bfade | 185 | void spapr_ics_free(ICSState *ics, int irq, int num); |
b0ec3129 | 186 | void spapr_dt_xics(int nr_servers, void *fdt, uint32_t phandle); |
b5cec4c5 | 187 | |
b4f27d71 CLG |
188 | qemu_irq xics_get_qirq(XICSFabric *xi, int irq); |
189 | ICPState *xics_icp_get(XICSFabric *xi, int server); | |
b5cec4c5 | 190 | |
9c7027ba | 191 | /* Internal XICS interfaces */ |
e3403258 CLG |
192 | void icp_set_cppr(ICPState *icp, uint8_t cppr); |
193 | void icp_set_mfrr(ICPState *icp, uint8_t mfrr); | |
9c7027ba | 194 | uint32_t icp_accept(ICPState *ss); |
1cbd2220 | 195 | uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr); |
e3403258 | 196 | void icp_eoi(ICPState *icp, uint32_t xirr); |
9c7027ba | 197 | |
d4d7a59a BH |
198 | void ics_simple_write_xive(ICSState *ics, int nr, int server, |
199 | uint8_t priority, uint8_t saved_priority); | |
9c7027ba BH |
200 | |
201 | void ics_set_irq_type(ICSState *ics, int srcno, bool lsi); | |
6449da45 CLG |
202 | void icp_pic_print_info(ICPState *icp, Monitor *mon); |
203 | void ics_pic_print_info(ICSState *ics, Monitor *mon); | |
9c7027ba | 204 | |
7844e12b | 205 | void ics_resend(ICSState *ics); |
b2fc59aa | 206 | void icp_resend(ICPState *ss); |
9c7027ba | 207 | |
2192a930 CLG |
208 | typedef struct sPAPRMachineState sPAPRMachineState; |
209 | ||
210 | int xics_kvm_init(sPAPRMachineState *spapr, Error **errp); | |
f63ebfe0 | 211 | void xics_spapr_init(sPAPRMachineState *spapr); |
2192a930 | 212 | |
2a6a4076 | 213 | #endif /* XICS_H */ |