[mirror_qemu.git] / include / hw / riscv / microchip_pfsoc.h

/*
 * Microchip PolarFire SoC machine interface
 *
 * Copyright (c) 2020 Wind River Systems, Inc.
 *
 * Author:
 *   Bin Meng <bin.meng@windriver.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef HW_MICROCHIP_PFSOC_H
#define HW_MICROCHIP_PFSOC_H

#include "hw/char/mchp_pfsoc_mmuart.h"
#include "hw/dma/sifive_pdma.h"
#include "hw/misc/mchp_pfsoc_dmc.h"
#include "hw/misc/mchp_pfsoc_ioscb.h"
#include "hw/misc/mchp_pfsoc_sysreg.h"
#include "hw/net/cadence_gem.h"
#include "hw/sd/cadence_sdhci.h"

typedef struct MicrochipPFSoCState {
    /*< private >*/
    DeviceState parent_obj;

    /*< public >*/
    CPUClusterState e_cluster;
    CPUClusterState u_cluster;
    RISCVHartArrayState e_cpus;
    RISCVHartArrayState u_cpus;
    DeviceState *plic;
    MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy;
    MchpPfSoCDdrCfgState ddr_cfg;
    MchpPfSoCIoscbState ioscb;
    MchpPfSoCMMUartState *serial0;
    MchpPfSoCMMUartState *serial1;
    MchpPfSoCMMUartState *serial2;
    MchpPfSoCMMUartState *serial3;
    MchpPfSoCMMUartState *serial4;
    MchpPfSoCSysregState sysreg;
    SiFivePDMAState dma;
    CadenceGEMState gem0;
    CadenceGEMState gem1;
    CadenceSDHCIState sdhci;
} MicrochipPFSoCState;

#define TYPE_MICROCHIP_PFSOC    "microchip.pfsoc"
#define MICROCHIP_PFSOC(obj) \
    OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC)

typedef struct MicrochipIcicleKitState {
    /*< private >*/
    MachineState parent_obj;

    /*< public >*/
    MicrochipPFSoCState soc;
} MicrochipIcicleKitState;

#define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \
    MACHINE_TYPE_NAME("microchip-icicle-kit")
#define MICROCHIP_ICICLE_KIT_MACHINE(obj) \
    OBJECT_CHECK(MicrochipIcicleKitState, (obj), \
                 TYPE_MICROCHIP_ICICLE_KIT_MACHINE)

enum {
    MICROCHIP_PFSOC_RSVD0,
    MICROCHIP_PFSOC_DEBUG,
    MICROCHIP_PFSOC_E51_DTIM,
    MICROCHIP_PFSOC_BUSERR_UNIT0,
    MICROCHIP_PFSOC_BUSERR_UNIT1,
    MICROCHIP_PFSOC_BUSERR_UNIT2,
    MICROCHIP_PFSOC_BUSERR_UNIT3,
    MICROCHIP_PFSOC_BUSERR_UNIT4,
    MICROCHIP_PFSOC_CLINT,
    MICROCHIP_PFSOC_L2CC,
    MICROCHIP_PFSOC_DMA,
    MICROCHIP_PFSOC_L2LIM,
    MICROCHIP_PFSOC_PLIC,
    MICROCHIP_PFSOC_MMUART0,
    MICROCHIP_PFSOC_SYSREG,
    MICROCHIP_PFSOC_MPUCFG,
    MICROCHIP_PFSOC_DDR_SGMII_PHY,
    MICROCHIP_PFSOC_EMMC_SD,
    MICROCHIP_PFSOC_DDR_CFG,
    MICROCHIP_PFSOC_MMUART1,
    MICROCHIP_PFSOC_MMUART2,
    MICROCHIP_PFSOC_MMUART3,
    MICROCHIP_PFSOC_MMUART4,
    MICROCHIP_PFSOC_SPI0,
    MICROCHIP_PFSOC_SPI1,
    MICROCHIP_PFSOC_I2C1,
    MICROCHIP_PFSOC_GEM0,
    MICROCHIP_PFSOC_GEM1,
    MICROCHIP_PFSOC_GPIO0,
    MICROCHIP_PFSOC_GPIO1,
    MICROCHIP_PFSOC_GPIO2,
    MICROCHIP_PFSOC_ENVM_CFG,
    MICROCHIP_PFSOC_ENVM_DATA,
    MICROCHIP_PFSOC_QSPI_XIP,
    MICROCHIP_PFSOC_IOSCB,
    MICROCHIP_PFSOC_EMMC_SD_MUX,
    MICROCHIP_PFSOC_DRAM_LO,
    MICROCHIP_PFSOC_DRAM_LO_ALIAS,
    MICROCHIP_PFSOC_DRAM_HI,
    MICROCHIP_PFSOC_DRAM_HI_ALIAS
};

enum {
    MICROCHIP_PFSOC_DMA_IRQ0 = 5,
    MICROCHIP_PFSOC_DMA_IRQ1 = 6,
    MICROCHIP_PFSOC_DMA_IRQ2 = 7,
    MICROCHIP_PFSOC_DMA_IRQ3 = 8,
    MICROCHIP_PFSOC_DMA_IRQ4 = 9,
    MICROCHIP_PFSOC_DMA_IRQ5 = 10,
    MICROCHIP_PFSOC_DMA_IRQ6 = 11,
    MICROCHIP_PFSOC_DMA_IRQ7 = 12,
    MICROCHIP_PFSOC_GEM0_IRQ = 64,
    MICROCHIP_PFSOC_GEM1_IRQ = 70,
    MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
    MICROCHIP_PFSOC_MMUART0_IRQ = 90,
    MICROCHIP_PFSOC_MMUART1_IRQ = 91,
    MICROCHIP_PFSOC_MMUART2_IRQ = 92,
    MICROCHIP_PFSOC_MMUART3_IRQ = 93,
    MICROCHIP_PFSOC_MMUART4_IRQ = 94,
};

#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT    1
#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT       4

#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES        185
#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES     7
#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE      0x04
#define MICROCHIP_PFSOC_PLIC_PENDING_BASE       0x1000
#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE        0x2000
#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE      0x80
#define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE       0x200000
#define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE     0x1000

#endif /* HW_MICROCHIP_PFSOC_H */
Commit	Line	Data
56f6e31e BM	1	/*
	2	* Microchip PolarFire SoC machine interface
	3	*
	4	* Copyright (c) 2020 Wind River Systems, Inc.
	5	*
	6	* Author:
	7	* Bin Meng <bin.meng@windriver.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms and conditions of the GNU General Public License,
	11	* version 2 or later, as published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope it will be useful, but WITHOUT
	14	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	15	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	16	* more details.
	17	*
	18	* You should have received a copy of the GNU General Public License along with
	19	* this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#ifndef HW_MICROCHIP_PFSOC_H
	23	#define HW_MICROCHIP_PFSOC_H
	24
8f2ac39d	25	#include "hw/char/mchp_pfsoc_mmuart.h"
7124e27b	26	#include "hw/dma/sifive_pdma.h"
933f73f1	27	#include "hw/misc/mchp_pfsoc_dmc.h"
e35d6179	28	#include "hw/misc/mchp_pfsoc_ioscb.h"
cdd58c70	29	#include "hw/misc/mchp_pfsoc_sysreg.h"
47374b07	30	#include "hw/net/cadence_gem.h"
898dc008	31	#include "hw/sd/cadence_sdhci.h"
8f2ac39d	32
56f6e31e BM	33	typedef struct MicrochipPFSoCState {
	34	/< private >/
	35	DeviceState parent_obj;
	36
	37	/< public >/
	38	CPUClusterState e_cluster;
	39	CPUClusterState u_cluster;
	40	RISCVHartArrayState e_cpus;
	41	RISCVHartArrayState u_cpus;
	42	DeviceState *plic;
933f73f1 BM	43	MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy;
933f73f1 BM	44	MchpPfSoCDdrCfgState ddr_cfg;
e35d6179	45	MchpPfSoCIoscbState ioscb;
8f2ac39d BM	46	MchpPfSoCMMUartState *serial0;
	47	MchpPfSoCMMUartState *serial1;
	48	MchpPfSoCMMUartState *serial2;
	49	MchpPfSoCMMUartState *serial3;
	50	MchpPfSoCMMUartState *serial4;
cdd58c70	51	MchpPfSoCSysregState sysreg;
7124e27b	52	SiFivePDMAState dma;
47374b07 BM	53	CadenceGEMState gem0;
47374b07 BM	54	CadenceGEMState gem1;
898dc008	55	CadenceSDHCIState sdhci;
56f6e31e BM	56	} MicrochipPFSoCState;
	57
	58	#define TYPE_MICROCHIP_PFSOC "microchip.pfsoc"
	59	#define MICROCHIP_PFSOC(obj) \
	60	OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC)
	61
	62	typedef struct MicrochipIcicleKitState {
	63	/< private >/
	64	MachineState parent_obj;
	65
	66	/< public >/
	67	MicrochipPFSoCState soc;
	68	} MicrochipIcicleKitState;
	69
	70	#define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \
	71	MACHINE_TYPE_NAME("microchip-icicle-kit")
	72	#define MICROCHIP_ICICLE_KIT_MACHINE(obj) \
	73	OBJECT_CHECK(MicrochipIcicleKitState, (obj), \
	74	TYPE_MICROCHIP_ICICLE_KIT_MACHINE)
	75
	76	enum {
27c22b2d	77	MICROCHIP_PFSOC_RSVD0,
56f6e31e BM	78	MICROCHIP_PFSOC_DEBUG,
	79	MICROCHIP_PFSOC_E51_DTIM,
	80	MICROCHIP_PFSOC_BUSERR_UNIT0,
	81	MICROCHIP_PFSOC_BUSERR_UNIT1,
	82	MICROCHIP_PFSOC_BUSERR_UNIT2,
	83	MICROCHIP_PFSOC_BUSERR_UNIT3,
	84	MICROCHIP_PFSOC_BUSERR_UNIT4,
	85	MICROCHIP_PFSOC_CLINT,
	86	MICROCHIP_PFSOC_L2CC,
7124e27b	87	MICROCHIP_PFSOC_DMA,
56f6e31e BM	88	MICROCHIP_PFSOC_L2LIM,
56f6e31e BM	89	MICROCHIP_PFSOC_PLIC,
8f2ac39d	90	MICROCHIP_PFSOC_MMUART0,
56f6e31e BM	91	MICROCHIP_PFSOC_SYSREG,
56f6e31e BM	92	MICROCHIP_PFSOC_MPUCFG,
933f73f1	93	MICROCHIP_PFSOC_DDR_SGMII_PHY,
898dc008	94	MICROCHIP_PFSOC_EMMC_SD,
933f73f1	95	MICROCHIP_PFSOC_DDR_CFG,
8f2ac39d BM	96	MICROCHIP_PFSOC_MMUART1,
	97	MICROCHIP_PFSOC_MMUART2,
	98	MICROCHIP_PFSOC_MMUART3,
	99	MICROCHIP_PFSOC_MMUART4,
dfc973ec VW	100	MICROCHIP_PFSOC_SPI0,
dfc973ec VW	101	MICROCHIP_PFSOC_SPI1,
90742c54	102	MICROCHIP_PFSOC_I2C1,
47374b07 BM	103	MICROCHIP_PFSOC_GEM0,
47374b07 BM	104	MICROCHIP_PFSOC_GEM1,
ce908a2f BM	105	MICROCHIP_PFSOC_GPIO0,
	106	MICROCHIP_PFSOC_GPIO1,
	107	MICROCHIP_PFSOC_GPIO2,
56f6e31e BM	108	MICROCHIP_PFSOC_ENVM_CFG,
56f6e31e BM	109	MICROCHIP_PFSOC_ENVM_DATA,
dfc973ec	110	MICROCHIP_PFSOC_QSPI_XIP,
e35d6179	111	MICROCHIP_PFSOC_IOSCB,
d6150ace	112	MICROCHIP_PFSOC_EMMC_SD_MUX,
f03100d7 BM	113	MICROCHIP_PFSOC_DRAM_LO,
	114	MICROCHIP_PFSOC_DRAM_LO_ALIAS,
	115	MICROCHIP_PFSOC_DRAM_HI,
	116	MICROCHIP_PFSOC_DRAM_HI_ALIAS
56f6e31e BM	117	};
56f6e31e BM	118
8f2ac39d	119	enum {
7124e27b BM	120	MICROCHIP_PFSOC_DMA_IRQ0 = 5,
	121	MICROCHIP_PFSOC_DMA_IRQ1 = 6,
	122	MICROCHIP_PFSOC_DMA_IRQ2 = 7,
	123	MICROCHIP_PFSOC_DMA_IRQ3 = 8,
	124	MICROCHIP_PFSOC_DMA_IRQ4 = 9,
	125	MICROCHIP_PFSOC_DMA_IRQ5 = 10,
	126	MICROCHIP_PFSOC_DMA_IRQ6 = 11,
	127	MICROCHIP_PFSOC_DMA_IRQ7 = 12,
47374b07 BM	128	MICROCHIP_PFSOC_GEM0_IRQ = 64,
47374b07 BM	129	MICROCHIP_PFSOC_GEM1_IRQ = 70,
898dc008	130	MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
8f2ac39d BM	131	MICROCHIP_PFSOC_MMUART0_IRQ = 90,
	132	MICROCHIP_PFSOC_MMUART1_IRQ = 91,
	133	MICROCHIP_PFSOC_MMUART2_IRQ = 92,
	134	MICROCHIP_PFSOC_MMUART3_IRQ = 93,
	135	MICROCHIP_PFSOC_MMUART4_IRQ = 94,
	136	};
	137
56f6e31e BM	138	#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
	139	#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
	140
56f6e31e BM	141	#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185
	142	#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
	143	#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04
	144	#define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000
	145	#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000
	146	#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80
	147	#define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE 0x200000
	148	#define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE 0x1000
	149
	150	#endif /* HW_MICROCHIP_PFSOC_H */