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a7240d1e MC |
1 | /* |
2 | * SiFive U series machine interface | |
3 | * | |
4 | * Copyright (c) 2017 SiFive, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #ifndef HW_SIFIVE_U_H | |
20 | #define HW_SIFIVE_U_H | |
21 | ||
5a7f76a3 | 22 | #include "hw/net/cadence_gem.h" |
ec150c7e | 23 | #include "hw/riscv/riscv_hart.h" |
5a7f76a3 | 24 | |
2308092b AF |
25 | #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" |
26 | #define RISCV_U_SOC(obj) \ | |
27 | OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC) | |
28 | ||
29 | typedef struct SiFiveUSoCState { | |
a7240d1e MC |
30 | /*< private >*/ |
31 | SysBusDevice parent_obj; | |
32 | ||
33 | /*< public >*/ | |
2308092b | 34 | RISCVHartArrayState cpus; |
a7240d1e | 35 | DeviceState *plic; |
5a7f76a3 | 36 | CadenceGEMState gem; |
2308092b AF |
37 | } SiFiveUSoCState; |
38 | ||
39 | typedef struct SiFiveUState { | |
40 | /*< private >*/ | |
41 | SysBusDevice parent_obj; | |
42 | ||
43 | /*< public >*/ | |
44 | SiFiveUSoCState soc; | |
a7240d1e MC |
45 | void *fdt; |
46 | int fdt_size; | |
47 | } SiFiveUState; | |
48 | ||
49 | enum { | |
50 | SIFIVE_U_DEBUG, | |
51 | SIFIVE_U_MROM, | |
52 | SIFIVE_U_CLINT, | |
53 | SIFIVE_U_PLIC, | |
54 | SIFIVE_U_UART0, | |
55 | SIFIVE_U_UART1, | |
5a7f76a3 AF |
56 | SIFIVE_U_DRAM, |
57 | SIFIVE_U_GEM | |
a7240d1e MC |
58 | }; |
59 | ||
60 | enum { | |
61 | SIFIVE_U_UART0_IRQ = 3, | |
5a7f76a3 AF |
62 | SIFIVE_U_UART1_IRQ = 4, |
63 | SIFIVE_U_GEM_IRQ = 0x35 | |
a7240d1e MC |
64 | }; |
65 | ||
2a8756ed | 66 | enum { |
fe93582c AP |
67 | SIFIVE_U_CLOCK_FREQ = 1000000000, |
68 | SIFIVE_U_GEM_CLOCK_FREQ = 125000000 | |
2a8756ed MC |
69 | }; |
70 | ||
a7240d1e | 71 | #define SIFIVE_U_PLIC_HART_CONFIG "MS" |
0feb4a71 | 72 | #define SIFIVE_U_PLIC_NUM_SOURCES 54 |
a7240d1e | 73 | #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 |
0feb4a71 | 74 | #define SIFIVE_U_PLIC_PRIORITY_BASE 0x04 |
a7240d1e MC |
75 | #define SIFIVE_U_PLIC_PENDING_BASE 0x1000 |
76 | #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000 | |
77 | #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80 | |
78 | #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000 | |
79 | #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000 | |
80 | ||
81 | #if defined(TARGET_RISCV32) | |
82 | #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 | |
83 | #elif defined(TARGET_RISCV64) | |
84 | #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 | |
85 | #endif | |
86 | ||
87 | #endif |