]>
Commit | Line | Data |
---|---|---|
a7240d1e MC |
1 | /* |
2 | * SiFive U series machine interface | |
3 | * | |
4 | * Copyright (c) 2017 SiFive, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #ifndef HW_SIFIVE_U_H | |
20 | #define HW_SIFIVE_U_H | |
21 | ||
5a7f76a3 | 22 | #include "hw/net/cadence_gem.h" |
ec150c7e | 23 | #include "hw/riscv/riscv_hart.h" |
20f41c86 | 24 | #include "hw/riscv/sifive_cpu.h" |
af14c840 | 25 | #include "hw/riscv/sifive_u_prci.h" |
5a7f76a3 | 26 | |
2308092b AF |
27 | #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" |
28 | #define RISCV_U_SOC(obj) \ | |
29 | OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC) | |
30 | ||
31 | typedef struct SiFiveUSoCState { | |
a7240d1e MC |
32 | /*< private >*/ |
33 | SysBusDevice parent_obj; | |
34 | ||
35 | /*< public >*/ | |
ecdfe393 BM |
36 | CPUClusterState e_cluster; |
37 | CPUClusterState u_cluster; | |
38 | RISCVHartArrayState e_cpus; | |
39 | RISCVHartArrayState u_cpus; | |
a7240d1e | 40 | DeviceState *plic; |
af14c840 | 41 | SiFiveUPRCIState prci; |
5a7f76a3 | 42 | CadenceGEMState gem; |
2308092b AF |
43 | } SiFiveUSoCState; |
44 | ||
45 | typedef struct SiFiveUState { | |
46 | /*< private >*/ | |
47 | SysBusDevice parent_obj; | |
48 | ||
49 | /*< public >*/ | |
50 | SiFiveUSoCState soc; | |
a7240d1e MC |
51 | void *fdt; |
52 | int fdt_size; | |
53 | } SiFiveUState; | |
54 | ||
55 | enum { | |
56 | SIFIVE_U_DEBUG, | |
57 | SIFIVE_U_MROM, | |
58 | SIFIVE_U_CLINT, | |
59 | SIFIVE_U_PLIC, | |
af14c840 | 60 | SIFIVE_U_PRCI, |
a7240d1e MC |
61 | SIFIVE_U_UART0, |
62 | SIFIVE_U_UART1, | |
5a7f76a3 AF |
63 | SIFIVE_U_DRAM, |
64 | SIFIVE_U_GEM | |
a7240d1e MC |
65 | }; |
66 | ||
67 | enum { | |
68 | SIFIVE_U_UART0_IRQ = 3, | |
5a7f76a3 AF |
69 | SIFIVE_U_UART1_IRQ = 4, |
70 | SIFIVE_U_GEM_IRQ = 0x35 | |
a7240d1e MC |
71 | }; |
72 | ||
2a8756ed | 73 | enum { |
fe93582c | 74 | SIFIVE_U_CLOCK_FREQ = 1000000000, |
e1724d09 BM |
75 | SIFIVE_U_HFCLK_FREQ = 33333333, |
76 | SIFIVE_U_RTCCLK_FREQ = 1000000, | |
fe93582c | 77 | SIFIVE_U_GEM_CLOCK_FREQ = 125000000 |
2a8756ed MC |
78 | }; |
79 | ||
f3d47d58 | 80 | #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 |
ecdfe393 | 81 | #define SIFIVE_U_COMPUTE_CPU_COUNT 4 |
f3d47d58 | 82 | |
a7240d1e | 83 | #define SIFIVE_U_PLIC_HART_CONFIG "MS" |
0feb4a71 | 84 | #define SIFIVE_U_PLIC_NUM_SOURCES 54 |
a7240d1e | 85 | #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 |
0feb4a71 | 86 | #define SIFIVE_U_PLIC_PRIORITY_BASE 0x04 |
a7240d1e MC |
87 | #define SIFIVE_U_PLIC_PENDING_BASE 0x1000 |
88 | #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000 | |
89 | #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80 | |
90 | #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000 | |
91 | #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000 | |
92 | ||
a7240d1e | 93 | #endif |