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04331d0b MC |
1 | /* |
2 | * SiFive VirtIO Board | |
3 | * | |
4 | * Copyright (c) 2017 SiFive, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #ifndef HW_VIRT_H | |
20 | #define HW_VIRT_H | |
21 | ||
22 | #define TYPE_RISCV_VIRT_BOARD "riscv.virt" | |
23 | #define VIRT(obj) \ | |
24 | OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD) | |
25 | ||
26 | enum { ROM_BASE = 0x1000 }; | |
27 | ||
28 | typedef struct { | |
29 | /*< private >*/ | |
30 | SysBusDevice parent_obj; | |
31 | ||
32 | /*< public >*/ | |
33 | RISCVHartArrayState soc; | |
34 | DeviceState *plic; | |
35 | void *fdt; | |
36 | int fdt_size; | |
37 | } RISCVVirtState; | |
38 | ||
39 | enum { | |
40 | VIRT_DEBUG, | |
41 | VIRT_MROM, | |
42 | VIRT_TEST, | |
43 | VIRT_CLINT, | |
44 | VIRT_PLIC, | |
45 | VIRT_UART0, | |
46 | VIRT_VIRTIO, | |
47 | VIRT_DRAM | |
48 | }; | |
49 | ||
50 | ||
51 | enum { | |
52 | UART0_IRQ = 10, | |
53 | VIRTIO_IRQ = 1, /* 1 to 8 */ | |
54 | VIRTIO_COUNT = 8, | |
55 | VIRTIO_NDEV = 10 | |
56 | }; | |
57 | ||
2a8756ed MC |
58 | enum { |
59 | VIRT_CLOCK_FREQ = 1000000000 | |
60 | }; | |
61 | ||
04331d0b MC |
62 | #define VIRT_PLIC_HART_CONFIG "MS" |
63 | #define VIRT_PLIC_NUM_SOURCES 127 | |
64 | #define VIRT_PLIC_NUM_PRIORITIES 7 | |
65 | #define VIRT_PLIC_PRIORITY_BASE 0x0 | |
66 | #define VIRT_PLIC_PENDING_BASE 0x1000 | |
67 | #define VIRT_PLIC_ENABLE_BASE 0x2000 | |
68 | #define VIRT_PLIC_ENABLE_STRIDE 0x80 | |
69 | #define VIRT_PLIC_CONTEXT_BASE 0x200000 | |
70 | #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 | |
71 | ||
72 | #if defined(TARGET_RISCV32) | |
73 | #define VIRT_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0 | |
74 | #elif defined(TARGET_RISCV64) | |
75 | #define VIRT_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0 | |
76 | #endif | |
77 | ||
78 | #endif |