]>
Commit | Line | Data |
---|---|---|
04331d0b | 1 | /* |
5b558380 | 2 | * QEMU RISC-V VirtIO machine interface |
04331d0b MC |
3 | * |
4 | * Copyright (c) 2017 SiFive, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
4996b128 MC |
19 | #ifndef HW_RISCV_VIRT_H |
20 | #define HW_RISCV_VIRT_H | |
04331d0b | 21 | |
ec150c7e MA |
22 | #include "hw/riscv/riscv_hart.h" |
23 | #include "hw/sysbus.h" | |
71eb522c | 24 | #include "hw/block/flash.h" |
ec150c7e | 25 | |
cdfc19e4 AF |
26 | #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") |
27 | #define RISCV_VIRT_MACHINE(obj) \ | |
28 | OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_MACHINE) | |
29 | ||
04331d0b MC |
30 | typedef struct { |
31 | /*< private >*/ | |
cdfc19e4 | 32 | MachineState parent; |
04331d0b MC |
33 | |
34 | /*< public >*/ | |
35 | RISCVHartArrayState soc; | |
36 | DeviceState *plic; | |
71eb522c | 37 | PFlashCFI01 *flash[2]; |
cdfc19e4 | 38 | |
04331d0b MC |
39 | void *fdt; |
40 | int fdt_size; | |
41 | } RISCVVirtState; | |
42 | ||
43 | enum { | |
44 | VIRT_DEBUG, | |
45 | VIRT_MROM, | |
46 | VIRT_TEST, | |
47 | VIRT_CLINT, | |
48 | VIRT_PLIC, | |
49 | VIRT_UART0, | |
50 | VIRT_VIRTIO, | |
71eb522c | 51 | VIRT_FLASH, |
6d56e396 AF |
52 | VIRT_DRAM, |
53 | VIRT_PCIE_MMIO, | |
54 | VIRT_PCIE_PIO, | |
55 | VIRT_PCIE_ECAM | |
04331d0b MC |
56 | }; |
57 | ||
04331d0b MC |
58 | enum { |
59 | UART0_IRQ = 10, | |
60 | VIRTIO_IRQ = 1, /* 1 to 8 */ | |
61 | VIRTIO_COUNT = 8, | |
6d56e396 | 62 | PCIE_IRQ = 0x20, /* 32 to 35 */ |
63b695f2 | 63 | VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */ |
04331d0b MC |
64 | }; |
65 | ||
66 | #define VIRT_PLIC_HART_CONFIG "MS" | |
67 | #define VIRT_PLIC_NUM_SOURCES 127 | |
68 | #define VIRT_PLIC_NUM_PRIORITIES 7 | |
0feb4a71 | 69 | #define VIRT_PLIC_PRIORITY_BASE 0x04 |
04331d0b MC |
70 | #define VIRT_PLIC_PENDING_BASE 0x1000 |
71 | #define VIRT_PLIC_ENABLE_BASE 0x2000 | |
72 | #define VIRT_PLIC_ENABLE_STRIDE 0x80 | |
73 | #define VIRT_PLIC_CONTEXT_BASE 0x200000 | |
74 | #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 | |
75 | ||
6d56e396 AF |
76 | #define FDT_PCI_ADDR_CELLS 3 |
77 | #define FDT_PCI_INT_CELLS 1 | |
78 | #define FDT_PLIC_ADDR_CELLS 0 | |
79 | #define FDT_PLIC_INT_CELLS 1 | |
80 | #define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \ | |
81 | FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS) | |
82 | ||
04331d0b | 83 | #if defined(TARGET_RISCV32) |
8903bf6e | 84 | #define VIRT_CPU TYPE_RISCV_CPU_BASE32 |
04331d0b | 85 | #elif defined(TARGET_RISCV64) |
8903bf6e | 86 | #define VIRT_CPU TYPE_RISCV_CPU_BASE64 |
04331d0b MC |
87 | #endif |
88 | ||
89 | #endif |