]>
Commit | Line | Data |
---|---|---|
637d23be SPB |
1 | /* |
2 | * SD Association Host Standard Specification v2.0 controller emulation | |
3 | * | |
4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
5 | * Mitsyanko Igor <i.mitsyanko@samsung.com> | |
6 | * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> | |
7 | * | |
8 | * Based on MMC controller for Samsung S5PC1xx-based board emulation | |
9 | * by Alexey Merkulov and Vladimir Monakhov. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | |
19 | * See the GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU _General Public License along | |
22 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
23 | */ | |
24 | ||
25 | #ifndef SDHCI_H | |
26 | #define SDHCI_H | |
27 | ||
28 | #include "qemu-common.h" | |
29 | #include "hw/block/block.h" | |
30 | #include "hw/pci/pci.h" | |
31 | #include "hw/sysbus.h" | |
32 | #include "hw/sd/sd.h" | |
33 | ||
34 | /* SD/MMC host controller state */ | |
35 | typedef struct SDHCIState { | |
36 | union { | |
37 | PCIDevice pcidev; | |
38 | SysBusDevice busdev; | |
39 | }; | |
40 | SDState *card; | |
41 | MemoryRegion iomem; | |
79f21707 | 42 | BlockBackend *blk; |
637d23be SPB |
43 | |
44 | QEMUTimer *insert_timer; /* timer for 'changing' sd card. */ | |
45 | QEMUTimer *transfer_timer; | |
46 | qemu_irq eject_cb; | |
47 | qemu_irq ro_cb; | |
48 | qemu_irq irq; | |
49 | ||
50 | uint32_t sdmasysad; /* SDMA System Address register */ | |
51 | uint16_t blksize; /* Host DMA Buff Boundary and Transfer BlkSize Reg */ | |
52 | uint16_t blkcnt; /* Blocks count for current transfer */ | |
53 | uint32_t argument; /* Command Argument Register */ | |
54 | uint16_t trnmod; /* Transfer Mode Setting Register */ | |
55 | uint16_t cmdreg; /* Command Register */ | |
56 | uint32_t rspreg[4]; /* Response Registers 0-3 */ | |
57 | uint32_t prnsts; /* Present State Register */ | |
58 | uint8_t hostctl; /* Host Control Register */ | |
59 | uint8_t pwrcon; /* Power control Register */ | |
60 | uint8_t blkgap; /* Block Gap Control Register */ | |
61 | uint8_t wakcon; /* WakeUp Control Register */ | |
62 | uint16_t clkcon; /* Clock control Register */ | |
63 | uint8_t timeoutcon; /* Timeout Control Register */ | |
64 | uint8_t admaerr; /* ADMA Error Status Register */ | |
65 | uint16_t norintsts; /* Normal Interrupt Status Register */ | |
66 | uint16_t errintsts; /* Error Interrupt Status Register */ | |
67 | uint16_t norintstsen; /* Normal Interrupt Status Enable Register */ | |
68 | uint16_t errintstsen; /* Error Interrupt Status Enable Register */ | |
69 | uint16_t norintsigen; /* Normal Interrupt Signal Enable Register */ | |
70 | uint16_t errintsigen; /* Error Interrupt Signal Enable Register */ | |
71 | uint16_t acmd12errsts; /* Auto CMD12 error status register */ | |
72 | uint64_t admasysaddr; /* ADMA System Address Register */ | |
73 | ||
74 | uint32_t capareg; /* Capabilities Register */ | |
75 | uint32_t maxcurr; /* Maximum Current Capabilities Register */ | |
76 | uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */ | |
77 | uint32_t buf_maxsz; | |
78 | uint16_t data_count; /* current element in FIFO buffer */ | |
79 | uint8_t stopped_state;/* Current SDHC state */ | |
72369755 | 80 | bool noeject_quirk;/* Quirk to disable card insert/remove interrupts */ |
637d23be SPB |
81 | /* Buffer Data Port Register - virtual access point to R and W buffers */ |
82 | /* Software Reset Register - always reads as 0 */ | |
83 | /* Force Event Auto CMD12 Error Interrupt Reg - write only */ | |
84 | /* Force Event Error Interrupt Register- write only */ | |
85 | /* RO Host Controller Version Register always reads as 0x2401 */ | |
86 | } SDHCIState; | |
87 | ||
88 | #define TYPE_PCI_SDHCI "sdhci-pci" | |
89 | #define PCI_SDHCI(obj) OBJECT_CHECK(SDHCIState, (obj), TYPE_PCI_SDHCI) | |
90 | ||
91 | #define TYPE_SYSBUS_SDHCI "generic-sdhci" | |
92 | #define SYSBUS_SDHCI(obj) \ | |
93 | OBJECT_CHECK(SDHCIState, (obj), TYPE_SYSBUS_SDHCI) | |
94 | ||
95 | #endif /* SDHCI_H */ |