[mirror_qemu.git] / include / hw / southbridge / piix.h

/*
 * QEMU PIIX South Bridge Emulation
 *
 * Copyright (c) 2006 Fabrice Bellard
 * Copyright (c) 2018 Hervé Poussineau
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 *
 */

#ifndef HW_SOUTHBRIDGE_PIIX_H
#define HW_SOUTHBRIDGE_PIIX_H

#define TYPE_PIIX4_PM "PIIX4_PM"

I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                      qemu_irq sci_irq, qemu_irq smi_irq,
                      int smm_enabled, DeviceState **piix4_pm);

/*
 * Reset Control Register: PCI-accessible ISA-Compatible Register at address
 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
 */
#define PIIX_RCR_IOPORT 0xcf9

extern PCIDevice *piix4_dev;

DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
                          I2CBus **smbus, size_t ide_buses);

#endif
Commit	Line	Data
fff123b8 PMD	1	/*
	2	* QEMU PIIX South Bridge Emulation
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
e29f2379	5	* Copyright (c) 2018 Hervé Poussineau
fff123b8 PMD	6	*
	7	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	8	* See the COPYING file in the top-level directory.
	9	*
	10	*/
	11
	12	#ifndef HW_SOUTHBRIDGE_PIIX_H
	13	#define HW_SOUTHBRIDGE_PIIX_H
	14
	15	#define TYPE_PIIX4_PM "PIIX4_PM"
	16
	17	I2CBus piix4_pm_init(PCIBus bus, int devfn, uint32_t smb_io_base,
	18	qemu_irq sci_irq, qemu_irq smi_irq,
	19	int smm_enabled, DeviceState **piix4_pm);
	20
0063454a PMD	21	/*
	22	* Reset Control Register: PCI-accessible ISA-Compatible Register at address
	23	* 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
	24	*/
	25	#define PIIX_RCR_IOPORT 0xcf9
	26
e29f2379 PMD	27	extern PCIDevice *piix4_dev;
	28
	29	DeviceState piix4_create(PCIBus pci_bus, ISABus **isa_bus,
	30	I2CBus **smbus, size_t ide_buses);
	31
fff123b8	32	#endif