projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| c906a3a0 JCD |
1 | /* |
| 2 | * IMX SPI Controller | |
| 3 | * | |
| 4 | * Copyright 2016 Jean-Christophe Dubois <jcd@tribudubois.net> | |
| 5 | * | |
| 6 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
| 7 | * See the COPYING file in the top-level directory. | |
| 8 | */ | |
| 9 | ||
| 10 | #ifndef IMX_SPI_H | |
| 11 | #define IMX_SPI_H | |
| 12 | ||
| 13 | #include "hw/sysbus.h" | |
| 14 | #include "hw/ssi/ssi.h" | |
| 15 | #include "qemu/bitops.h" | |
| 16 | #include "qemu/fifo32.h" | |
| 17 | ||
| 18 | #define ECSPI_FIFO_SIZE 64 | |
| 19 | ||
| 20 | #define ECSPI_RXDATA 0 | |
| 21 | #define ECSPI_TXDATA 1 | |
| 22 | #define ECSPI_CONREG 2 | |
| 23 | #define ECSPI_CONFIGREG 3 | |
| 24 | #define ECSPI_INTREG 4 | |
| 25 | #define ECSPI_DMAREG 5 | |
| 26 | #define ECSPI_STATREG 6 | |
| 27 | #define ECSPI_PERIODREG 7 | |
| 28 | #define ECSPI_TESTREG 8 | |
| 29 | #define ECSPI_MSGDATA 16 | |
| 30 | #define ECSPI_MAX 17 | |
| 31 | ||
| 32 | /* ECSPI_CONREG */ | |
| 33 | #define ECSPI_CONREG_EN (1 << 0) | |
| 34 | #define ECSPI_CONREG_HT (1 << 1) | |
| 35 | #define ECSPI_CONREG_XCH (1 << 2) | |
| 36 | #define ECSPI_CONREG_SMC (1 << 3) | |
| 37 | #define ECSPI_CONREG_CHANNEL_MODE_SHIFT 4 | |
| 38 | #define ECSPI_CONREG_CHANNEL_MODE_LENGTH 4 | |
| 39 | #define ECSPI_CONREG_DRCTL_SHIFT 16 | |
| 40 | #define ECSPI_CONREG_DRCTL_LENGTH 2 | |
| 41 | #define ECSPI_CONREG_CHANNEL_SELECT_SHIFT 18 | |
| 42 | #define ECSPI_CONREG_CHANNEL_SELECT_LENGTH 2 | |
| 43 | #define ECSPI_CONREG_BURST_LENGTH_SHIFT 20 | |
| 44 | #define ECSPI_CONREG_BURST_LENGTH_LENGTH 12 | |
| 45 | ||
| 46 | /* ECSPI_CONFIGREG */ | |
| 47 | #define ECSPI_CONFIGREG_SS_CTL_SHIFT 8 | |
| 48 | #define ECSPI_CONFIGREG_SS_CTL_LENGTH 4 | |
| 49 | ||
| 50 | /* ECSPI_INTREG */ | |
| 51 | #define ECSPI_INTREG_TEEN (1 << 0) | |
| 52 | #define ECSPI_INTREG_TDREN (1 << 1) | |
| 53 | #define ECSPI_INTREG_TFEN (1 << 2) | |
| 54 | #define ECSPI_INTREG_RREN (1 << 3) | |
| 55 | #define ECSPI_INTREG_RDREN (1 << 4) | |
| 56 | #define ECSPI_INTREG_RFEN (1 << 5) | |
| 57 | #define ECSPI_INTREG_ROEN (1 << 6) | |
| 58 | #define ECSPI_INTREG_TCEN (1 << 7) | |
| 59 | ||
| 60 | /* ECSPI_DMAREG */ | |
| 61 | #define ECSPI_DMAREG_RXTDEN (1 << 31) | |
| 62 | #define ECSPI_DMAREG_RXDEN (1 << 23) | |
| 63 | #define ECSPI_DMAREG_TEDEN (1 << 7) | |
| 64 | #define ECSPI_DMAREG_RX_THRESHOLD_SHIFT 16 | |
| 65 | #define ECSPI_DMAREG_RX_THRESHOLD_LENGTH 6 | |
| 66 | ||
| 67 | /* ECSPI_STATREG */ | |
| 68 | #define ECSPI_STATREG_TE (1 << 0) | |
| 69 | #define ECSPI_STATREG_TDR (1 << 1) | |
| 70 | #define ECSPI_STATREG_TF (1 << 2) | |
| 71 | #define ECSPI_STATREG_RR (1 << 3) | |
| 72 | #define ECSPI_STATREG_RDR (1 << 4) | |
| 73 | #define ECSPI_STATREG_RF (1 << 5) | |
| 74 | #define ECSPI_STATREG_RO (1 << 6) | |
| 75 | #define ECSPI_STATREG_TC (1 << 7) | |
| 76 | ||
| 77 | #define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH) | |
| 78 | ||
| 79 | #define TYPE_IMX_SPI "imx.spi" | |
| 80 | #define IMX_SPI(obj) OBJECT_CHECK(IMXSPIState, (obj), TYPE_IMX_SPI) | |
| 81 | ||
| 82 | typedef struct IMXSPIState { | |
| 83 | /* <private> */ | |
| 84 | SysBusDevice parent_obj; | |
| 85 | ||
| 86 | /* <public> */ | |
| 87 | MemoryRegion iomem; | |
| 88 | ||
| 89 | qemu_irq irq; | |
| 90 | ||
| 91 | qemu_irq cs_lines[4]; | |
| 92 | ||
| 93 | SSIBus *bus; | |
| 94 | ||
| 95 | uint32_t regs[ECSPI_MAX]; | |
| 96 | ||
| 97 | Fifo32 rx_fifo; | |
| 98 | Fifo32 tx_fifo; | |
| 99 | ||
| 100 | int16_t burst_length; | |
| 101 | } IMXSPIState; | |
| 102 | ||
| 103 | #endif /* IMX_SPI_H */ |