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6363235b AF |
1 | /* |
2 | * Header file for the Xilinx Zynq SPI controller | |
3 | * | |
4 | * Copyright (C) 2015 Xilinx Inc | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
121d0712 MA |
25 | #ifndef XILINX_SPIPS_H |
26 | #define XILINX_SPIPS_H | |
6363235b AF |
27 | |
28 | #include "hw/ssi/ssi.h" | |
c95997a3 FI |
29 | #include "qemu/fifo32.h" |
30 | #include "hw/stream.h" | |
ec150c7e | 31 | #include "hw/sysbus.h" |
db1015e9 | 32 | #include "qom/object.h" |
6363235b AF |
33 | |
34 | typedef struct XilinxSPIPS XilinxSPIPS; | |
35 | ||
36 | #define XLNX_SPIPS_R_MAX (0x100 / 4) | |
4f0da466 | 37 | #define XLNX_ZYNQMP_SPIPS_R_MAX (0x830 / 4) |
6363235b | 38 | |
5394dbcc FI |
39 | /* Bite off 4k chunks at a time */ |
40 | #define LQSPI_CACHE_SIZE 1024 | |
41 | ||
21d887cd SPB |
42 | #define QSPI_DMA_MAX_BURST_SIZE 2048 |
43 | ||
5394dbcc FI |
44 | typedef enum { |
45 | READ = 0x3, READ_4 = 0x13, | |
46 | FAST_READ = 0xb, FAST_READ_4 = 0x0c, | |
47 | DOR = 0x3b, DOR_4 = 0x3c, | |
48 | QOR = 0x6b, QOR_4 = 0x6c, | |
49 | DIOR = 0xbb, DIOR_4 = 0xbc, | |
50 | QIOR = 0xeb, QIOR_4 = 0xec, | |
51 | ||
52 | PP = 0x2, PP_4 = 0x12, | |
53 | DPP = 0xa2, | |
54 | QPP = 0x32, QPP_4 = 0x34, | |
55 | } FlashCMD; | |
56 | ||
6363235b AF |
57 | struct XilinxSPIPS { |
58 | SysBusDevice parent_obj; | |
59 | ||
60 | MemoryRegion iomem; | |
61 | MemoryRegion mmlqspi; | |
62 | ||
63 | qemu_irq irq; | |
64 | int irqline; | |
65 | ||
66 | uint8_t num_cs; | |
67 | uint8_t num_busses; | |
68 | ||
69 | uint8_t snoop_state; | |
ef06ca39 FI |
70 | int cmd_dummies; |
71 | uint8_t link_state; | |
72 | uint8_t link_state_next; | |
73 | uint8_t link_state_next_when; | |
6363235b | 74 | qemu_irq *cs_lines; |
ef06ca39 | 75 | bool *cs_lines_state; |
6363235b AF |
76 | SSIBus **spi; |
77 | ||
78 | Fifo8 rx_fifo; | |
79 | Fifo8 tx_fifo; | |
80 | ||
81 | uint8_t num_txrx_bytes; | |
ef06ca39 | 82 | uint32_t rx_discard; |
6363235b AF |
83 | |
84 | uint32_t regs[XLNX_SPIPS_R_MAX]; | |
275e28cc FI |
85 | |
86 | bool man_start_com; | |
6363235b AF |
87 | }; |
88 | ||
db1015e9 | 89 | struct XilinxQSPIPS { |
5394dbcc FI |
90 | XilinxSPIPS parent_obj; |
91 | ||
92 | uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; | |
93 | hwaddr lqspi_cached_addr; | |
94 | Error *migration_blocker; | |
95 | bool mmio_execution_enabled; | |
db1015e9 EH |
96 | }; |
97 | typedef struct XilinxQSPIPS XilinxQSPIPS; | |
5394dbcc | 98 | |
db1015e9 | 99 | struct XlnxZynqMPQSPIPS { |
c95997a3 FI |
100 | XilinxQSPIPS parent_obj; |
101 | ||
102 | StreamSlave *dma; | |
c95997a3 FI |
103 | int gqspi_irqline; |
104 | ||
105 | uint32_t regs[XLNX_ZYNQMP_SPIPS_R_MAX]; | |
106 | ||
107 | /* GQSPI has seperate tx/rx fifos */ | |
108 | Fifo8 rx_fifo_g; | |
109 | Fifo8 tx_fifo_g; | |
110 | Fifo32 fifo_g; | |
111 | /* | |
112 | * At the end of each generic command, misaligned extra bytes are discard | |
113 | * or padded to tx and rx respectively to round it out (and avoid need for | |
114 | * individual byte access. Since we use byte fifos, keep track of the | |
115 | * alignment WRT to word access. | |
116 | */ | |
117 | uint8_t rx_fifo_g_align; | |
118 | uint8_t tx_fifo_g_align; | |
119 | bool man_start_com_g; | |
21d887cd SPB |
120 | uint32_t dma_burst_size; |
121 | uint8_t dma_buf[QSPI_DMA_MAX_BURST_SIZE]; | |
db1015e9 EH |
122 | }; |
123 | typedef struct XlnxZynqMPQSPIPS XlnxZynqMPQSPIPS; | |
c95997a3 | 124 | |
db1015e9 | 125 | struct XilinxSPIPSClass { |
5394dbcc FI |
126 | SysBusDeviceClass parent_class; |
127 | ||
128 | const MemoryRegionOps *reg_ops; | |
129 | ||
130 | uint32_t rx_fifo_size; | |
131 | uint32_t tx_fifo_size; | |
db1015e9 EH |
132 | }; |
133 | typedef struct XilinxSPIPSClass XilinxSPIPSClass; | |
5394dbcc | 134 | |
6363235b AF |
135 | #define TYPE_XILINX_SPIPS "xlnx.ps7-spi" |
136 | #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" | |
c95997a3 | 137 | #define TYPE_XLNX_ZYNQMP_QSPIPS "xlnx.usmp-gqspi" |
6363235b | 138 | |
8110fa1d EH |
139 | DECLARE_OBJ_CHECKERS(XilinxSPIPS, XilinxSPIPSClass, |
140 | XILINX_SPIPS, TYPE_XILINX_SPIPS) | |
141 | ||
142 | DECLARE_INSTANCE_CHECKER(XilinxQSPIPS, XILINX_QSPIPS, | |
143 | TYPE_XILINX_QSPIPS) | |
144 | ||
145 | DECLARE_INSTANCE_CHECKER(XlnxZynqMPQSPIPS, XLNX_ZYNQMP_QSPIPS, | |
146 | TYPE_XLNX_ZYNQMP_QSPIPS) | |
c95997a3 | 147 | |
121d0712 | 148 | #endif /* XILINX_SPIPS_H */ |