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1/* QEMU Synchronous Serial Interface support. */
2
3/* In principle SSI is a point-point interface. As such the qemu
4 implementation has a single slave device on a "bus".
5 However it is fairly common for boards to have multiple slaves
6 connected to a single master, and select devices with an external
7 chip select. This is implemented in qemu by having an explicit mux device.
8 It is assumed that master and slave are both using the same transfer width.
9 */
10
11#ifndef QEMU_SSI_H
12#define QEMU_SSI_H
13
83c9f4ca 14#include "hw/qdev.h"
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15
16typedef struct SSISlave SSISlave;
17
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18#define TYPE_SSI_SLAVE "ssi-slave"
19#define SSI_SLAVE(obj) \
20 OBJECT_CHECK(SSISlave, (obj), TYPE_SSI_SLAVE)
21#define SSI_SLAVE_CLASS(klass) \
22 OBJECT_CLASS_CHECK(SSISlaveClass, (klass), TYPE_SSI_SLAVE)
23#define SSI_SLAVE_GET_CLASS(obj) \
24 OBJECT_GET_CLASS(SSISlaveClass, (obj), TYPE_SSI_SLAVE)
25
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26#define SSI_GPIO_CS "ssi-gpio-cs"
27
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28typedef enum {
29 SSI_CS_NONE = 0,
30 SSI_CS_LOW,
31 SSI_CS_HIGH,
32} SSICSMode;
33
90d37239 34/* Slave devices. */
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35typedef struct SSISlaveClass {
36 DeviceClass parent_class;
37
81a322d4 38 int (*init)(SSISlave *dev);
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39
40 /* if you have standard or no CS behaviour, just override transfer.
41 * This is called when the device cs is active (true by default).
42 */
90d37239 43 uint32_t (*transfer)(SSISlave *dev, uint32_t val);
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44 /* called when the CS line changes. Optional, devices only need to implement
45 * this if they have side effects associated with the cs line (beyond
46 * tristating the txrx lines).
47 */
48 int (*set_cs)(SSISlave *dev, bool select);
49 /* define whether or not CS exists and is active low/high */
50 SSICSMode cs_polarity;
51
52 /* if you have non-standard CS behaviour override this to take control
53 * of the CS behaviour at the device level. transfer, set_cs, and
54 * cs_polarity are unused if this is overwritten. Transfer_raw will
55 * always be called for the device for every txrx access to the parent bus
56 */
57 uint32_t (*transfer_raw)(SSISlave *dev, uint32_t val);
cd6c4cf2 58} SSISlaveClass;
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59
60struct SSISlave {
1f760d5f 61 DeviceState parent_obj;
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62
63 /* Chip select state */
64 bool cs;
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65};
66
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67#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev)
68
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69extern const VMStateDescription vmstate_ssi_slave;
70
71#define VMSTATE_SSI_SLAVE(_field, _state) { \
72 .name = (stringify(_field)), \
73 .size = sizeof(SSISlave), \
74 .vmsd = &vmstate_ssi_slave, \
75 .flags = VMS_STRUCT, \
76 .offset = vmstate_offset_value(_state, _field, SSISlave), \
77}
78
90d37239 79DeviceState *ssi_create_slave(SSIBus *bus, const char *name);
74687e40 80DeviceState *ssi_create_slave_no_init(SSIBus *bus, const char *name);
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81
82/* Master interface. */
02e2da45 83SSIBus *ssi_create_bus(DeviceState *parent, const char *name);
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84
85uint32_t ssi_transfer(SSIBus *bus, uint32_t val);
86
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87/* Automatically connect all children nodes a spi controller as slaves */
88void ssi_auto_connect_slaves(DeviceState *parent, qemu_irq *cs_lines,
89 SSIBus *bus);
90
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91/* max111x.c */
92void max111x_set_input(DeviceState *dev, int line, uint8_t value);
93
90d37239 94#endif