]>
Commit | Line | Data |
---|---|---|
121d0712 MA |
1 | #ifndef ALLWINNER_A10_PIT_H |
2 | #define ALLWINNER_A10_PIT_H | |
3589de8c LG |
3 | |
4 | #include "hw/ptimer.h" | |
ec150c7e | 5 | #include "hw/sysbus.h" |
db1015e9 | 6 | #include "qom/object.h" |
3589de8c LG |
7 | |
8 | #define TYPE_AW_A10_PIT "allwinner-A10-timer" | |
8063396b | 9 | OBJECT_DECLARE_SIMPLE_TYPE(AwA10PITState, AW_A10_PIT) |
3589de8c LG |
10 | |
11 | #define AW_A10_PIT_TIMER_NR 6 | |
12 | #define AW_A10_PIT_TIMER_IRQ 0x1 | |
13 | #define AW_A10_PIT_WDOG_IRQ 0x100 | |
14 | ||
15 | #define AW_A10_PIT_TIMER_IRQ_EN 0 | |
16 | #define AW_A10_PIT_TIMER_IRQ_ST 0x4 | |
17 | ||
18 | #define AW_A10_PIT_TIMER_CONTROL 0x0 | |
19 | #define AW_A10_PIT_TIMER_EN 0x1 | |
20 | #define AW_A10_PIT_TIMER_RELOAD 0x2 | |
21 | #define AW_A10_PIT_TIMER_MODE 0x80 | |
22 | ||
23 | #define AW_A10_PIT_TIMER_INTERVAL 0x4 | |
24 | #define AW_A10_PIT_TIMER_COUNT 0x8 | |
25 | #define AW_A10_PIT_WDOG_CONTROL 0x90 | |
26 | #define AW_A10_PIT_WDOG_MODE 0x94 | |
27 | ||
28 | #define AW_A10_PIT_COUNT_CTL 0xa0 | |
29 | #define AW_A10_PIT_COUNT_RL_EN 0x2 | |
30 | #define AW_A10_PIT_COUNT_CLR_EN 0x1 | |
31 | #define AW_A10_PIT_COUNT_LO 0xa4 | |
32 | #define AW_A10_PIT_COUNT_HI 0xa8 | |
33 | ||
34 | #define AW_A10_PIT_TIMER_BASE 0x10 | |
35 | #define AW_A10_PIT_TIMER_BASE_END \ | |
36 | (AW_A10_PIT_TIMER_BASE * 6 + AW_A10_PIT_TIMER_COUNT) | |
37 | ||
38 | #define AW_A10_PIT_DEFAULT_CLOCK 0x4 | |
39 | ||
323a8771 BG |
40 | |
41 | typedef struct AwA10TimerContext { | |
42 | AwA10PITState *container; | |
43 | int index; | |
44 | } AwA10TimerContext; | |
45 | ||
46 | struct AwA10PITState { | |
3589de8c LG |
47 | /*< private >*/ |
48 | SysBusDevice parent_obj; | |
49 | /*< public >*/ | |
50 | qemu_irq irq[AW_A10_PIT_TIMER_NR]; | |
51 | ptimer_state * timer[AW_A10_PIT_TIMER_NR]; | |
323a8771 | 52 | AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR]; |
3589de8c | 53 | MemoryRegion iomem; |
286226a4 | 54 | uint32_t clk_freq[4]; |
3589de8c LG |
55 | |
56 | uint32_t irq_enable; | |
57 | uint32_t irq_status; | |
58 | uint32_t control[AW_A10_PIT_TIMER_NR]; | |
59 | uint32_t interval[AW_A10_PIT_TIMER_NR]; | |
60 | uint32_t count[AW_A10_PIT_TIMER_NR]; | |
61 | uint32_t watch_dog_mode; | |
62 | uint32_t watch_dog_control; | |
63 | uint32_t count_lo; | |
64 | uint32_t count_hi; | |
65 | uint32_t count_ctl; | |
323a8771 | 66 | }; |
3589de8c LG |
67 | |
68 | #endif |