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62232bf4 GH |
1 | /* |
2 | * Virtio GPU Device | |
3 | * | |
4 | * Copyright Red Hat, Inc. 2013-2014 | |
5 | * | |
6 | * Authors: | |
7 | * Dave Airlie <airlied@redhat.com> | |
8 | * Gerd Hoffmann <kraxel@redhat.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2. | |
11 | * See the COPYING file in the top-level directory. | |
12 | */ | |
13 | ||
121d0712 MA |
14 | #ifndef HW_VIRTIO_GPU_H |
15 | #define HW_VIRTIO_GPU_H | |
62232bf4 GH |
16 | |
17 | #include "qemu/queue.h" | |
18 | #include "ui/qemu-pixman.h" | |
19 | #include "ui/console.h" | |
20 | #include "hw/virtio/virtio.h" | |
8afc224f | 21 | #include "qemu/log.h" |
62232bf4 GH |
22 | |
23 | #include "standard-headers/linux/virtio_gpu.h" | |
a8bff79e | 24 | |
62232bf4 GH |
25 | #define TYPE_VIRTIO_GPU "virtio-gpu-device" |
26 | #define VIRTIO_GPU(obj) \ | |
27 | OBJECT_CHECK(VirtIOGPU, (obj), TYPE_VIRTIO_GPU) | |
28 | ||
29 | #define VIRTIO_ID_GPU 16 | |
30 | ||
62232bf4 GH |
31 | struct virtio_gpu_simple_resource { |
32 | uint32_t resource_id; | |
33 | uint32_t width; | |
34 | uint32_t height; | |
35 | uint32_t format; | |
0c244e50 | 36 | uint64_t *addrs; |
62232bf4 GH |
37 | struct iovec *iov; |
38 | unsigned int iov_cnt; | |
39 | uint32_t scanout_bitmask; | |
40 | pixman_image_t *image; | |
9b7621bc | 41 | uint64_t hostmem; |
62232bf4 GH |
42 | QTAILQ_ENTRY(virtio_gpu_simple_resource) next; |
43 | }; | |
44 | ||
45 | struct virtio_gpu_scanout { | |
46 | QemuConsole *con; | |
47 | DisplaySurface *ds; | |
48 | uint32_t width, height; | |
49 | int x, y; | |
50 | int invalidate; | |
51 | uint32_t resource_id; | |
0c244e50 | 52 | struct virtio_gpu_update_cursor cursor; |
62232bf4 GH |
53 | QEMUCursor *current_cursor; |
54 | }; | |
55 | ||
56 | struct virtio_gpu_requested_state { | |
57 | uint32_t width, height; | |
58 | int x, y; | |
59 | }; | |
60 | ||
9d9e1521 GH |
61 | enum virtio_gpu_conf_flags { |
62 | VIRTIO_GPU_FLAG_VIRGL_ENABLED = 1, | |
63 | VIRTIO_GPU_FLAG_STATS_ENABLED, | |
64 | }; | |
65 | ||
66 | #define virtio_gpu_virgl_enabled(_cfg) \ | |
67 | (_cfg.flags & (1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED)) | |
68 | #define virtio_gpu_stats_enabled(_cfg) \ | |
69 | (_cfg.flags & (1 << VIRTIO_GPU_FLAG_STATS_ENABLED)) | |
70 | ||
62232bf4 | 71 | struct virtio_gpu_conf { |
9b7621bc | 72 | uint64_t max_hostmem; |
62232bf4 | 73 | uint32_t max_outputs; |
9d9e1521 | 74 | uint32_t flags; |
729abb6a GH |
75 | uint32_t xres; |
76 | uint32_t yres; | |
62232bf4 GH |
77 | }; |
78 | ||
79 | struct virtio_gpu_ctrl_command { | |
80 | VirtQueueElement elem; | |
81 | VirtQueue *vq; | |
82 | struct virtio_gpu_ctrl_hdr cmd_hdr; | |
83 | uint32_t error; | |
0c55a1cf | 84 | bool waiting; |
62232bf4 GH |
85 | bool finished; |
86 | QTAILQ_ENTRY(virtio_gpu_ctrl_command) next; | |
87 | }; | |
88 | ||
89 | typedef struct VirtIOGPU { | |
90 | VirtIODevice parent_obj; | |
91 | ||
92 | QEMUBH *ctrl_bh; | |
93 | QEMUBH *cursor_bh; | |
94 | VirtQueue *ctrl_vq; | |
95 | VirtQueue *cursor_vq; | |
96 | ||
97 | int enable; | |
98 | ||
99 | int config_size; | |
100 | DeviceState *qdev; | |
101 | ||
102 | QTAILQ_HEAD(, virtio_gpu_simple_resource) reslist; | |
3eb769fd | 103 | QTAILQ_HEAD(, virtio_gpu_ctrl_command) cmdq; |
62232bf4 GH |
104 | QTAILQ_HEAD(, virtio_gpu_ctrl_command) fenceq; |
105 | ||
acfc4846 MAL |
106 | struct virtio_gpu_scanout scanout[VIRTIO_GPU_MAX_SCANOUTS]; |
107 | struct virtio_gpu_requested_state req_state[VIRTIO_GPU_MAX_SCANOUTS]; | |
62232bf4 GH |
108 | |
109 | struct virtio_gpu_conf conf; | |
9b7621bc | 110 | uint64_t hostmem; |
62232bf4 GH |
111 | int enabled_output_bitmask; |
112 | struct virtio_gpu_config virtio_config; | |
113 | ||
9d9e1521 GH |
114 | bool use_virgl_renderer; |
115 | bool renderer_inited; | |
c540128f | 116 | int renderer_blocked; |
62232bf4 GH |
117 | QEMUTimer *fence_poll; |
118 | QEMUTimer *print_stats; | |
119 | ||
9d9e1521 | 120 | uint32_t inflight; |
62232bf4 | 121 | struct { |
62232bf4 GH |
122 | uint32_t max_inflight; |
123 | uint32_t requests; | |
124 | uint32_t req_3d; | |
125 | uint32_t bytes_3d; | |
126 | } stats; | |
de889221 DDAG |
127 | |
128 | Error *migration_blocker; | |
62232bf4 GH |
129 | } VirtIOGPU; |
130 | ||
131 | extern const GraphicHwOps virtio_gpu_ops; | |
132 | ||
133 | /* to share between PCI and VGA */ | |
134 | #define DEFINE_VIRTIO_GPU_PCI_PROPERTIES(_state) \ | |
135 | DEFINE_PROP_BIT("ioeventfd", _state, flags, \ | |
136 | VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, false), \ | |
137 | DEFINE_PROP_UINT32("vectors", _state, nvectors, 3) | |
138 | ||
62232bf4 GH |
139 | #define VIRTIO_GPU_FILL_CMD(out) do { \ |
140 | size_t s; \ | |
141 | s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 0, \ | |
142 | &out, sizeof(out)); \ | |
143 | if (s != sizeof(out)) { \ | |
144 | qemu_log_mask(LOG_GUEST_ERROR, \ | |
145 | "%s: command size incorrect %zu vs %zu\n", \ | |
146 | __func__, s, sizeof(out)); \ | |
147 | return; \ | |
148 | } \ | |
149 | } while (0) | |
150 | ||
151 | /* virtio-gpu.c */ | |
43e4dbe2 | 152 | void virtio_gpu_reset(VirtIODevice *vdev); |
62232bf4 GH |
153 | void virtio_gpu_ctrl_response(VirtIOGPU *g, |
154 | struct virtio_gpu_ctrl_command *cmd, | |
155 | struct virtio_gpu_ctrl_hdr *resp, | |
156 | size_t resp_len); | |
157 | void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g, | |
158 | struct virtio_gpu_ctrl_command *cmd, | |
159 | enum virtio_gpu_ctrl_type type); | |
160 | void virtio_gpu_get_display_info(VirtIOGPU *g, | |
161 | struct virtio_gpu_ctrl_command *cmd); | |
162 | int virtio_gpu_create_mapping_iov(struct virtio_gpu_resource_attach_backing *ab, | |
163 | struct virtio_gpu_ctrl_command *cmd, | |
0c244e50 | 164 | uint64_t **addr, struct iovec **iov); |
62232bf4 | 165 | void virtio_gpu_cleanup_mapping_iov(struct iovec *iov, uint32_t count); |
0c55a1cf | 166 | void virtio_gpu_process_cmdq(VirtIOGPU *g); |
62232bf4 | 167 | |
9d9e1521 GH |
168 | /* virtio-gpu-3d.c */ |
169 | void virtio_gpu_virgl_process_cmd(VirtIOGPU *g, | |
170 | struct virtio_gpu_ctrl_command *cmd); | |
171 | void virtio_gpu_virgl_fence_poll(VirtIOGPU *g); | |
172 | void virtio_gpu_virgl_reset(VirtIOGPU *g); | |
c19f4fbc | 173 | void virtio_gpu_gl_block(void *opaque, bool block); |
9d9e1521 | 174 | int virtio_gpu_virgl_init(VirtIOGPU *g); |
5643cc94 | 175 | int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g); |
62232bf4 | 176 | #endif |