[mirror_ubuntu-eoan-kernel.git] / include / kvm / arm_pmu.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2015 Linaro Ltd.
 * Author: Shannon Zhao <shannon.zhao@linaro.org>
 */

#ifndef __ASM_ARM_KVM_PMU_H
#define __ASM_ARM_KVM_PMU_H

#include <linux/perf_event.h>
#include <asm/perf_event.h>

#define ARMV8_PMU_CYCLE_IDX		(ARMV8_PMU_MAX_COUNTERS - 1)

#ifdef CONFIG_KVM_ARM_PMU

struct kvm_pmc {
	u8 idx;	/* index into the pmu->pmc array */
	struct perf_event *perf_event;
	u64 bitmask;
};

struct kvm_pmu {
	int irq_num;
	struct kvm_pmc pmc[ARMV8_PMU_MAX_COUNTERS];
	bool ready;
	bool created;
	bool irq_level;
};

#define kvm_arm_pmu_v3_ready(v)		((v)->arch.pmu.ready)
#define kvm_arm_pmu_irq_initialized(v)	((v)->arch.pmu.irq_num >= VGIC_NR_SGIS)
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val);
u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu);
void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu);
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu);
bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu);
void kvm_pmu_update_run(struct kvm_vcpu *vcpu);
void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
				    u64 select_idx);
bool kvm_arm_support_pmu_v3(void);
int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
			    struct kvm_device_attr *attr);
int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
			    struct kvm_device_attr *attr);
int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
			    struct kvm_device_attr *attr);
int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu);
#else
struct kvm_pmu {
};

#define kvm_arm_pmu_v3_ready(v)		(false)
#define kvm_arm_pmu_irq_initialized(v)	(false)
static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
					    u64 select_idx)
{
	return 0;
}
static inline void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu,
					     u64 select_idx, u64 val) {}
static inline u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
{
	return 0;
}
static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
static inline void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {}
static inline void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
static inline void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) {}
static inline bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu)
{
	return false;
}
static inline void kvm_pmu_update_run(struct kvm_vcpu *vcpu) {}
static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
						  u64 data, u64 select_idx) {}
static inline bool kvm_arm_support_pmu_v3(void) { return false; }
static inline int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
					  struct kvm_device_attr *attr)
{
	return -ENXIO;
}
static inline int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
					  struct kvm_device_attr *attr)
{
	return -ENXIO;
}
static inline int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
					  struct kvm_device_attr *attr)
{
	return -ENXIO;
}
static inline int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu)
{
	return 0;
}
#endif

#endif
Commit	Line	Data
caab277b	1	/* SPDX-License-Identifier: GPL-2.0-only */
04fe4726 SZ	2	/*
	3	* Copyright (C) 2015 Linaro Ltd.
	4	* Author: Shannon Zhao <shannon.zhao@linaro.org>
04fe4726 SZ	5	*/
	6
	7	#ifndef __ASM_ARM_KVM_PMU_H
	8	#define __ASM_ARM_KVM_PMU_H
	9
04fe4726 SZ	10	#include <linux/perf_event.h>
	11	#include <asm/perf_event.h>
	12
051ff581 SZ	13	#define ARMV8_PMU_CYCLE_IDX (ARMV8_PMU_MAX_COUNTERS - 1)
051ff581 SZ	14
0efce9da SH	15	#ifdef CONFIG_KVM_ARM_PMU
0efce9da SH	16
04fe4726 SZ	17	struct kvm_pmc {
	18	u8 idx; /* index into the pmu->pmc array */
	19	struct perf_event *perf_event;
	20	u64 bitmask;
	21	};
	22
	23	struct kvm_pmu {
	24	int irq_num;
	25	struct kvm_pmc pmc[ARMV8_PMU_MAX_COUNTERS];
	26	bool ready;
a2befacf	27	bool created;
b02386eb	28	bool irq_level;
04fe4726	29	};
ab946834 SZ	30
ab946834 SZ	31	#define kvm_arm_pmu_v3_ready(v) ((v)->arch.pmu.ready)
bb0c70bc	32	#define kvm_arm_pmu_irq_initialized(v) ((v)->arch.pmu.irq_num >= VGIC_NR_SGIS)
051ff581 SZ	33	u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
051ff581 SZ	34	void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val);
96b0eebc	35	u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu);
2aa36e98	36	void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
5f0a714a	37	void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu);
96b0eebc SZ	38	void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
96b0eebc SZ	39	void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
b02386eb SZ	40	void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
b02386eb SZ	41	void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu);
3dbbdf78 CD	42	bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu);
3dbbdf78 CD	43	void kvm_pmu_update_run(struct kvm_vcpu *vcpu);
7a0adc70	44	void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
76993739	45	void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
7f766358 SZ	46	void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
7f766358 SZ	47	u64 select_idx);
808e7381	48	bool kvm_arm_support_pmu_v3(void);
bb0c70bc SZ	49	int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
	50	struct kvm_device_attr *attr);
	51	int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
	52	struct kvm_device_attr *attr);
	53	int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
	54	struct kvm_device_attr *attr);
a2befacf	55	int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu);
04fe4726 SZ	56	#else
	57	struct kvm_pmu {
	58	};
ab946834 SZ	59
ab946834 SZ	60	#define kvm_arm_pmu_v3_ready(v) (false)
bb0c70bc	61	#define kvm_arm_pmu_irq_initialized(v) (false)
051ff581 SZ	62	static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
	63	u64 select_idx)
	64	{
	65	return 0;
	66	}
	67	static inline void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu,
	68	u64 select_idx, u64 val) {}
96b0eebc SZ	69	static inline u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
	70	{
	71	return 0;
	72	}
2aa36e98	73	static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
5f0a714a	74	static inline void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {}
96b0eebc SZ	75	static inline void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {}
96b0eebc SZ	76	static inline void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {}
b02386eb SZ	77	static inline void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
b02386eb SZ	78	static inline void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) {}
3dbbdf78 CD	79	static inline bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu)
	80	{
	81	return false;
	82	}
	83	static inline void kvm_pmu_update_run(struct kvm_vcpu *vcpu) {}
7a0adc70	84	static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
76993739	85	static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {}
7f766358 SZ	86	static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
7f766358 SZ	87	u64 data, u64 select_idx) {}
808e7381	88	static inline bool kvm_arm_support_pmu_v3(void) { return false; }
bb0c70bc SZ	89	static inline int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
	90	struct kvm_device_attr *attr)
	91	{
	92	return -ENXIO;
	93	}
	94	static inline int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
	95	struct kvm_device_attr *attr)
	96	{
	97	return -ENXIO;
	98	}
	99	static inline int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
	100	struct kvm_device_attr *attr)
	101	{
	102	return -ENXIO;
	103	}
a2befacf CD	104	static inline int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu)
	105	{
	106	return 0;
	107	}
04fe4726 SZ	108	#endif
	109
	110	#endif