[mirror_ubuntu-artful-kernel.git] / include / kvm / arm_pmu.h

/*
 * Copyright (C) 2015 Linaro Ltd.
 * Author: Shannon Zhao <shannon.zhao@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __ASM_ARM_KVM_PMU_H
#define __ASM_ARM_KVM_PMU_H

#include <linux/perf_event.h>
#include <asm/perf_event.h>

#define ARMV8_PMU_CYCLE_IDX		(ARMV8_PMU_MAX_COUNTERS - 1)

#ifdef CONFIG_KVM_ARM_PMU

struct kvm_pmc {
	u8 idx;	/* index into the pmu->pmc array */
	struct perf_event *perf_event;
	u64 bitmask;
};

struct kvm_pmu {
	int irq_num;
	struct kvm_pmc pmc[ARMV8_PMU_MAX_COUNTERS];
	bool ready;
	bool created;
	bool irq_level;
};

#define kvm_arm_pmu_v3_ready(v)		((v)->arch.pmu.ready)
#define kvm_arm_pmu_irq_initialized(v)	((v)->arch.pmu.irq_num >= VGIC_NR_SGIS)
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val);
u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu);
void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu);
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu);
bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu);
void kvm_pmu_update_run(struct kvm_vcpu *vcpu);
void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
				    u64 select_idx);
bool kvm_arm_support_pmu_v3(void);
int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
			    struct kvm_device_attr *attr);
int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
			    struct kvm_device_attr *attr);
int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
			    struct kvm_device_attr *attr);
int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu);
#else
struct kvm_pmu {
};

#define kvm_arm_pmu_v3_ready(v)		(false)
#define kvm_arm_pmu_irq_initialized(v)	(false)
static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
					    u64 select_idx)
{
	return 0;
}
static inline void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu,
					     u64 select_idx, u64 val) {}
static inline u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
{
	return 0;
}
static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
static inline void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {}
static inline void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
static inline void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) {}
static inline bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu)
{
	return false;
}
static inline void kvm_pmu_update_run(struct kvm_vcpu *vcpu) {}
static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
						  u64 data, u64 select_idx) {}
static inline bool kvm_arm_support_pmu_v3(void) { return false; }
static inline int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
					  struct kvm_device_attr *attr)
{
	return -ENXIO;
}
static inline int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
					  struct kvm_device_attr *attr)
{
	return -ENXIO;
}
static inline int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
					  struct kvm_device_attr *attr)
{
	return -ENXIO;
}
static inline int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu)
{
	return 0;
}
#endif

#endif
Commit	Line	Data
04fe4726 SZ	1	/*
	2	* Copyright (C) 2015 Linaro Ltd.
	3	* Author: Shannon Zhao <shannon.zhao@linaro.org>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#ifndef __ASM_ARM_KVM_PMU_H
	19	#define __ASM_ARM_KVM_PMU_H
	20
04fe4726 SZ	21	#include <linux/perf_event.h>
	22	#include <asm/perf_event.h>
	23
051ff581 SZ	24	#define ARMV8_PMU_CYCLE_IDX (ARMV8_PMU_MAX_COUNTERS - 1)
051ff581 SZ	25
0efce9da SH	26	#ifdef CONFIG_KVM_ARM_PMU
0efce9da SH	27
04fe4726 SZ	28	struct kvm_pmc {
	29	u8 idx; /* index into the pmu->pmc array */
	30	struct perf_event *perf_event;
	31	u64 bitmask;
	32	};
	33
	34	struct kvm_pmu {
	35	int irq_num;
	36	struct kvm_pmc pmc[ARMV8_PMU_MAX_COUNTERS];
	37	bool ready;
a2befacf	38	bool created;
b02386eb	39	bool irq_level;
04fe4726	40	};
ab946834 SZ	41
ab946834 SZ	42	#define kvm_arm_pmu_v3_ready(v) ((v)->arch.pmu.ready)
bb0c70bc	43	#define kvm_arm_pmu_irq_initialized(v) ((v)->arch.pmu.irq_num >= VGIC_NR_SGIS)
051ff581 SZ	44	u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
051ff581 SZ	45	void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val);
96b0eebc	46	u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu);
2aa36e98	47	void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
5f0a714a	48	void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu);
96b0eebc SZ	49	void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
96b0eebc SZ	50	void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
76d883c4	51	void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val);
b02386eb SZ	52	void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
b02386eb SZ	53	void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu);
3dbbdf78 CD	54	bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu);
3dbbdf78 CD	55	void kvm_pmu_update_run(struct kvm_vcpu *vcpu);
7a0adc70	56	void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
76993739	57	void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
7f766358 SZ	58	void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
7f766358 SZ	59	u64 select_idx);
808e7381	60	bool kvm_arm_support_pmu_v3(void);
bb0c70bc SZ	61	int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
	62	struct kvm_device_attr *attr);
	63	int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
	64	struct kvm_device_attr *attr);
	65	int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
	66	struct kvm_device_attr *attr);
a2befacf	67	int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu);
04fe4726 SZ	68	#else
	69	struct kvm_pmu {
	70	};
ab946834 SZ	71
ab946834 SZ	72	#define kvm_arm_pmu_v3_ready(v) (false)
bb0c70bc	73	#define kvm_arm_pmu_irq_initialized(v) (false)
051ff581 SZ	74	static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
	75	u64 select_idx)
	76	{
	77	return 0;
	78	}
	79	static inline void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu,
	80	u64 select_idx, u64 val) {}
96b0eebc SZ	81	static inline u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
	82	{
	83	return 0;
	84	}
2aa36e98	85	static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
5f0a714a	86	static inline void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {}
96b0eebc SZ	87	static inline void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {}
96b0eebc SZ	88	static inline void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {}
76d883c4	89	static inline void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val) {}
b02386eb SZ	90	static inline void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
b02386eb SZ	91	static inline void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) {}
3dbbdf78 CD	92	static inline bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu)
	93	{
	94	return false;
	95	}
	96	static inline void kvm_pmu_update_run(struct kvm_vcpu *vcpu) {}
7a0adc70	97	static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
76993739	98	static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {}
7f766358 SZ	99	static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
7f766358 SZ	100	u64 data, u64 select_idx) {}
808e7381	101	static inline bool kvm_arm_support_pmu_v3(void) { return false; }
bb0c70bc SZ	102	static inline int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
	103	struct kvm_device_attr *attr)
	104	{
	105	return -ENXIO;
	106	}
	107	static inline int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
	108	struct kvm_device_attr *attr)
	109	{
	110	return -ENXIO;
	111	}
	112	static inline int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
	113	struct kvm_device_attr *attr)
	114	{
	115	return -ENXIO;
	116	}
a2befacf CD	117	static inline int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu)
	118	{
	119	return 0;
	120	}
04fe4726 SZ	121	#endif
	122
	123	#endif