[mirror_ubuntu-artful-kernel.git] / include / kvm / arm_vgic.h

/*
 * Copyright (C) 2015, 2016 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __KVM_ARM_VGIC_H
#define __KVM_ARM_VGIC_H

#include <linux/kernel.h>
#include <linux/kvm.h>
#include <linux/irqreturn.h>
#include <linux/spinlock.h>
#include <linux/static_key.h>
#include <linux/types.h>
#include <kvm/iodev.h>
#include <linux/list.h>
#include <linux/jump_label.h>

#define VGIC_V3_MAX_CPUS	255
#define VGIC_V2_MAX_CPUS	8
#define VGIC_NR_IRQS_LEGACY     256
#define VGIC_NR_SGIS		16
#define VGIC_NR_PPIS		16
#define VGIC_NR_PRIVATE_IRQS	(VGIC_NR_SGIS + VGIC_NR_PPIS)
#define VGIC_MAX_PRIVATE	(VGIC_NR_PRIVATE_IRQS - 1)
#define VGIC_MAX_SPI		1019
#define VGIC_MAX_RESERVED	1023
#define VGIC_MIN_LPI		8192
#define KVM_IRQCHIP_NUM_PINS	(1020 - 32)

#define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
#define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \
			 (irq) <= VGIC_MAX_SPI)

enum vgic_type {
	VGIC_V2,		/* Good ol' GICv2 */
	VGIC_V3,		/* New fancy GICv3 */
};

/* same for all guests, as depending only on the _host's_ GIC model */
struct vgic_global {
	/* type of the host GIC */
	enum vgic_type		type;

	/* Physical address of vgic virtual cpu interface */
	phys_addr_t		vcpu_base;

	/* GICV mapping */
	void __iomem		*vcpu_base_va;

	/* virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* Number of implemented list registers */
	int			nr_lr;

	/* Maintenance IRQ number */
	unsigned int		maint_irq;

	/* maximum number of VCPUs allowed (GICv2 limits us to 8) */
	int			max_gic_vcpus;

	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
	bool			can_emulate_gicv2;

	/* GIC system register CPU interface */
	struct static_key_false gicv3_cpuif;

	u32			ich_vtr_el2;
};

extern struct vgic_global kvm_vgic_global_state;

#define VGIC_V2_MAX_LRS		(1 << 6)
#define VGIC_V3_MAX_LRS		16
#define VGIC_V3_LR_INDEX(lr)	(VGIC_V3_MAX_LRS - 1 - lr)

enum vgic_irq_config {
	VGIC_CONFIG_EDGE = 0,
	VGIC_CONFIG_LEVEL
};

struct vgic_irq {
	spinlock_t irq_lock;		/* Protects the content of the struct */
	struct list_head lpi_list;	/* Used to link all LPIs together */
	struct list_head ap_list;

	struct kvm_vcpu *vcpu;		/* SGIs and PPIs: The VCPU
					 * SPIs and LPIs: The VCPU whose ap_list
					 * this is queued on.
					 */

	struct kvm_vcpu *target_vcpu;	/* The VCPU that this interrupt should
					 * be sent to, as a result of the
					 * targets reg (v2) or the
					 * affinity reg (v3).
					 */

	u32 intid;			/* Guest visible INTID */
	bool line_level;		/* Level only */
	bool pending_latch;		/* The pending latch state used to calculate
					 * the pending state for both level
					 * and edge triggered IRQs. */
	bool active;			/* not used for LPIs */
	bool enabled;
	bool hw;			/* Tied to HW IRQ */
	struct kref refcount;		/* Used for LPIs */
	u32 hwintid;			/* HW INTID number */
	union {
		u8 targets;			/* GICv2 target VCPUs mask */
		u32 mpidr;			/* GICv3 target VCPU */
	};
	u8 source;			/* GICv2 SGIs only */
	u8 priority;
	enum vgic_irq_config config;	/* Level or edge */

	void *owner;			/* Opaque pointer to reserve an interrupt
					   for in-kernel devices. */
};

struct vgic_register_region;
struct vgic_its;

enum iodev_type {
	IODEV_CPUIF,
	IODEV_DIST,
	IODEV_REDIST,
	IODEV_ITS
};

struct vgic_io_device {
	gpa_t base_addr;
	union {
		struct kvm_vcpu *redist_vcpu;
		struct vgic_its *its;
	};
	const struct vgic_register_region *regions;
	enum iodev_type iodev_type;
	int nr_regions;
	struct kvm_io_device dev;
};

struct vgic_its {
	/* The base address of the ITS control register frame */
	gpa_t			vgic_its_base;

	bool			enabled;
	struct vgic_io_device	iodev;
	struct kvm_device	*dev;

	/* These registers correspond to GITS_BASER{0,1} */
	u64			baser_device_table;
	u64			baser_coll_table;

	/* Protects the command queue */
	struct mutex		cmd_lock;
	u64			cbaser;
	u32			creadr;
	u32			cwriter;

	/* migration ABI revision in use */
	u32			abi_rev;

	/* Protects the device and collection lists */
	struct mutex		its_lock;
	struct list_head	device_list;
	struct list_head	collection_list;
};

struct vgic_state_iter;

struct vgic_dist {
	bool			in_kernel;
	bool			ready;
	bool			initialized;

	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	u32			vgic_model;

	/* Do injected MSIs require an additional device ID? */
	bool			msis_require_devid;

	int			nr_spis;

	/* TODO: Consider moving to global state */
	/* Virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* base addresses in guest physical address space: */
	gpa_t			vgic_dist_base;		/* distributor */
	union {
		/* either a GICv2 CPU interface */
		gpa_t			vgic_cpu_base;
		/* or a number of GICv3 redistributor regions */
		struct {
			gpa_t		vgic_redist_base;
			gpa_t		vgic_redist_free_offset;
		};
	};

	/* distributor enabled */
	bool			enabled;

	struct vgic_irq		*spis;

	struct vgic_io_device	dist_iodev;

	bool			has_its;

	/*
	 * Contains the attributes and gpa of the LPI configuration table.
	 * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
	 * one address across all redistributors.
	 * GICv3 spec: 6.1.2 "LPI Configuration tables"
	 */
	u64			propbaser;

	/* Protects the lpi_list and the count value below. */
	spinlock_t		lpi_list_lock;
	struct list_head	lpi_list_head;
	int			lpi_list_count;

	/* used by vgic-debug */
	struct vgic_state_iter *iter;
};

struct vgic_v2_cpu_if {
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u64		vgic_elrsr;	/* Saved only */
	u32		vgic_apr;
	u32		vgic_lr[VGIC_V2_MAX_LRS];
};

struct vgic_v3_cpu_if {
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_sre;	/* Restored only, change ignored */
	u32		vgic_elrsr;	/* Saved only */
	u32		vgic_ap0r[4];
	u32		vgic_ap1r[4];
	u64		vgic_lr[VGIC_V3_MAX_LRS];
};

struct vgic_cpu {
	/* CPU vif control registers for world switch */
	union {
		struct vgic_v2_cpu_if	vgic_v2;
		struct vgic_v3_cpu_if	vgic_v3;
	};

	unsigned int used_lrs;
	struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];

	spinlock_t ap_list_lock;	/* Protects the ap_list */

	/*
	 * List of IRQs that this VCPU should consider because they are either
	 * Active or Pending (hence the name; AP list), or because they recently
	 * were one of the two and need to be migrated off this list to another
	 * VCPU.
	 */
	struct list_head ap_list_head;

	/*
	 * Members below are used with GICv3 emulation only and represent
	 * parts of the redistributor.
	 */
	struct vgic_io_device	rd_iodev;
	struct vgic_io_device	sgi_iodev;

	/* Contains the attributes and gpa of the LPI pending tables. */
	u64 pendbaser;

	bool lpis_enabled;

	/* Cache guest priority bits */
	u32 num_pri_bits;

	/* Cache guest interrupt ID bits */
	u32 num_id_bits;
};

extern struct static_key_false vgic_v2_cpuif_trap;
extern struct static_key_false vgic_v3_cpuif_trap;

int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
void kvm_vgic_early_init(struct kvm *kvm);
int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
int kvm_vgic_create(struct kvm *kvm, u32 type);
void kvm_vgic_destroy(struct kvm *kvm);
void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
int kvm_vgic_map_resources(struct kvm *kvm);
int kvm_vgic_hyp_init(void);
void kvm_vgic_init_cpu_hardware(void);

int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
			bool level, void *owner);
int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq);
int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq);
bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq);

int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);

void kvm_vgic_load(struct kvm_vcpu *vcpu);
void kvm_vgic_put(struct kvm_vcpu *vcpu);

#define irqchip_in_kernel(k)	(!!((k)->arch.vgic.in_kernel))
#define vgic_initialized(k)	((k)->arch.vgic.initialized)
#define vgic_ready(k)		((k)->arch.vgic.ready)
#define vgic_valid_spi(k, i)	(((i) >= VGIC_NR_PRIVATE_IRQS) && \
			((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))

bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);

void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);

/**
 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
 *
 * The host's GIC naturally limits the maximum amount of VCPUs a guest
 * can use.
 */
static inline int kvm_vgic_get_max_vcpus(void)
{
	return kvm_vgic_global_state.max_gic_vcpus;
}

int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi);

/**
 * kvm_vgic_setup_default_irq_routing:
 * Setup a default flat gsi routing table mapping all SPIs
 */
int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);

int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner);

#endif /* __KVM_ARM_VGIC_H */
Commit	Line	Data
1a89dd91	1	/*
50926d82	2	* Copyright (C) 2015, 2016 ARM Ltd.
1a89dd91 MZ	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
50926d82	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
1a89dd91	15	*/
50926d82 MZ	16	#ifndef __KVM_ARM_VGIC_H
50926d82 MZ	17	#define __KVM_ARM_VGIC_H
b18b5778	18
b47ef92a MZ	19	#include <linux/kernel.h>
b47ef92a MZ	20	#include <linux/kvm.h>
b47ef92a MZ	21	#include <linux/irqreturn.h>
b47ef92a MZ	22	#include <linux/spinlock.h>
fb5ee369	23	#include <linux/static_key.h>
b47ef92a	24	#include <linux/types.h>
6777f77f	25	#include <kvm/iodev.h>
424c3383	26	#include <linux/list.h>
5a7a8426	27	#include <linux/jump_label.h>
1a89dd91	28
50926d82 MZ	29	#define VGIC_V3_MAX_CPUS 255
	30	#define VGIC_V2_MAX_CPUS 8
	31	#define VGIC_NR_IRQS_LEGACY 256
b47ef92a MZ	32	#define VGIC_NR_SGIS 16
	33	#define VGIC_NR_PPIS 16
	34	#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
50926d82 MZ	35	#define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
	36	#define VGIC_MAX_SPI 1019
	37	#define VGIC_MAX_RESERVED 1023
	38	#define VGIC_MIN_LPI 8192
180ae7b1	39	#define KVM_IRQCHIP_NUM_PINS (1020 - 32)
8f186d52	40
3cba4af3	41	#define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
ebb127f2 CD	42	#define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \
ebb127f2 CD	43	(irq) <= VGIC_MAX_SPI)
3cba4af3	44
50926d82 MZ	45	enum vgic_type {
	46	VGIC_V2, /* Good ol' GICv2 */
	47	VGIC_V3, /* New fancy GICv3 */
	48	};
b47ef92a	49
50926d82 MZ	50	/* same for all guests, as depending only on the _host's_ GIC model */
	51	struct vgic_global {
	52	/* type of the host GIC */
	53	enum vgic_type type;
b47ef92a	54
50926d82 MZ	55	/* Physical address of vgic virtual cpu interface */
50926d82 MZ	56	phys_addr_t vcpu_base;
b47ef92a	57
bf8feb39 MZ	58	/* GICV mapping */
	59	void __iomem *vcpu_base_va;
	60
50926d82 MZ	61	/* virtual control interface mapping */
50926d82 MZ	62	void __iomem *vctrl_base;
b47ef92a	63
50926d82 MZ	64	/* Number of implemented list registers */
50926d82 MZ	65	int nr_lr;
8d5c6b06	66
50926d82 MZ	67	/* Maintenance IRQ number */
50926d82 MZ	68	unsigned int maint_irq;
1a9b1305	69
50926d82 MZ	70	/* maximum number of VCPUs allowed (GICv2 limits us to 8) */
50926d82 MZ	71	int max_gic_vcpus;
8d5c6b06	72
50926d82 MZ	73	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
50926d82 MZ	74	bool can_emulate_gicv2;
5a7a8426 VM	75
	76	/* GIC system register CPU interface */
	77	struct static_key_false gicv3_cpuif;
d017d7b0 VK	78
d017d7b0 VK	79	u32 ich_vtr_el2;
8d5c6b06 MZ	80	};
8d5c6b06 MZ	81
50926d82	82	extern struct vgic_global kvm_vgic_global_state;
beee38b9	83
50926d82 MZ	84	#define VGIC_V2_MAX_LRS (1 << 6)
	85	#define VGIC_V3_MAX_LRS 16
	86	#define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
8d5c6b06	87
50926d82 MZ	88	enum vgic_irq_config {
	89	VGIC_CONFIG_EDGE = 0,
	90	VGIC_CONFIG_LEVEL
ca85f623 MZ	91	};
ca85f623 MZ	92
50926d82 MZ	93	struct vgic_irq {
50926d82 MZ	94	spinlock_t irq_lock; /* Protects the content of the struct */
3802411d	95	struct list_head lpi_list; /* Used to link all LPIs together */
50926d82 MZ	96	struct list_head ap_list;
	97
	98	struct kvm_vcpu vcpu; / SGIs and PPIs: The VCPU
	99	* SPIs and LPIs: The VCPU whose ap_list
	100	* this is queued on.
	101	*/
	102
	103	struct kvm_vcpu target_vcpu; / The VCPU that this interrupt should
	104	* be sent to, as a result of the
	105	* targets reg (v2) or the
	106	* affinity reg (v3).
	107	*/
	108
	109	u32 intid; /* Guest visible INTID */
50926d82	110	bool line_level; /* Level only */
8694e4da CD	111	bool pending_latch; /* The pending latch state used to calculate
	112	* the pending state for both level
	113	* and edge triggered IRQs. */
50926d82 MZ	114	bool active; /* not used for LPIs */
	115	bool enabled;
	116	bool hw; /* Tied to HW IRQ */
5dd4b924	117	struct kref refcount; /* Used for LPIs */
50926d82 MZ	118	u32 hwintid; /* HW INTID number */
	119	union {
	120	u8 targets; /* GICv2 target VCPUs mask */
	121	u32 mpidr; /* GICv3 target VCPU */
	122	};
	123	u8 source; /* GICv2 SGIs only */
	124	u8 priority;
	125	enum vgic_irq_config config; /* Level or edge */
c6ccd30e CD	126
	127	void owner; / Opaque pointer to reserve an interrupt
	128	for in-kernel devices. */
b26e5fda AP	129	};
b26e5fda AP	130
50926d82	131	struct vgic_register_region;
59c5ab40 AP	132	struct vgic_its;
	133
	134	enum iodev_type {
	135	IODEV_CPUIF,
	136	IODEV_DIST,
	137	IODEV_REDIST,
	138	IODEV_ITS
	139	};
50926d82	140
6777f77f	141	struct vgic_io_device {
50926d82	142	gpa_t base_addr;
59c5ab40 AP	143	union {
	144	struct kvm_vcpu *redist_vcpu;
	145	struct vgic_its *its;
	146	};
50926d82	147	const struct vgic_register_region *regions;
59c5ab40	148	enum iodev_type iodev_type;
50926d82	149	int nr_regions;
6777f77f AP	150	struct kvm_io_device dev;
	151	};
	152
59c5ab40 AP	153	struct vgic_its {
	154	/* The base address of the ITS control register frame */
	155	gpa_t vgic_its_base;
	156
	157	bool enabled;
	158	struct vgic_io_device iodev;
bb717644	159	struct kvm_device *dev;
424c3383 AP	160
	161	/* These registers correspond to GITS_BASER{0,1} */
	162	u64 baser_device_table;
	163	u64 baser_coll_table;
	164
	165	/* Protects the command queue */
	166	struct mutex cmd_lock;
	167	u64 cbaser;
	168	u32 creadr;
	169	u32 cwriter;
	170
71afe470 EA	171	/* migration ABI revision in use */
	172	u32 abi_rev;
	173
424c3383 AP	174	/* Protects the device and collection lists */
	175	struct mutex its_lock;
	176	struct list_head device_list;
	177	struct list_head collection_list;
59c5ab40 AP	178	};
59c5ab40 AP	179
10f92c4c CD	180	struct vgic_state_iter;
10f92c4c CD	181
1a89dd91	182	struct vgic_dist {
f982cf4e	183	bool in_kernel;
01ac5e34	184	bool ready;
50926d82	185	bool initialized;
b47ef92a	186
59892136 AP	187	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	188	u32 vgic_model;
	189
0e4e82f1 AP	190	/* Do injected MSIs require an additional device ID? */
	191	bool msis_require_devid;
	192
50926d82	193	int nr_spis;
c1bfb577	194
50926d82	195	/* TODO: Consider moving to global state */
b47ef92a MZ	196	/* Virtual control interface mapping */
	197	void __iomem *vctrl_base;
	198
50926d82 MZ	199	/* base addresses in guest physical address space: */
50926d82 MZ	200	gpa_t vgic_dist_base; /* distributor */
a0675c25	201	union {
50926d82 MZ	202	/* either a GICv2 CPU interface */
	203	gpa_t vgic_cpu_base;
	204	/* or a number of GICv3 redistributor regions */
552c9f47 CD	205	struct {
	206	gpa_t vgic_redist_base;
	207	gpa_t vgic_redist_free_offset;
	208	};
a0675c25	209	};
b47ef92a	210
50926d82 MZ	211	/* distributor enabled */
50926d82 MZ	212	bool enabled;
47a98b15	213
50926d82	214	struct vgic_irq *spis;
b47ef92a	215
a9cf86f6	216	struct vgic_io_device dist_iodev;
0aa1de57	217
1085fdc6 AP	218	bool has_its;
1085fdc6 AP	219
0aa1de57 AP	220	/*
	221	* Contains the attributes and gpa of the LPI configuration table.
	222	* Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
	223	* one address across all redistributors.
	224	* GICv3 spec: 6.1.2 "LPI Configuration tables"
	225	*/
	226	u64 propbaser;
3802411d AP	227
	228	/* Protects the lpi_list and the count value below. */
	229	spinlock_t lpi_list_lock;
	230	struct list_head lpi_list_head;
	231	int lpi_list_count;
10f92c4c CD	232
	233	/* used by vgic-debug */
	234	struct vgic_state_iter *iter;
1a89dd91 MZ	235	};
1a89dd91 MZ	236
eede821d MZ	237	struct vgic_v2_cpu_if {
	238	u32 vgic_hcr;
	239	u32 vgic_vmcr;
2df36a5d	240	u64 vgic_elrsr; /* Saved only */
eede821d	241	u32 vgic_apr;
8f186d52	242	u32 vgic_lr[VGIC_V2_MAX_LRS];
eede821d MZ	243	};
eede821d MZ	244
b2fb1c0d	245	struct vgic_v3_cpu_if {
b2fb1c0d MZ	246	u32 vgic_hcr;
b2fb1c0d MZ	247	u32 vgic_vmcr;
2f5fa41a	248	u32 vgic_sre; /* Restored only, change ignored */
b2fb1c0d MZ	249	u32 vgic_elrsr; /* Saved only */
	250	u32 vgic_ap0r[4];
	251	u32 vgic_ap1r[4];
	252	u64 vgic_lr[VGIC_V3_MAX_LRS];
b2fb1c0d MZ	253	};
b2fb1c0d MZ	254
1a89dd91	255	struct vgic_cpu {
9d949dce	256	/* CPU vif control registers for world switch */
eede821d MZ	257	union {
eede821d MZ	258	struct vgic_v2_cpu_if vgic_v2;
b2fb1c0d	259	struct vgic_v3_cpu_if vgic_v3;
eede821d	260	};
6c3d63c9	261
50926d82 MZ	262	unsigned int used_lrs;
50926d82 MZ	263	struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
1a89dd91	264
50926d82	265	spinlock_t ap_list_lock; /* Protects the ap_list */
9d949dce	266
50926d82 MZ	267	/*
	268	* List of IRQs that this VCPU should consider because they are either
	269	* Active or Pending (hence the name; AP list), or because they recently
	270	* were one of the two and need to be migrated off this list to another
	271	* VCPU.
	272	*/
	273	struct list_head ap_list_head;
495dd859	274
8f6cdc1c AP	275	/*
	276	* Members below are used with GICv3 emulation only and represent
	277	* parts of the redistributor.
	278	*/
	279	struct vgic_io_device rd_iodev;
	280	struct vgic_io_device sgi_iodev;
0aa1de57 AP	281
	282	/* Contains the attributes and gpa of the LPI pending tables. */
	283	u64 pendbaser;
	284
	285	bool lpis_enabled;
d017d7b0 VK	286
	287	/* Cache guest priority bits */
	288	u32 num_pri_bits;
	289
	290	/* Cache guest interrupt ID bits */
	291	u32 num_id_bits;
50926d82	292	};
1a89dd91	293
fb5ee369	294	extern struct static_key_false vgic_v2_cpuif_trap;
59da1cbf	295	extern struct static_key_false vgic_v3_cpuif_trap;
fb5ee369	296
ce01e4e8	297	int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write);
6c3d63c9	298	void kvm_vgic_early_init(struct kvm *kvm);
1aab6f46	299	int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
59892136	300	int kvm_vgic_create(struct kvm *kvm, u32 type);
c1bfb577	301	void kvm_vgic_destroy(struct kvm *kvm);
6c3d63c9	302	void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
c1bfb577	303	void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
50926d82 MZ	304	int kvm_vgic_map_resources(struct kvm *kvm);
50926d82 MZ	305	int kvm_vgic_hyp_init(void);
5b0d2cc2	306	void kvm_vgic_init_cpu_hardware(void);
50926d82 MZ	307
50926d82 MZ	308	int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
cb3f0ad8	309	bool level, void *owner);
50926d82	310	int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq);
63306c28	311	int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq);
e262f419	312	bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq);
1a89dd91	313
50926d82 MZ	314	int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
50926d82 MZ	315
328e5664 CD	316	void kvm_vgic_load(struct kvm_vcpu *vcpu);
	317	void kvm_vgic_put(struct kvm_vcpu *vcpu);
	318
f982cf4e	319	#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
50926d82	320	#define vgic_initialized(k) ((k)->arch.vgic.initialized)
c52edf5f	321	#define vgic_ready(k) ((k)->arch.vgic.ready)
2defaff4	322	#define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \
50926d82 MZ	323	((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
	324
	325	bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
	326	void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
	327	void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
9d949dce	328
50926d82	329	void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
8f186d52	330
50926d82 MZ	331	/**
	332	* kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
	333	*
	334	* The host's GIC naturally limits the maximum amount of VCPUs a guest
	335	* can use.
	336	*/
	337	static inline int kvm_vgic_get_max_vcpus(void)
	338	{
	339	return kvm_vgic_global_state.max_gic_vcpus;
	340	}
	341
0e4e82f1 AP	342	int kvm_send_userspace_msi(struct kvm kvm, struct kvm_msi msi);
0e4e82f1 AP	343
180ae7b1 EA	344	/**
	345	* kvm_vgic_setup_default_irq_routing:
	346	* Setup a default flat gsi routing table mapping all SPIs
	347	*/
	348	int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);
	349
c6ccd30e CD	350	int kvm_vgic_set_owner(struct kvm_vcpu vcpu, unsigned int intid, void owner);
c6ccd30e CD	351
50926d82	352	#endif /* __KVM_ARM_VGIC_H */