[mirror_ubuntu-bionic-kernel.git] / include / kvm / arm_vgic.h

/*
 * Copyright (C) 2012 ARM Ltd.
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */

#ifndef __ASM_ARM_KVM_VGIC_H
#define __ASM_ARM_KVM_VGIC_H

#include <linux/kernel.h>
#include <linux/kvm.h>
#include <linux/irqreturn.h>
#include <linux/spinlock.h>
#include <linux/types.h>

#define VGIC_NR_IRQS		256
#define VGIC_NR_SGIS		16
#define VGIC_NR_PPIS		16
#define VGIC_NR_PRIVATE_IRQS	(VGIC_NR_SGIS + VGIC_NR_PPIS)
#define VGIC_NR_SHARED_IRQS	(VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
#define VGIC_MAX_CPUS		KVM_MAX_VCPUS

#define VGIC_V2_MAX_LRS		(1 << 6)
#define VGIC_V3_MAX_LRS		16

/* Sanity checks... */
#if (VGIC_MAX_CPUS > 8)
#error	Invalid number of CPU interfaces
#endif

#if (VGIC_NR_IRQS & 31)
#error "VGIC_NR_IRQS must be a multiple of 32"
#endif

#if (VGIC_NR_IRQS > 1024)
#error "VGIC_NR_IRQS must be <= 1024"
#endif

/*
 * The GIC distributor registers describing interrupts have two parts:
 * - 32 per-CPU interrupts (SGI + PPI)
 * - a bunch of shared interrupts (SPI)
 */
struct vgic_bitmap {
	union {
		u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
		DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
	} percpu[VGIC_MAX_CPUS];
	union {
		u32 reg[VGIC_NR_SHARED_IRQS / 32];
		DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
	} shared;
};

struct vgic_bytemap {
	u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
	u32 shared[VGIC_NR_SHARED_IRQS  / 4];
};

struct kvm_vcpu;

enum vgic_type {
	VGIC_V2,		/* Good ol' GICv2 */
	VGIC_V3,		/* New fancy GICv3 */
};

#define LR_STATE_PENDING	(1 << 0)
#define LR_STATE_ACTIVE		(1 << 1)
#define LR_STATE_MASK		(3 << 0)
#define LR_EOI_INT		(1 << 2)

struct vgic_lr {
	u16	irq;
	u8	source;
	u8	state;
};

struct vgic_vmcr {
	u32	ctlr;
	u32	abpr;
	u32	bpr;
	u32	pmr;
};

struct vgic_ops {
	struct vgic_lr	(*get_lr)(const struct kvm_vcpu *, int);
	void	(*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
	void	(*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr);
	u64	(*get_elrsr)(const struct kvm_vcpu *vcpu);
	u64	(*get_eisr)(const struct kvm_vcpu *vcpu);
	u32	(*get_interrupt_status)(const struct kvm_vcpu *vcpu);
	void	(*enable_underflow)(struct kvm_vcpu *vcpu);
	void	(*disable_underflow)(struct kvm_vcpu *vcpu);
	void	(*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
	void	(*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
	void	(*enable)(struct kvm_vcpu *vcpu);
};

struct vgic_params {
	/* vgic type */
	enum vgic_type	type;
	/* Physical address of vgic virtual cpu interface */
	phys_addr_t	vcpu_base;
	/* Number of list registers */
	u32		nr_lr;
	/* Interrupt number */
	unsigned int	maint_irq;
	/* Virtual control interface base address */
	void __iomem	*vctrl_base;
};

struct vgic_dist {
#ifdef CONFIG_KVM_ARM_VGIC
	spinlock_t		lock;
	bool			in_kernel;
	bool			ready;

	/* Virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* Distributor and vcpu interface mapping in the guest */
	phys_addr_t		vgic_dist_base;
	phys_addr_t		vgic_cpu_base;

	/* Distributor enabled */
	u32			enabled;

	/* Interrupt enabled (one bit per IRQ) */
	struct vgic_bitmap	irq_enabled;

	/* Interrupt 'pin' level */
	struct vgic_bitmap	irq_state;

	/* Level-triggered interrupt in progress */
	struct vgic_bitmap	irq_active;

	/* Interrupt priority. Not used yet. */
	struct vgic_bytemap	irq_priority;

	/* Level/edge triggered */
	struct vgic_bitmap	irq_cfg;

	/* Source CPU per SGI and target CPU */
	u8			irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];

	/* Target CPU for each IRQ */
	u8			irq_spi_cpu[VGIC_NR_SHARED_IRQS];
	struct vgic_bitmap	irq_spi_target[VGIC_MAX_CPUS];

	/* Bitmap indicating which CPU has something pending */
	unsigned long		irq_pending_on_cpu;
#endif
};

struct vgic_v2_cpu_if {
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_misr;	/* Saved only */
	u32		vgic_eisr[2];	/* Saved only */
	u32		vgic_elrsr[2];	/* Saved only */
	u32		vgic_apr;
	u32		vgic_lr[VGIC_V2_MAX_LRS];
};

struct vgic_v3_cpu_if {
#ifdef CONFIG_ARM_GIC_V3
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_misr;	/* Saved only */
	u32		vgic_eisr;	/* Saved only */
	u32		vgic_elrsr;	/* Saved only */
	u32		vgic_ap0r[4];
	u32		vgic_ap1r[4];
	u64		vgic_lr[VGIC_V3_MAX_LRS];
#endif
};

struct vgic_cpu {
#ifdef CONFIG_KVM_ARM_VGIC
	/* per IRQ to LR mapping */
	u8		vgic_irq_lr_map[VGIC_NR_IRQS];

	/* Pending interrupts on this VCPU */
	DECLARE_BITMAP(	pending_percpu, VGIC_NR_PRIVATE_IRQS);
	DECLARE_BITMAP(	pending_shared, VGIC_NR_SHARED_IRQS);

	/* Bitmap of used/free list registers */
	DECLARE_BITMAP(	lr_used, VGIC_V2_MAX_LRS);

	/* Number of list registers on this CPU */
	int		nr_lr;

	/* CPU vif control registers for world switch */
	union {
		struct vgic_v2_cpu_if	vgic_v2;
		struct vgic_v3_cpu_if	vgic_v3;
	};
#endif
};

#define LR_EMPTY	0xff

#define INT_STATUS_EOI		(1 << 0)
#define INT_STATUS_UNDERFLOW	(1 << 1)

struct kvm;
struct kvm_vcpu;
struct kvm_run;
struct kvm_exit_mmio;

#ifdef CONFIG_KVM_ARM_VGIC
int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
int kvm_vgic_hyp_init(void);
int kvm_vgic_init(struct kvm *kvm);
int kvm_vgic_create(struct kvm *kvm);
int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
			bool level);
int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
		      struct kvm_exit_mmio *mmio);

#define irqchip_in_kernel(k)	(!!((k)->arch.vgic.in_kernel))
#define vgic_initialized(k)	((k)->arch.vgic.ready)

int vgic_v2_probe(struct device_node *vgic_node,
		  const struct vgic_ops **ops,
		  const struct vgic_params **params);
#ifdef CONFIG_ARM_GIC_V3
int vgic_v3_probe(struct device_node *vgic_node,
		  const struct vgic_ops **ops,
		  const struct vgic_params **params);
#else
static inline int vgic_v3_probe(struct device_node *vgic_node,
				const struct vgic_ops **ops,
				const struct vgic_params **params)
{
	return -ENODEV;
}
#endif

#else
static inline int kvm_vgic_hyp_init(void)
{
	return 0;
}

static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
{
	return 0;
}

static inline int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
{
	return -ENXIO;
}

static inline int kvm_vgic_init(struct kvm *kvm)
{
	return 0;
}

static inline int kvm_vgic_create(struct kvm *kvm)
{
	return 0;
}

static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
{
	return 0;
}

static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}

static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
				      unsigned int irq_num, bool level)
{
	return 0;
}

static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
{
	return 0;
}

static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
				    struct kvm_exit_mmio *mmio)
{
	return false;
}

static inline int irqchip_in_kernel(struct kvm *kvm)
{
	return 0;
}

static inline bool vgic_initialized(struct kvm *kvm)
{
	return true;
}
#endif

#endif
Commit	Line	Data
1a89dd91 MZ	1	/*
	2	* Copyright (C) 2012 ARM Ltd.
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*/
	18
	19	#ifndef __ASM_ARM_KVM_VGIC_H
	20	#define __ASM_ARM_KVM_VGIC_H
	21
b47ef92a MZ	22	#include <linux/kernel.h>
b47ef92a MZ	23	#include <linux/kvm.h>
b47ef92a MZ	24	#include <linux/irqreturn.h>
	25	#include <linux/spinlock.h>
	26	#include <linux/types.h>
1a89dd91	27
9b2d2e0d	28	#define VGIC_NR_IRQS 256
b47ef92a MZ	29	#define VGIC_NR_SGIS 16
	30	#define VGIC_NR_PPIS 16
	31	#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
	32	#define VGIC_NR_SHARED_IRQS (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
	33	#define VGIC_MAX_CPUS KVM_MAX_VCPUS
8f186d52 MZ	34
8f186d52 MZ	35	#define VGIC_V2_MAX_LRS (1 << 6)
b2fb1c0d	36	#define VGIC_V3_MAX_LRS 16
b47ef92a MZ	37
	38	/* Sanity checks... */
	39	#if (VGIC_MAX_CPUS > 8)
	40	#error Invalid number of CPU interfaces
	41	#endif
	42
	43	#if (VGIC_NR_IRQS & 31)
	44	#error "VGIC_NR_IRQS must be a multiple of 32"
	45	#endif
	46
	47	#if (VGIC_NR_IRQS > 1024)
	48	#error "VGIC_NR_IRQS must be <= 1024"
	49	#endif
	50
	51	/*
	52	* The GIC distributor registers describing interrupts have two parts:
	53	* - 32 per-CPU interrupts (SGI + PPI)
	54	* - a bunch of shared interrupts (SPI)
	55	*/
	56	struct vgic_bitmap {
	57	union {
	58	u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
	59	DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
	60	} percpu[VGIC_MAX_CPUS];
	61	union {
	62	u32 reg[VGIC_NR_SHARED_IRQS / 32];
	63	DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
	64	} shared;
	65	};
	66
	67	struct vgic_bytemap {
	68	u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
	69	u32 shared[VGIC_NR_SHARED_IRQS / 4];
	70	};
	71
8d5c6b06 MZ	72	struct kvm_vcpu;
8d5c6b06 MZ	73
1a9b1305 MZ	74	enum vgic_type {
1a9b1305 MZ	75	VGIC_V2, /* Good ol' GICv2 */
b2fb1c0d	76	VGIC_V3, /* New fancy GICv3 */
1a9b1305 MZ	77	};
1a9b1305 MZ	78
8d5c6b06 MZ	79	#define LR_STATE_PENDING (1 << 0)
	80	#define LR_STATE_ACTIVE (1 << 1)
	81	#define LR_STATE_MASK (3 << 0)
	82	#define LR_EOI_INT (1 << 2)
	83
	84	struct vgic_lr {
	85	u16 irq;
	86	u8 source;
	87	u8 state;
	88	};
	89
beee38b9 MZ	90	struct vgic_vmcr {
	91	u32 ctlr;
	92	u32 abpr;
	93	u32 bpr;
	94	u32 pmr;
	95	};
	96
8d5c6b06 MZ	97	struct vgic_ops {
	98	struct vgic_lr (get_lr)(const struct kvm_vcpu , int);
	99	void (set_lr)(struct kvm_vcpu , int, struct vgic_lr);
69bb2c9f MZ	100	void (sync_lr_elrsr)(struct kvm_vcpu , int, struct vgic_lr);
69bb2c9f MZ	101	u64 (get_elrsr)(const struct kvm_vcpu vcpu);
8d6a0313	102	u64 (get_eisr)(const struct kvm_vcpu vcpu);
495dd859	103	u32 (get_interrupt_status)(const struct kvm_vcpu vcpu);
909d9b50 MZ	104	void (enable_underflow)(struct kvm_vcpu vcpu);
909d9b50 MZ	105	void (disable_underflow)(struct kvm_vcpu vcpu);
beee38b9 MZ	106	void (get_vmcr)(struct kvm_vcpu vcpu, struct vgic_vmcr *vmcr);
beee38b9 MZ	107	void (set_vmcr)(struct kvm_vcpu vcpu, struct vgic_vmcr *vmcr);
da8dafd1	108	void (enable)(struct kvm_vcpu vcpu);
8d5c6b06 MZ	109	};
8d5c6b06 MZ	110
ca85f623	111	struct vgic_params {
1a9b1305 MZ	112	/* vgic type */
1a9b1305 MZ	113	enum vgic_type type;
ca85f623 MZ	114	/* Physical address of vgic virtual cpu interface */
	115	phys_addr_t vcpu_base;
	116	/* Number of list registers */
	117	u32 nr_lr;
	118	/* Interrupt number */
	119	unsigned int maint_irq;
	120	/* Virtual control interface base address */
	121	void __iomem *vctrl_base;
	122	};
	123
1a89dd91	124	struct vgic_dist {
b47ef92a MZ	125	#ifdef CONFIG_KVM_ARM_VGIC
b47ef92a MZ	126	spinlock_t lock;
f982cf4e	127	bool in_kernel;
01ac5e34	128	bool ready;
b47ef92a MZ	129
	130	/* Virtual control interface mapping */
	131	void __iomem *vctrl_base;
	132
330690cd CD	133	/* Distributor and vcpu interface mapping in the guest */
	134	phys_addr_t vgic_dist_base;
	135	phys_addr_t vgic_cpu_base;
b47ef92a MZ	136
	137	/* Distributor enabled */
	138	u32 enabled;
	139
	140	/* Interrupt enabled (one bit per IRQ) */
	141	struct vgic_bitmap irq_enabled;
	142
	143	/* Interrupt 'pin' level */
	144	struct vgic_bitmap irq_state;
	145
	146	/* Level-triggered interrupt in progress */
	147	struct vgic_bitmap irq_active;
	148
	149	/* Interrupt priority. Not used yet. */
	150	struct vgic_bytemap irq_priority;
	151
	152	/* Level/edge triggered */
	153	struct vgic_bitmap irq_cfg;
	154
	155	/* Source CPU per SGI and target CPU */
	156	u8 irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];
	157
	158	/* Target CPU for each IRQ */
	159	u8 irq_spi_cpu[VGIC_NR_SHARED_IRQS];
	160	struct vgic_bitmap irq_spi_target[VGIC_MAX_CPUS];
	161
	162	/* Bitmap indicating which CPU has something pending */
	163	unsigned long irq_pending_on_cpu;
	164	#endif
1a89dd91 MZ	165	};
1a89dd91 MZ	166
eede821d MZ	167	struct vgic_v2_cpu_if {
	168	u32 vgic_hcr;
	169	u32 vgic_vmcr;
	170	u32 vgic_misr; /* Saved only */
	171	u32 vgic_eisr[2]; /* Saved only */
	172	u32 vgic_elrsr[2]; /* Saved only */
	173	u32 vgic_apr;
8f186d52	174	u32 vgic_lr[VGIC_V2_MAX_LRS];
eede821d MZ	175	};
eede821d MZ	176
b2fb1c0d MZ	177	struct vgic_v3_cpu_if {
	178	#ifdef CONFIG_ARM_GIC_V3
	179	u32 vgic_hcr;
	180	u32 vgic_vmcr;
	181	u32 vgic_misr; /* Saved only */
	182	u32 vgic_eisr; /* Saved only */
	183	u32 vgic_elrsr; /* Saved only */
	184	u32 vgic_ap0r[4];
	185	u32 vgic_ap1r[4];
	186	u64 vgic_lr[VGIC_V3_MAX_LRS];
	187	#endif
	188	};
	189
1a89dd91	190	struct vgic_cpu {
9d949dce MZ	191	#ifdef CONFIG_KVM_ARM_VGIC
	192	/* per IRQ to LR mapping */
	193	u8 vgic_irq_lr_map[VGIC_NR_IRQS];
	194
	195	/* Pending interrupts on this VCPU */
	196	DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
	197	DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS);
	198
	199	/* Bitmap of used/free list registers */
8f186d52	200	DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS);
9d949dce MZ	201
	202	/* Number of list registers on this CPU */
	203	int nr_lr;
	204
	205	/* CPU vif control registers for world switch */
eede821d MZ	206	union {
eede821d MZ	207	struct vgic_v2_cpu_if vgic_v2;
b2fb1c0d	208	struct vgic_v3_cpu_if vgic_v3;
eede821d	209	};
9d949dce	210	#endif
1a89dd91 MZ	211	};
1a89dd91 MZ	212
9d949dce MZ	213	#define LR_EMPTY 0xff
9d949dce MZ	214
495dd859 MZ	215	#define INT_STATUS_EOI (1 << 0)
	216	#define INT_STATUS_UNDERFLOW (1 << 1)
	217
1a89dd91 MZ	218	struct kvm;
	219	struct kvm_vcpu;
	220	struct kvm_run;
	221	struct kvm_exit_mmio;
	222
	223	#ifdef CONFIG_KVM_ARM_VGIC
ce01e4e8	224	int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write);
01ac5e34 MZ	225	int kvm_vgic_hyp_init(void);
	226	int kvm_vgic_init(struct kvm *kvm);
	227	int kvm_vgic_create(struct kvm *kvm);
	228	int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
9d949dce MZ	229	void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
9d949dce MZ	230	void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
5863c2ce MZ	231	int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
5863c2ce MZ	232	bool level);
9d949dce	233	int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
1a89dd91 MZ	234	bool vgic_handle_mmio(struct kvm_vcpu vcpu, struct kvm_run run,
	235	struct kvm_exit_mmio *mmio);
	236
f982cf4e	237	#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
01ac5e34	238	#define vgic_initialized(k) ((k)->arch.vgic.ready)
9d949dce	239
8f186d52 MZ	240	int vgic_v2_probe(struct device_node *vgic_node,
	241	const struct vgic_ops **ops,
	242	const struct vgic_params **params);
b2fb1c0d MZ	243	#ifdef CONFIG_ARM_GIC_V3
	244	int vgic_v3_probe(struct device_node *vgic_node,
	245	const struct vgic_ops **ops,
	246	const struct vgic_params **params);
	247	#else
	248	static inline int vgic_v3_probe(struct device_node *vgic_node,
	249	const struct vgic_ops **ops,
	250	const struct vgic_params **params)
	251	{
	252	return -ENODEV;
	253	}
	254	#endif
8f186d52	255
1a89dd91 MZ	256	#else
	257	static inline int kvm_vgic_hyp_init(void)
	258	{
	259	return 0;
	260	}
	261
330690cd CD	262	static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
	263	{
	264	return 0;
	265	}
	266
6cbde825 MZ	267	static inline int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write)
	268	{
	269	return -ENXIO;
	270	}
	271
1a89dd91 MZ	272	static inline int kvm_vgic_init(struct kvm *kvm)
	273	{
	274	return 0;
	275	}
	276
	277	static inline int kvm_vgic_create(struct kvm *kvm)
	278	{
	279	return 0;
	280	}
	281
	282	static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
	283	{
	284	return 0;
	285	}
	286
	287	static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
	288	static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
	289
5863c2ce MZ	290	static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
	291	unsigned int irq_num, bool level)
	292	{
	293	return 0;
	294	}
	295
1a89dd91 MZ	296	static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
	297	{
	298	return 0;
	299	}
	300
	301	static inline bool vgic_handle_mmio(struct kvm_vcpu vcpu, struct kvm_run run,
	302	struct kvm_exit_mmio *mmio)
	303	{
	304	return false;
	305	}
	306
	307	static inline int irqchip_in_kernel(struct kvm *kvm)
	308	{
	309	return 0;
	310	}
01ac5e34 MZ	311
	312	static inline bool vgic_initialized(struct kvm *kvm)
	313	{
	314	return true;
	315	}
1a89dd91 MZ	316	#endif
	317
	318	#endif