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Commit | Line | Data |
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caab277b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
1a89dd91 | 2 | /* |
50926d82 | 3 | * Copyright (C) 2015, 2016 ARM Ltd. |
1a89dd91 | 4 | */ |
50926d82 MZ |
5 | #ifndef __KVM_ARM_VGIC_H |
6 | #define __KVM_ARM_VGIC_H | |
b18b5778 | 7 | |
b47ef92a MZ |
8 | #include <linux/kernel.h> |
9 | #include <linux/kvm.h> | |
b47ef92a MZ |
10 | #include <linux/irqreturn.h> |
11 | #include <linux/spinlock.h> | |
fb5ee369 | 12 | #include <linux/static_key.h> |
b47ef92a | 13 | #include <linux/types.h> |
6777f77f | 14 | #include <kvm/iodev.h> |
424c3383 | 15 | #include <linux/list.h> |
5a7a8426 | 16 | #include <linux/jump_label.h> |
1a89dd91 | 17 | |
74fe55dc MZ |
18 | #include <linux/irqchip/arm-gic-v4.h> |
19 | ||
e25028c8 | 20 | #define VGIC_V3_MAX_CPUS 512 |
50926d82 MZ |
21 | #define VGIC_V2_MAX_CPUS 8 |
22 | #define VGIC_NR_IRQS_LEGACY 256 | |
b47ef92a MZ |
23 | #define VGIC_NR_SGIS 16 |
24 | #define VGIC_NR_PPIS 16 | |
25 | #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) | |
50926d82 MZ |
26 | #define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1) |
27 | #define VGIC_MAX_SPI 1019 | |
28 | #define VGIC_MAX_RESERVED 1023 | |
29 | #define VGIC_MIN_LPI 8192 | |
180ae7b1 | 30 | #define KVM_IRQCHIP_NUM_PINS (1020 - 32) |
8f186d52 | 31 | |
3cba4af3 | 32 | #define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS) |
ebb127f2 CD |
33 | #define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \ |
34 | (irq) <= VGIC_MAX_SPI) | |
3cba4af3 | 35 | |
50926d82 MZ |
36 | enum vgic_type { |
37 | VGIC_V2, /* Good ol' GICv2 */ | |
38 | VGIC_V3, /* New fancy GICv3 */ | |
39 | }; | |
b47ef92a | 40 | |
50926d82 MZ |
41 | /* same for all guests, as depending only on the _host's_ GIC model */ |
42 | struct vgic_global { | |
43 | /* type of the host GIC */ | |
44 | enum vgic_type type; | |
b47ef92a | 45 | |
50926d82 MZ |
46 | /* Physical address of vgic virtual cpu interface */ |
47 | phys_addr_t vcpu_base; | |
b47ef92a | 48 | |
1bb32a44 | 49 | /* GICV mapping, kernel VA */ |
bf8feb39 | 50 | void __iomem *vcpu_base_va; |
1bb32a44 MZ |
51 | /* GICV mapping, HYP VA */ |
52 | void __iomem *vcpu_hyp_va; | |
bf8feb39 | 53 | |
1bb32a44 | 54 | /* virtual control interface mapping, kernel VA */ |
50926d82 | 55 | void __iomem *vctrl_base; |
1bb32a44 MZ |
56 | /* virtual control interface mapping, HYP VA */ |
57 | void __iomem *vctrl_hyp; | |
b47ef92a | 58 | |
50926d82 MZ |
59 | /* Number of implemented list registers */ |
60 | int nr_lr; | |
8d5c6b06 | 61 | |
50926d82 MZ |
62 | /* Maintenance IRQ number */ |
63 | unsigned int maint_irq; | |
1a9b1305 | 64 | |
50926d82 MZ |
65 | /* maximum number of VCPUs allowed (GICv2 limits us to 8) */ |
66 | int max_gic_vcpus; | |
8d5c6b06 | 67 | |
50926d82 MZ |
68 | /* Only needed for the legacy KVM_CREATE_IRQCHIP */ |
69 | bool can_emulate_gicv2; | |
5a7a8426 | 70 | |
e7c48059 MZ |
71 | /* Hardware has GICv4? */ |
72 | bool has_gicv4; | |
73 | ||
5a7a8426 VM |
74 | /* GIC system register CPU interface */ |
75 | struct static_key_false gicv3_cpuif; | |
d017d7b0 VK |
76 | |
77 | u32 ich_vtr_el2; | |
8d5c6b06 MZ |
78 | }; |
79 | ||
50926d82 | 80 | extern struct vgic_global kvm_vgic_global_state; |
beee38b9 | 81 | |
50926d82 MZ |
82 | #define VGIC_V2_MAX_LRS (1 << 6) |
83 | #define VGIC_V3_MAX_LRS 16 | |
84 | #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr) | |
8d5c6b06 | 85 | |
50926d82 MZ |
86 | enum vgic_irq_config { |
87 | VGIC_CONFIG_EDGE = 0, | |
88 | VGIC_CONFIG_LEVEL | |
ca85f623 MZ |
89 | }; |
90 | ||
50926d82 | 91 | struct vgic_irq { |
8fa3adb8 | 92 | raw_spinlock_t irq_lock; /* Protects the content of the struct */ |
3802411d | 93 | struct list_head lpi_list; /* Used to link all LPIs together */ |
50926d82 MZ |
94 | struct list_head ap_list; |
95 | ||
96 | struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU | |
97 | * SPIs and LPIs: The VCPU whose ap_list | |
98 | * this is queued on. | |
99 | */ | |
100 | ||
101 | struct kvm_vcpu *target_vcpu; /* The VCPU that this interrupt should | |
102 | * be sent to, as a result of the | |
103 | * targets reg (v2) or the | |
104 | * affinity reg (v3). | |
105 | */ | |
106 | ||
107 | u32 intid; /* Guest visible INTID */ | |
50926d82 | 108 | bool line_level; /* Level only */ |
8694e4da CD |
109 | bool pending_latch; /* The pending latch state used to calculate |
110 | * the pending state for both level | |
111 | * and edge triggered IRQs. */ | |
50926d82 MZ |
112 | bool active; /* not used for LPIs */ |
113 | bool enabled; | |
114 | bool hw; /* Tied to HW IRQ */ | |
5dd4b924 | 115 | struct kref refcount; /* Used for LPIs */ |
50926d82 | 116 | u32 hwintid; /* HW INTID number */ |
47bbd31f | 117 | unsigned int host_irq; /* linux irq corresponding to hwintid */ |
50926d82 MZ |
118 | union { |
119 | u8 targets; /* GICv2 target VCPUs mask */ | |
120 | u32 mpidr; /* GICv3 target VCPU */ | |
121 | }; | |
122 | u8 source; /* GICv2 SGIs only */ | |
53692908 | 123 | u8 active_source; /* GICv2 SGIs only */ |
50926d82 | 124 | u8 priority; |
8df3c8f3 | 125 | u8 group; /* 0 == group 0, 1 == group 1 */ |
50926d82 | 126 | enum vgic_irq_config config; /* Level or edge */ |
c6ccd30e | 127 | |
b6909a65 CD |
128 | /* |
129 | * Callback function pointer to in-kernel devices that can tell us the | |
130 | * state of the input level of mapped level-triggered IRQ faster than | |
131 | * peaking into the physical GIC. | |
132 | * | |
133 | * Always called in non-preemptible section and the functions can use | |
134 | * kvm_arm_get_running_vcpu() to get the vcpu pointer for private | |
135 | * IRQs. | |
136 | */ | |
137 | bool (*get_input_level)(int vintid); | |
138 | ||
c6ccd30e CD |
139 | void *owner; /* Opaque pointer to reserve an interrupt |
140 | for in-kernel devices. */ | |
b26e5fda AP |
141 | }; |
142 | ||
50926d82 | 143 | struct vgic_register_region; |
59c5ab40 AP |
144 | struct vgic_its; |
145 | ||
146 | enum iodev_type { | |
147 | IODEV_CPUIF, | |
148 | IODEV_DIST, | |
149 | IODEV_REDIST, | |
150 | IODEV_ITS | |
151 | }; | |
50926d82 | 152 | |
6777f77f | 153 | struct vgic_io_device { |
50926d82 | 154 | gpa_t base_addr; |
59c5ab40 AP |
155 | union { |
156 | struct kvm_vcpu *redist_vcpu; | |
157 | struct vgic_its *its; | |
158 | }; | |
50926d82 | 159 | const struct vgic_register_region *regions; |
59c5ab40 | 160 | enum iodev_type iodev_type; |
50926d82 | 161 | int nr_regions; |
6777f77f AP |
162 | struct kvm_io_device dev; |
163 | }; | |
164 | ||
59c5ab40 AP |
165 | struct vgic_its { |
166 | /* The base address of the ITS control register frame */ | |
167 | gpa_t vgic_its_base; | |
168 | ||
169 | bool enabled; | |
170 | struct vgic_io_device iodev; | |
bb717644 | 171 | struct kvm_device *dev; |
424c3383 AP |
172 | |
173 | /* These registers correspond to GITS_BASER{0,1} */ | |
174 | u64 baser_device_table; | |
175 | u64 baser_coll_table; | |
176 | ||
177 | /* Protects the command queue */ | |
178 | struct mutex cmd_lock; | |
179 | u64 cbaser; | |
180 | u32 creadr; | |
181 | u32 cwriter; | |
182 | ||
71afe470 EA |
183 | /* migration ABI revision in use */ |
184 | u32 abi_rev; | |
185 | ||
424c3383 AP |
186 | /* Protects the device and collection lists */ |
187 | struct mutex its_lock; | |
188 | struct list_head device_list; | |
189 | struct list_head collection_list; | |
59c5ab40 AP |
190 | }; |
191 | ||
10f92c4c CD |
192 | struct vgic_state_iter; |
193 | ||
dbd9733a EA |
194 | struct vgic_redist_region { |
195 | u32 index; | |
196 | gpa_t base; | |
197 | u32 count; /* number of redistributors or 0 if single region */ | |
198 | u32 free_index; /* index of the next free redistributor */ | |
199 | struct list_head list; | |
200 | }; | |
201 | ||
1a89dd91 | 202 | struct vgic_dist { |
f982cf4e | 203 | bool in_kernel; |
01ac5e34 | 204 | bool ready; |
50926d82 | 205 | bool initialized; |
b47ef92a | 206 | |
59892136 AP |
207 | /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ |
208 | u32 vgic_model; | |
209 | ||
aa075b0f CD |
210 | /* Implementation revision as reported in the GICD_IIDR */ |
211 | u32 implementation_rev; | |
212 | ||
32f8777e CD |
213 | /* Userspace can write to GICv2 IGROUPR */ |
214 | bool v2_groups_user_writable; | |
215 | ||
0e4e82f1 AP |
216 | /* Do injected MSIs require an additional device ID? */ |
217 | bool msis_require_devid; | |
218 | ||
50926d82 | 219 | int nr_spis; |
c1bfb577 | 220 | |
50926d82 MZ |
221 | /* base addresses in guest physical address space: */ |
222 | gpa_t vgic_dist_base; /* distributor */ | |
a0675c25 | 223 | union { |
50926d82 MZ |
224 | /* either a GICv2 CPU interface */ |
225 | gpa_t vgic_cpu_base; | |
226 | /* or a number of GICv3 redistributor regions */ | |
dbd9733a | 227 | struct list_head rd_regions; |
a0675c25 | 228 | }; |
b47ef92a | 229 | |
50926d82 MZ |
230 | /* distributor enabled */ |
231 | bool enabled; | |
47a98b15 | 232 | |
50926d82 | 233 | struct vgic_irq *spis; |
b47ef92a | 234 | |
a9cf86f6 | 235 | struct vgic_io_device dist_iodev; |
0aa1de57 | 236 | |
1085fdc6 AP |
237 | bool has_its; |
238 | ||
0aa1de57 AP |
239 | /* |
240 | * Contains the attributes and gpa of the LPI configuration table. | |
241 | * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share | |
242 | * one address across all redistributors. | |
243 | * GICv3 spec: 6.1.2 "LPI Configuration tables" | |
244 | */ | |
245 | u64 propbaser; | |
3802411d AP |
246 | |
247 | /* Protects the lpi_list and the count value below. */ | |
fc3bc475 | 248 | raw_spinlock_t lpi_list_lock; |
3802411d AP |
249 | struct list_head lpi_list_head; |
250 | int lpi_list_count; | |
10f92c4c CD |
251 | |
252 | /* used by vgic-debug */ | |
253 | struct vgic_state_iter *iter; | |
74fe55dc MZ |
254 | |
255 | /* | |
256 | * GICv4 ITS per-VM data, containing the IRQ domain, the VPE | |
257 | * array, the property table pointer as well as allocation | |
258 | * data. This essentially ties the Linux IRQ core and ITS | |
259 | * together, and avoids leaking KVM's data structures anywhere | |
260 | * else. | |
261 | */ | |
262 | struct its_vm its_vm; | |
1a89dd91 MZ |
263 | }; |
264 | ||
eede821d MZ |
265 | struct vgic_v2_cpu_if { |
266 | u32 vgic_hcr; | |
267 | u32 vgic_vmcr; | |
eede821d | 268 | u32 vgic_apr; |
8f186d52 | 269 | u32 vgic_lr[VGIC_V2_MAX_LRS]; |
eede821d MZ |
270 | }; |
271 | ||
b2fb1c0d | 272 | struct vgic_v3_cpu_if { |
b2fb1c0d MZ |
273 | u32 vgic_hcr; |
274 | u32 vgic_vmcr; | |
2f5fa41a | 275 | u32 vgic_sre; /* Restored only, change ignored */ |
b2fb1c0d MZ |
276 | u32 vgic_ap0r[4]; |
277 | u32 vgic_ap1r[4]; | |
278 | u64 vgic_lr[VGIC_V3_MAX_LRS]; | |
74fe55dc MZ |
279 | |
280 | /* | |
281 | * GICv4 ITS per-VPE data, containing the doorbell IRQ, the | |
282 | * pending table pointer, the its_vm pointer and a few other | |
283 | * HW specific things. As for the its_vm structure, this is | |
284 | * linking the Linux IRQ subsystem and the ITS together. | |
285 | */ | |
286 | struct its_vpe its_vpe; | |
b2fb1c0d MZ |
287 | }; |
288 | ||
1a89dd91 | 289 | struct vgic_cpu { |
9d949dce | 290 | /* CPU vif control registers for world switch */ |
eede821d MZ |
291 | union { |
292 | struct vgic_v2_cpu_if vgic_v2; | |
b2fb1c0d | 293 | struct vgic_v3_cpu_if vgic_v3; |
eede821d | 294 | }; |
6c3d63c9 | 295 | |
50926d82 MZ |
296 | unsigned int used_lrs; |
297 | struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS]; | |
1a89dd91 | 298 | |
e08d8d29 | 299 | raw_spinlock_t ap_list_lock; /* Protects the ap_list */ |
9d949dce | 300 | |
50926d82 MZ |
301 | /* |
302 | * List of IRQs that this VCPU should consider because they are either | |
303 | * Active or Pending (hence the name; AP list), or because they recently | |
304 | * were one of the two and need to be migrated off this list to another | |
305 | * VCPU. | |
306 | */ | |
307 | struct list_head ap_list_head; | |
495dd859 | 308 | |
8f6cdc1c AP |
309 | /* |
310 | * Members below are used with GICv3 emulation only and represent | |
311 | * parts of the redistributor. | |
312 | */ | |
313 | struct vgic_io_device rd_iodev; | |
314 | struct vgic_io_device sgi_iodev; | |
dbd9733a | 315 | struct vgic_redist_region *rdreg; |
0aa1de57 AP |
316 | |
317 | /* Contains the attributes and gpa of the LPI pending tables. */ | |
318 | u64 pendbaser; | |
319 | ||
320 | bool lpis_enabled; | |
d017d7b0 VK |
321 | |
322 | /* Cache guest priority bits */ | |
323 | u32 num_pri_bits; | |
324 | ||
325 | /* Cache guest interrupt ID bits */ | |
326 | u32 num_id_bits; | |
50926d82 | 327 | }; |
1a89dd91 | 328 | |
fb5ee369 | 329 | extern struct static_key_false vgic_v2_cpuif_trap; |
59da1cbf | 330 | extern struct static_key_false vgic_v3_cpuif_trap; |
fb5ee369 | 331 | |
ce01e4e8 | 332 | int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write); |
6c3d63c9 | 333 | void kvm_vgic_early_init(struct kvm *kvm); |
1aab6f46 | 334 | int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu); |
59892136 | 335 | int kvm_vgic_create(struct kvm *kvm, u32 type); |
c1bfb577 | 336 | void kvm_vgic_destroy(struct kvm *kvm); |
c1bfb577 | 337 | void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu); |
50926d82 MZ |
338 | int kvm_vgic_map_resources(struct kvm *kvm); |
339 | int kvm_vgic_hyp_init(void); | |
5b0d2cc2 | 340 | void kvm_vgic_init_cpu_hardware(void); |
50926d82 MZ |
341 | |
342 | int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid, | |
cb3f0ad8 | 343 | bool level, void *owner); |
47bbd31f | 344 | int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq, |
b6909a65 | 345 | u32 vintid, bool (*get_input_level)(int vindid)); |
47bbd31f EA |
346 | int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid); |
347 | bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid); | |
1a89dd91 | 348 | |
50926d82 MZ |
349 | int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); |
350 | ||
328e5664 CD |
351 | void kvm_vgic_load(struct kvm_vcpu *vcpu); |
352 | void kvm_vgic_put(struct kvm_vcpu *vcpu); | |
353 | ||
f982cf4e | 354 | #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) |
50926d82 | 355 | #define vgic_initialized(k) ((k)->arch.vgic.initialized) |
c52edf5f | 356 | #define vgic_ready(k) ((k)->arch.vgic.ready) |
2defaff4 | 357 | #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \ |
50926d82 MZ |
358 | ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS)) |
359 | ||
360 | bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu); | |
361 | void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu); | |
362 | void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu); | |
413aa807 | 363 | void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid); |
9d949dce | 364 | |
6249f2a4 | 365 | void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1); |
8f186d52 | 366 | |
50926d82 MZ |
367 | /** |
368 | * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW | |
369 | * | |
370 | * The host's GIC naturally limits the maximum amount of VCPUs a guest | |
371 | * can use. | |
372 | */ | |
373 | static inline int kvm_vgic_get_max_vcpus(void) | |
374 | { | |
375 | return kvm_vgic_global_state.max_gic_vcpus; | |
376 | } | |
377 | ||
0e4e82f1 AP |
378 | int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi); |
379 | ||
180ae7b1 EA |
380 | /** |
381 | * kvm_vgic_setup_default_irq_routing: | |
382 | * Setup a default flat gsi routing table mapping all SPIs | |
383 | */ | |
384 | int kvm_vgic_setup_default_irq_routing(struct kvm *kvm); | |
385 | ||
c6ccd30e CD |
386 | int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner); |
387 | ||
196b1364 MZ |
388 | struct kvm_kernel_irq_routing_entry; |
389 | ||
390 | int kvm_vgic_v4_set_forwarding(struct kvm *kvm, int irq, | |
391 | struct kvm_kernel_irq_routing_entry *irq_entry); | |
392 | ||
393 | int kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int irq, | |
394 | struct kvm_kernel_irq_routing_entry *irq_entry); | |
395 | ||
df9ba959 MZ |
396 | void kvm_vgic_v4_enable_doorbell(struct kvm_vcpu *vcpu); |
397 | void kvm_vgic_v4_disable_doorbell(struct kvm_vcpu *vcpu); | |
398 | ||
50926d82 | 399 | #endif /* __KVM_ARM_VGIC_H */ |