[mirror_ubuntu-zesty-kernel.git] / include / kvm / arm_vgic.h

/*
 * Copyright (C) 2015, 2016 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __KVM_ARM_VGIC_H
#define __KVM_ARM_VGIC_H

#include <linux/kernel.h>
#include <linux/kvm.h>
#include <linux/irqreturn.h>
#include <linux/spinlock.h>
#include <linux/static_key.h>
#include <linux/types.h>
#include <kvm/iodev.h>
#include <linux/list.h>
#include <linux/jump_label.h>

#define VGIC_V3_MAX_CPUS	255
#define VGIC_V2_MAX_CPUS	8
#define VGIC_NR_IRQS_LEGACY     256
#define VGIC_NR_SGIS		16
#define VGIC_NR_PPIS		16
#define VGIC_NR_PRIVATE_IRQS	(VGIC_NR_SGIS + VGIC_NR_PPIS)
#define VGIC_MAX_PRIVATE	(VGIC_NR_PRIVATE_IRQS - 1)
#define VGIC_MAX_SPI		1019
#define VGIC_MAX_RESERVED	1023
#define VGIC_MIN_LPI		8192
#define KVM_IRQCHIP_NUM_PINS	(1020 - 32)

enum vgic_type {
	VGIC_V2,		/* Good ol' GICv2 */
	VGIC_V3,		/* New fancy GICv3 */
};

/* same for all guests, as depending only on the _host's_ GIC model */
struct vgic_global {
	/* type of the host GIC */
	enum vgic_type		type;

	/* Physical address of vgic virtual cpu interface */
	phys_addr_t		vcpu_base;

	/* GICV mapping */
	void __iomem		*vcpu_base_va;

	/* virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* Number of implemented list registers */
	int			nr_lr;

	/* Maintenance IRQ number */
	unsigned int		maint_irq;

	/* maximum number of VCPUs allowed (GICv2 limits us to 8) */
	int			max_gic_vcpus;

	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
	bool			can_emulate_gicv2;

	/* GIC system register CPU interface */
	struct static_key_false gicv3_cpuif;
};

extern struct vgic_global kvm_vgic_global_state;

#define VGIC_V2_MAX_LRS		(1 << 6)
#define VGIC_V3_MAX_LRS		16
#define VGIC_V3_LR_INDEX(lr)	(VGIC_V3_MAX_LRS - 1 - lr)

enum vgic_irq_config {
	VGIC_CONFIG_EDGE = 0,
	VGIC_CONFIG_LEVEL
};

struct vgic_irq {
	spinlock_t irq_lock;		/* Protects the content of the struct */
	struct list_head lpi_list;	/* Used to link all LPIs together */
	struct list_head ap_list;

	struct kvm_vcpu *vcpu;		/* SGIs and PPIs: The VCPU
					 * SPIs and LPIs: The VCPU whose ap_list
					 * this is queued on.
					 */

	struct kvm_vcpu *target_vcpu;	/* The VCPU that this interrupt should
					 * be sent to, as a result of the
					 * targets reg (v2) or the
					 * affinity reg (v3).
					 */

	u32 intid;			/* Guest visible INTID */
	bool pending;
	bool line_level;		/* Level only */
	bool soft_pending;		/* Level only */
	bool active;			/* not used for LPIs */
	bool enabled;
	bool hw;			/* Tied to HW IRQ */
	struct kref refcount;		/* Used for LPIs */
	u32 hwintid;			/* HW INTID number */
	union {
		u8 targets;			/* GICv2 target VCPUs mask */
		u32 mpidr;			/* GICv3 target VCPU */
	};
	u8 source;			/* GICv2 SGIs only */
	u8 priority;
	enum vgic_irq_config config;	/* Level or edge */
};

struct vgic_register_region;
struct vgic_its;

enum iodev_type {
	IODEV_CPUIF,
	IODEV_DIST,
	IODEV_REDIST,
	IODEV_ITS
};

struct vgic_io_device {
	gpa_t base_addr;
	union {
		struct kvm_vcpu *redist_vcpu;
		struct vgic_its *its;
	};
	const struct vgic_register_region *regions;
	enum iodev_type iodev_type;
	int nr_regions;
	struct kvm_io_device dev;
};

struct vgic_its {
	/* The base address of the ITS control register frame */
	gpa_t			vgic_its_base;

	bool			enabled;
	bool			initialized;
	struct vgic_io_device	iodev;
	struct kvm_device	*dev;

	/* These registers correspond to GITS_BASER{0,1} */
	u64			baser_device_table;
	u64			baser_coll_table;

	/* Protects the command queue */
	struct mutex		cmd_lock;
	u64			cbaser;
	u32			creadr;
	u32			cwriter;

	/* Protects the device and collection lists */
	struct mutex		its_lock;
	struct list_head	device_list;
	struct list_head	collection_list;
};

struct vgic_dist {
	bool			in_kernel;
	bool			ready;
	bool			initialized;

	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	u32			vgic_model;

	/* Do injected MSIs require an additional device ID? */
	bool			msis_require_devid;

	int			nr_spis;

	/* TODO: Consider moving to global state */
	/* Virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* base addresses in guest physical address space: */
	gpa_t			vgic_dist_base;		/* distributor */
	union {
		/* either a GICv2 CPU interface */
		gpa_t			vgic_cpu_base;
		/* or a number of GICv3 redistributor regions */
		gpa_t			vgic_redist_base;
	};

	/* distributor enabled */
	bool			enabled;

	struct vgic_irq		*spis;

	struct vgic_io_device	dist_iodev;

	bool			has_its;

	/*
	 * Contains the attributes and gpa of the LPI configuration table.
	 * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
	 * one address across all redistributors.
	 * GICv3 spec: 6.1.2 "LPI Configuration tables"
	 */
	u64			propbaser;

	/* Protects the lpi_list and the count value below. */
	spinlock_t		lpi_list_lock;
	struct list_head	lpi_list_head;
	int			lpi_list_count;
};

struct vgic_v2_cpu_if {
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_misr;	/* Saved only */
	u64		vgic_eisr;	/* Saved only */
	u64		vgic_elrsr;	/* Saved only */
	u32		vgic_apr;
	u32		vgic_lr[VGIC_V2_MAX_LRS];
};

struct vgic_v3_cpu_if {
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_sre;	/* Restored only, change ignored */
	u32		vgic_misr;	/* Saved only */
	u32		vgic_eisr;	/* Saved only */
	u32		vgic_elrsr;	/* Saved only */
	u32		vgic_ap0r[4];
	u32		vgic_ap1r[4];
	u64		vgic_lr[VGIC_V3_MAX_LRS];
};

struct vgic_cpu {
	/* CPU vif control registers for world switch */
	union {
		struct vgic_v2_cpu_if	vgic_v2;
		struct vgic_v3_cpu_if	vgic_v3;
	};

	unsigned int used_lrs;
	struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];

	spinlock_t ap_list_lock;	/* Protects the ap_list */

	/*
	 * List of IRQs that this VCPU should consider because they are either
	 * Active or Pending (hence the name; AP list), or because they recently
	 * were one of the two and need to be migrated off this list to another
	 * VCPU.
	 */
	struct list_head ap_list_head;

	u64 live_lrs;

	/*
	 * Members below are used with GICv3 emulation only and represent
	 * parts of the redistributor.
	 */
	struct vgic_io_device	rd_iodev;
	struct vgic_io_device	sgi_iodev;

	/* Contains the attributes and gpa of the LPI pending tables. */
	u64 pendbaser;

	bool lpis_enabled;
};

extern struct static_key_false vgic_v2_cpuif_trap;
extern struct static_key_false vgic_v3_cpuif_trap;

int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
void kvm_vgic_early_init(struct kvm *kvm);
int kvm_vgic_create(struct kvm *kvm, u32 type);
void kvm_vgic_destroy(struct kvm *kvm);
void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
int kvm_vgic_map_resources(struct kvm *kvm);
int kvm_vgic_hyp_init(void);

int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
			bool level);
int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int intid,
			       bool level);
int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq);
int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq);
bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq);

int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);

#define irqchip_in_kernel(k)	(!!((k)->arch.vgic.in_kernel))
#define vgic_initialized(k)	((k)->arch.vgic.initialized)
#define vgic_ready(k)		((k)->arch.vgic.ready)
#define vgic_valid_spi(k, i)	(((i) >= VGIC_NR_PRIVATE_IRQS) && \
			((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))

bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);

void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);

/**
 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
 *
 * The host's GIC naturally limits the maximum amount of VCPUs a guest
 * can use.
 */
static inline int kvm_vgic_get_max_vcpus(void)
{
	return kvm_vgic_global_state.max_gic_vcpus;
}

int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi);

/**
 * kvm_vgic_setup_default_irq_routing:
 * Setup a default flat gsi routing table mapping all SPIs
 */
int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);

#endif /* __KVM_ARM_VGIC_H */
Commit	Line	Data
1a89dd91	1	/*
50926d82	2	* Copyright (C) 2015, 2016 ARM Ltd.
1a89dd91 MZ	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
50926d82	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
1a89dd91	15	*/
50926d82 MZ	16	#ifndef __KVM_ARM_VGIC_H
50926d82 MZ	17	#define __KVM_ARM_VGIC_H
b18b5778	18
b47ef92a MZ	19	#include <linux/kernel.h>
b47ef92a MZ	20	#include <linux/kvm.h>
b47ef92a MZ	21	#include <linux/irqreturn.h>
b47ef92a MZ	22	#include <linux/spinlock.h>
fb5ee369	23	#include <linux/static_key.h>
b47ef92a	24	#include <linux/types.h>
6777f77f	25	#include <kvm/iodev.h>
424c3383	26	#include <linux/list.h>
5a7a8426	27	#include <linux/jump_label.h>
1a89dd91	28
50926d82 MZ	29	#define VGIC_V3_MAX_CPUS 255
	30	#define VGIC_V2_MAX_CPUS 8
	31	#define VGIC_NR_IRQS_LEGACY 256
b47ef92a MZ	32	#define VGIC_NR_SGIS 16
	33	#define VGIC_NR_PPIS 16
	34	#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
50926d82 MZ	35	#define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
	36	#define VGIC_MAX_SPI 1019
	37	#define VGIC_MAX_RESERVED 1023
	38	#define VGIC_MIN_LPI 8192
180ae7b1	39	#define KVM_IRQCHIP_NUM_PINS (1020 - 32)
8f186d52	40
50926d82 MZ	41	enum vgic_type {
	42	VGIC_V2, /* Good ol' GICv2 */
	43	VGIC_V3, /* New fancy GICv3 */
	44	};
b47ef92a	45
50926d82 MZ	46	/* same for all guests, as depending only on the _host's_ GIC model */
	47	struct vgic_global {
	48	/* type of the host GIC */
	49	enum vgic_type type;
b47ef92a	50
50926d82 MZ	51	/* Physical address of vgic virtual cpu interface */
50926d82 MZ	52	phys_addr_t vcpu_base;
b47ef92a	53
bf8feb39 MZ	54	/* GICV mapping */
	55	void __iomem *vcpu_base_va;
	56
50926d82 MZ	57	/* virtual control interface mapping */
50926d82 MZ	58	void __iomem *vctrl_base;
b47ef92a	59
50926d82 MZ	60	/* Number of implemented list registers */
50926d82 MZ	61	int nr_lr;
8d5c6b06	62
50926d82 MZ	63	/* Maintenance IRQ number */
50926d82 MZ	64	unsigned int maint_irq;
1a9b1305	65
50926d82 MZ	66	/* maximum number of VCPUs allowed (GICv2 limits us to 8) */
50926d82 MZ	67	int max_gic_vcpus;
8d5c6b06	68
50926d82 MZ	69	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
50926d82 MZ	70	bool can_emulate_gicv2;
5a7a8426 VM	71
	72	/* GIC system register CPU interface */
	73	struct static_key_false gicv3_cpuif;
8d5c6b06 MZ	74	};
8d5c6b06 MZ	75
50926d82	76	extern struct vgic_global kvm_vgic_global_state;
beee38b9	77
50926d82 MZ	78	#define VGIC_V2_MAX_LRS (1 << 6)
	79	#define VGIC_V3_MAX_LRS 16
	80	#define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
8d5c6b06	81
50926d82 MZ	82	enum vgic_irq_config {
	83	VGIC_CONFIG_EDGE = 0,
	84	VGIC_CONFIG_LEVEL
ca85f623 MZ	85	};
ca85f623 MZ	86
50926d82 MZ	87	struct vgic_irq {
50926d82 MZ	88	spinlock_t irq_lock; /* Protects the content of the struct */
3802411d	89	struct list_head lpi_list; /* Used to link all LPIs together */
50926d82 MZ	90	struct list_head ap_list;
	91
	92	struct kvm_vcpu vcpu; / SGIs and PPIs: The VCPU
	93	* SPIs and LPIs: The VCPU whose ap_list
	94	* this is queued on.
	95	*/
	96
	97	struct kvm_vcpu target_vcpu; / The VCPU that this interrupt should
	98	* be sent to, as a result of the
	99	* targets reg (v2) or the
	100	* affinity reg (v3).
	101	*/
	102
	103	u32 intid; /* Guest visible INTID */
	104	bool pending;
	105	bool line_level; /* Level only */
	106	bool soft_pending; /* Level only */
	107	bool active; /* not used for LPIs */
	108	bool enabled;
	109	bool hw; /* Tied to HW IRQ */
5dd4b924	110	struct kref refcount; /* Used for LPIs */
50926d82 MZ	111	u32 hwintid; /* HW INTID number */
	112	union {
	113	u8 targets; /* GICv2 target VCPUs mask */
	114	u32 mpidr; /* GICv3 target VCPU */
	115	};
	116	u8 source; /* GICv2 SGIs only */
	117	u8 priority;
	118	enum vgic_irq_config config; /* Level or edge */
b26e5fda AP	119	};
b26e5fda AP	120
50926d82	121	struct vgic_register_region;
59c5ab40 AP	122	struct vgic_its;
	123
	124	enum iodev_type {
	125	IODEV_CPUIF,
	126	IODEV_DIST,
	127	IODEV_REDIST,
	128	IODEV_ITS
	129	};
50926d82	130
6777f77f	131	struct vgic_io_device {
50926d82	132	gpa_t base_addr;
59c5ab40 AP	133	union {
	134	struct kvm_vcpu *redist_vcpu;
	135	struct vgic_its *its;
	136	};
50926d82	137	const struct vgic_register_region *regions;
59c5ab40	138	enum iodev_type iodev_type;
50926d82	139	int nr_regions;
6777f77f AP	140	struct kvm_io_device dev;
	141	};
	142
59c5ab40 AP	143	struct vgic_its {
	144	/* The base address of the ITS control register frame */
	145	gpa_t vgic_its_base;
	146
	147	bool enabled;
1085fdc6	148	bool initialized;
59c5ab40	149	struct vgic_io_device iodev;
bb717644	150	struct kvm_device *dev;
424c3383 AP	151
	152	/* These registers correspond to GITS_BASER{0,1} */
	153	u64 baser_device_table;
	154	u64 baser_coll_table;
	155
	156	/* Protects the command queue */
	157	struct mutex cmd_lock;
	158	u64 cbaser;
	159	u32 creadr;
	160	u32 cwriter;
	161
	162	/* Protects the device and collection lists */
	163	struct mutex its_lock;
	164	struct list_head device_list;
	165	struct list_head collection_list;
59c5ab40 AP	166	};
59c5ab40 AP	167
1a89dd91	168	struct vgic_dist {
f982cf4e	169	bool in_kernel;
01ac5e34	170	bool ready;
50926d82	171	bool initialized;
b47ef92a	172
59892136 AP	173	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	174	u32 vgic_model;
	175
0e4e82f1 AP	176	/* Do injected MSIs require an additional device ID? */
	177	bool msis_require_devid;
	178
50926d82	179	int nr_spis;
c1bfb577	180
50926d82	181	/* TODO: Consider moving to global state */
b47ef92a MZ	182	/* Virtual control interface mapping */
	183	void __iomem *vctrl_base;
	184
50926d82 MZ	185	/* base addresses in guest physical address space: */
50926d82 MZ	186	gpa_t vgic_dist_base; /* distributor */
a0675c25	187	union {
50926d82 MZ	188	/* either a GICv2 CPU interface */
	189	gpa_t vgic_cpu_base;
	190	/* or a number of GICv3 redistributor regions */
	191	gpa_t vgic_redist_base;
a0675c25	192	};
b47ef92a	193
50926d82 MZ	194	/* distributor enabled */
50926d82 MZ	195	bool enabled;
47a98b15	196
50926d82	197	struct vgic_irq *spis;
b47ef92a	198
a9cf86f6	199	struct vgic_io_device dist_iodev;
0aa1de57	200
1085fdc6 AP	201	bool has_its;
1085fdc6 AP	202
0aa1de57 AP	203	/*
	204	* Contains the attributes and gpa of the LPI configuration table.
	205	* Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
	206	* one address across all redistributors.
	207	* GICv3 spec: 6.1.2 "LPI Configuration tables"
	208	*/
	209	u64 propbaser;
3802411d AP	210
	211	/* Protects the lpi_list and the count value below. */
	212	spinlock_t lpi_list_lock;
	213	struct list_head lpi_list_head;
	214	int lpi_list_count;
1a89dd91 MZ	215	};
1a89dd91 MZ	216
eede821d MZ	217	struct vgic_v2_cpu_if {
	218	u32 vgic_hcr;
	219	u32 vgic_vmcr;
	220	u32 vgic_misr; /* Saved only */
2df36a5d CD	221	u64 vgic_eisr; /* Saved only */
2df36a5d CD	222	u64 vgic_elrsr; /* Saved only */
eede821d	223	u32 vgic_apr;
8f186d52	224	u32 vgic_lr[VGIC_V2_MAX_LRS];
eede821d MZ	225	};
eede821d MZ	226
b2fb1c0d	227	struct vgic_v3_cpu_if {
b2fb1c0d MZ	228	u32 vgic_hcr;
b2fb1c0d MZ	229	u32 vgic_vmcr;
2f5fa41a	230	u32 vgic_sre; /* Restored only, change ignored */
b2fb1c0d MZ	231	u32 vgic_misr; /* Saved only */
	232	u32 vgic_eisr; /* Saved only */
	233	u32 vgic_elrsr; /* Saved only */
	234	u32 vgic_ap0r[4];
	235	u32 vgic_ap1r[4];
	236	u64 vgic_lr[VGIC_V3_MAX_LRS];
b2fb1c0d MZ	237	};
b2fb1c0d MZ	238
1a89dd91	239	struct vgic_cpu {
9d949dce	240	/* CPU vif control registers for world switch */
eede821d MZ	241	union {
eede821d MZ	242	struct vgic_v2_cpu_if vgic_v2;
b2fb1c0d	243	struct vgic_v3_cpu_if vgic_v3;
eede821d	244	};
6c3d63c9	245
50926d82 MZ	246	unsigned int used_lrs;
50926d82 MZ	247	struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
1a89dd91	248
50926d82	249	spinlock_t ap_list_lock; /* Protects the ap_list */
9d949dce	250
50926d82 MZ	251	/*
	252	* List of IRQs that this VCPU should consider because they are either
	253	* Active or Pending (hence the name; AP list), or because they recently
	254	* were one of the two and need to be migrated off this list to another
	255	* VCPU.
	256	*/
	257	struct list_head ap_list_head;
495dd859	258
50926d82	259	u64 live_lrs;
8f6cdc1c AP	260
	261	/*
	262	* Members below are used with GICv3 emulation only and represent
	263	* parts of the redistributor.
	264	*/
	265	struct vgic_io_device rd_iodev;
	266	struct vgic_io_device sgi_iodev;
0aa1de57 AP	267
	268	/* Contains the attributes and gpa of the LPI pending tables. */
	269	u64 pendbaser;
	270
	271	bool lpis_enabled;
50926d82	272	};
1a89dd91	273
fb5ee369	274	extern struct static_key_false vgic_v2_cpuif_trap;
0c94a05f	275	extern struct static_key_false vgic_v3_cpuif_trap;
fb5ee369	276
ce01e4e8	277	int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write);
6c3d63c9	278	void kvm_vgic_early_init(struct kvm *kvm);
59892136	279	int kvm_vgic_create(struct kvm *kvm, u32 type);
c1bfb577	280	void kvm_vgic_destroy(struct kvm *kvm);
6c3d63c9	281	void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
c1bfb577	282	void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
50926d82 MZ	283	int kvm_vgic_map_resources(struct kvm *kvm);
	284	int kvm_vgic_hyp_init(void);
	285
	286	int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
5863c2ce	287	bool level);
50926d82 MZ	288	int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int intid,
	289	bool level);
	290	int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq);
63306c28	291	int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq);
e262f419	292	bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq);
1a89dd91	293
50926d82 MZ	294	int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
50926d82 MZ	295
f982cf4e	296	#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
50926d82	297	#define vgic_initialized(k) ((k)->arch.vgic.initialized)
c52edf5f	298	#define vgic_ready(k) ((k)->arch.vgic.ready)
2defaff4	299	#define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \
50926d82 MZ	300	((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
	301
	302	bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
	303	void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
	304	void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
9d949dce	305
50926d82	306	void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
8f186d52	307
50926d82 MZ	308	/**
	309	* kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
	310	*
	311	* The host's GIC naturally limits the maximum amount of VCPUs a guest
	312	* can use.
	313	*/
	314	static inline int kvm_vgic_get_max_vcpus(void)
	315	{
	316	return kvm_vgic_global_state.max_gic_vcpus;
	317	}
	318
0e4e82f1 AP	319	int kvm_send_userspace_msi(struct kvm kvm, struct kvm_msi msi);
0e4e82f1 AP	320
180ae7b1 EA	321	/**
	322	* kvm_vgic_setup_default_irq_routing:
	323	* Setup a default flat gsi routing table mapping all SPIs
	324	*/
	325	int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);
	326
50926d82	327	#endif /* __KVM_ARM_VGIC_H */