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1a89dd91 | 1 | /* |
50926d82 | 2 | * Copyright (C) 2015, 2016 ARM Ltd. |
1a89dd91 MZ |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
50926d82 | 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
1a89dd91 | 15 | */ |
50926d82 MZ |
16 | #ifndef __KVM_ARM_VGIC_H |
17 | #define __KVM_ARM_VGIC_H | |
b18b5778 | 18 | |
b47ef92a MZ |
19 | #include <linux/kernel.h> |
20 | #include <linux/kvm.h> | |
b47ef92a MZ |
21 | #include <linux/irqreturn.h> |
22 | #include <linux/spinlock.h> | |
fb5ee369 | 23 | #include <linux/static_key.h> |
b47ef92a | 24 | #include <linux/types.h> |
6777f77f | 25 | #include <kvm/iodev.h> |
424c3383 | 26 | #include <linux/list.h> |
5a7a8426 | 27 | #include <linux/jump_label.h> |
1a89dd91 | 28 | |
50926d82 MZ |
29 | #define VGIC_V3_MAX_CPUS 255 |
30 | #define VGIC_V2_MAX_CPUS 8 | |
31 | #define VGIC_NR_IRQS_LEGACY 256 | |
b47ef92a MZ |
32 | #define VGIC_NR_SGIS 16 |
33 | #define VGIC_NR_PPIS 16 | |
34 | #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) | |
50926d82 MZ |
35 | #define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1) |
36 | #define VGIC_MAX_SPI 1019 | |
37 | #define VGIC_MAX_RESERVED 1023 | |
38 | #define VGIC_MIN_LPI 8192 | |
180ae7b1 | 39 | #define KVM_IRQCHIP_NUM_PINS (1020 - 32) |
8f186d52 | 40 | |
50926d82 MZ |
41 | enum vgic_type { |
42 | VGIC_V2, /* Good ol' GICv2 */ | |
43 | VGIC_V3, /* New fancy GICv3 */ | |
44 | }; | |
b47ef92a | 45 | |
50926d82 MZ |
46 | /* same for all guests, as depending only on the _host's_ GIC model */ |
47 | struct vgic_global { | |
48 | /* type of the host GIC */ | |
49 | enum vgic_type type; | |
b47ef92a | 50 | |
50926d82 MZ |
51 | /* Physical address of vgic virtual cpu interface */ |
52 | phys_addr_t vcpu_base; | |
b47ef92a | 53 | |
bf8feb39 MZ |
54 | /* GICV mapping */ |
55 | void __iomem *vcpu_base_va; | |
56 | ||
50926d82 MZ |
57 | /* virtual control interface mapping */ |
58 | void __iomem *vctrl_base; | |
b47ef92a | 59 | |
50926d82 MZ |
60 | /* Number of implemented list registers */ |
61 | int nr_lr; | |
8d5c6b06 | 62 | |
50926d82 MZ |
63 | /* Maintenance IRQ number */ |
64 | unsigned int maint_irq; | |
1a9b1305 | 65 | |
50926d82 MZ |
66 | /* maximum number of VCPUs allowed (GICv2 limits us to 8) */ |
67 | int max_gic_vcpus; | |
8d5c6b06 | 68 | |
50926d82 MZ |
69 | /* Only needed for the legacy KVM_CREATE_IRQCHIP */ |
70 | bool can_emulate_gicv2; | |
5a7a8426 VM |
71 | |
72 | /* GIC system register CPU interface */ | |
73 | struct static_key_false gicv3_cpuif; | |
d017d7b0 VK |
74 | |
75 | u32 ich_vtr_el2; | |
8d5c6b06 MZ |
76 | }; |
77 | ||
50926d82 | 78 | extern struct vgic_global kvm_vgic_global_state; |
beee38b9 | 79 | |
50926d82 MZ |
80 | #define VGIC_V2_MAX_LRS (1 << 6) |
81 | #define VGIC_V3_MAX_LRS 16 | |
82 | #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr) | |
8d5c6b06 | 83 | |
50926d82 MZ |
84 | enum vgic_irq_config { |
85 | VGIC_CONFIG_EDGE = 0, | |
86 | VGIC_CONFIG_LEVEL | |
ca85f623 MZ |
87 | }; |
88 | ||
50926d82 MZ |
89 | struct vgic_irq { |
90 | spinlock_t irq_lock; /* Protects the content of the struct */ | |
3802411d | 91 | struct list_head lpi_list; /* Used to link all LPIs together */ |
50926d82 MZ |
92 | struct list_head ap_list; |
93 | ||
94 | struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU | |
95 | * SPIs and LPIs: The VCPU whose ap_list | |
96 | * this is queued on. | |
97 | */ | |
98 | ||
99 | struct kvm_vcpu *target_vcpu; /* The VCPU that this interrupt should | |
100 | * be sent to, as a result of the | |
101 | * targets reg (v2) or the | |
102 | * affinity reg (v3). | |
103 | */ | |
104 | ||
105 | u32 intid; /* Guest visible INTID */ | |
50926d82 | 106 | bool line_level; /* Level only */ |
8694e4da CD |
107 | bool pending_latch; /* The pending latch state used to calculate |
108 | * the pending state for both level | |
109 | * and edge triggered IRQs. */ | |
50926d82 MZ |
110 | bool active; /* not used for LPIs */ |
111 | bool enabled; | |
112 | bool hw; /* Tied to HW IRQ */ | |
5dd4b924 | 113 | struct kref refcount; /* Used for LPIs */ |
50926d82 MZ |
114 | u32 hwintid; /* HW INTID number */ |
115 | union { | |
116 | u8 targets; /* GICv2 target VCPUs mask */ | |
117 | u32 mpidr; /* GICv3 target VCPU */ | |
118 | }; | |
119 | u8 source; /* GICv2 SGIs only */ | |
120 | u8 priority; | |
121 | enum vgic_irq_config config; /* Level or edge */ | |
b26e5fda AP |
122 | }; |
123 | ||
50926d82 | 124 | struct vgic_register_region; |
59c5ab40 AP |
125 | struct vgic_its; |
126 | ||
127 | enum iodev_type { | |
128 | IODEV_CPUIF, | |
129 | IODEV_DIST, | |
130 | IODEV_REDIST, | |
131 | IODEV_ITS | |
132 | }; | |
50926d82 | 133 | |
6777f77f | 134 | struct vgic_io_device { |
50926d82 | 135 | gpa_t base_addr; |
59c5ab40 AP |
136 | union { |
137 | struct kvm_vcpu *redist_vcpu; | |
138 | struct vgic_its *its; | |
139 | }; | |
50926d82 | 140 | const struct vgic_register_region *regions; |
59c5ab40 | 141 | enum iodev_type iodev_type; |
50926d82 | 142 | int nr_regions; |
6777f77f AP |
143 | struct kvm_io_device dev; |
144 | }; | |
145 | ||
59c5ab40 AP |
146 | struct vgic_its { |
147 | /* The base address of the ITS control register frame */ | |
148 | gpa_t vgic_its_base; | |
149 | ||
150 | bool enabled; | |
151 | struct vgic_io_device iodev; | |
bb717644 | 152 | struct kvm_device *dev; |
424c3383 AP |
153 | |
154 | /* These registers correspond to GITS_BASER{0,1} */ | |
155 | u64 baser_device_table; | |
156 | u64 baser_coll_table; | |
157 | ||
158 | /* Protects the command queue */ | |
159 | struct mutex cmd_lock; | |
160 | u64 cbaser; | |
161 | u32 creadr; | |
162 | u32 cwriter; | |
163 | ||
71afe470 EA |
164 | /* migration ABI revision in use */ |
165 | u32 abi_rev; | |
166 | ||
424c3383 AP |
167 | /* Protects the device and collection lists */ |
168 | struct mutex its_lock; | |
169 | struct list_head device_list; | |
170 | struct list_head collection_list; | |
59c5ab40 AP |
171 | }; |
172 | ||
10f92c4c CD |
173 | struct vgic_state_iter; |
174 | ||
1a89dd91 | 175 | struct vgic_dist { |
f982cf4e | 176 | bool in_kernel; |
01ac5e34 | 177 | bool ready; |
50926d82 | 178 | bool initialized; |
b47ef92a | 179 | |
59892136 AP |
180 | /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ |
181 | u32 vgic_model; | |
182 | ||
0e4e82f1 AP |
183 | /* Do injected MSIs require an additional device ID? */ |
184 | bool msis_require_devid; | |
185 | ||
50926d82 | 186 | int nr_spis; |
c1bfb577 | 187 | |
50926d82 | 188 | /* TODO: Consider moving to global state */ |
b47ef92a MZ |
189 | /* Virtual control interface mapping */ |
190 | void __iomem *vctrl_base; | |
191 | ||
50926d82 MZ |
192 | /* base addresses in guest physical address space: */ |
193 | gpa_t vgic_dist_base; /* distributor */ | |
a0675c25 | 194 | union { |
50926d82 MZ |
195 | /* either a GICv2 CPU interface */ |
196 | gpa_t vgic_cpu_base; | |
197 | /* or a number of GICv3 redistributor regions */ | |
198 | gpa_t vgic_redist_base; | |
a0675c25 | 199 | }; |
b47ef92a | 200 | |
50926d82 MZ |
201 | /* distributor enabled */ |
202 | bool enabled; | |
47a98b15 | 203 | |
50926d82 | 204 | struct vgic_irq *spis; |
b47ef92a | 205 | |
a9cf86f6 | 206 | struct vgic_io_device dist_iodev; |
0aa1de57 | 207 | |
1085fdc6 AP |
208 | bool has_its; |
209 | ||
0aa1de57 AP |
210 | /* |
211 | * Contains the attributes and gpa of the LPI configuration table. | |
212 | * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share | |
213 | * one address across all redistributors. | |
214 | * GICv3 spec: 6.1.2 "LPI Configuration tables" | |
215 | */ | |
216 | u64 propbaser; | |
3802411d AP |
217 | |
218 | /* Protects the lpi_list and the count value below. */ | |
219 | spinlock_t lpi_list_lock; | |
220 | struct list_head lpi_list_head; | |
221 | int lpi_list_count; | |
10f92c4c CD |
222 | |
223 | /* used by vgic-debug */ | |
224 | struct vgic_state_iter *iter; | |
1a89dd91 MZ |
225 | }; |
226 | ||
eede821d MZ |
227 | struct vgic_v2_cpu_if { |
228 | u32 vgic_hcr; | |
229 | u32 vgic_vmcr; | |
2df36a5d | 230 | u64 vgic_elrsr; /* Saved only */ |
eede821d | 231 | u32 vgic_apr; |
8f186d52 | 232 | u32 vgic_lr[VGIC_V2_MAX_LRS]; |
eede821d MZ |
233 | }; |
234 | ||
b2fb1c0d | 235 | struct vgic_v3_cpu_if { |
b2fb1c0d MZ |
236 | u32 vgic_hcr; |
237 | u32 vgic_vmcr; | |
2f5fa41a | 238 | u32 vgic_sre; /* Restored only, change ignored */ |
b2fb1c0d MZ |
239 | u32 vgic_elrsr; /* Saved only */ |
240 | u32 vgic_ap0r[4]; | |
241 | u32 vgic_ap1r[4]; | |
242 | u64 vgic_lr[VGIC_V3_MAX_LRS]; | |
b2fb1c0d MZ |
243 | }; |
244 | ||
1a89dd91 | 245 | struct vgic_cpu { |
9d949dce | 246 | /* CPU vif control registers for world switch */ |
eede821d MZ |
247 | union { |
248 | struct vgic_v2_cpu_if vgic_v2; | |
b2fb1c0d | 249 | struct vgic_v3_cpu_if vgic_v3; |
eede821d | 250 | }; |
6c3d63c9 | 251 | |
50926d82 MZ |
252 | unsigned int used_lrs; |
253 | struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS]; | |
1a89dd91 | 254 | |
50926d82 | 255 | spinlock_t ap_list_lock; /* Protects the ap_list */ |
9d949dce | 256 | |
50926d82 MZ |
257 | /* |
258 | * List of IRQs that this VCPU should consider because they are either | |
259 | * Active or Pending (hence the name; AP list), or because they recently | |
260 | * were one of the two and need to be migrated off this list to another | |
261 | * VCPU. | |
262 | */ | |
263 | struct list_head ap_list_head; | |
495dd859 | 264 | |
8f6cdc1c AP |
265 | /* |
266 | * Members below are used with GICv3 emulation only and represent | |
267 | * parts of the redistributor. | |
268 | */ | |
269 | struct vgic_io_device rd_iodev; | |
270 | struct vgic_io_device sgi_iodev; | |
0aa1de57 AP |
271 | |
272 | /* Contains the attributes and gpa of the LPI pending tables. */ | |
273 | u64 pendbaser; | |
274 | ||
275 | bool lpis_enabled; | |
d017d7b0 VK |
276 | |
277 | /* Cache guest priority bits */ | |
278 | u32 num_pri_bits; | |
279 | ||
280 | /* Cache guest interrupt ID bits */ | |
281 | u32 num_id_bits; | |
50926d82 | 282 | }; |
1a89dd91 | 283 | |
fb5ee369 MZ |
284 | extern struct static_key_false vgic_v2_cpuif_trap; |
285 | ||
ce01e4e8 | 286 | int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write); |
6c3d63c9 | 287 | void kvm_vgic_early_init(struct kvm *kvm); |
1aab6f46 | 288 | int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu); |
59892136 | 289 | int kvm_vgic_create(struct kvm *kvm, u32 type); |
c1bfb577 | 290 | void kvm_vgic_destroy(struct kvm *kvm); |
6c3d63c9 | 291 | void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu); |
c1bfb577 | 292 | void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu); |
50926d82 MZ |
293 | int kvm_vgic_map_resources(struct kvm *kvm); |
294 | int kvm_vgic_hyp_init(void); | |
295 | ||
296 | int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid, | |
5863c2ce | 297 | bool level); |
50926d82 MZ |
298 | int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int intid, |
299 | bool level); | |
300 | int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq); | |
63306c28 | 301 | int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq); |
e262f419 | 302 | bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq); |
1a89dd91 | 303 | |
50926d82 MZ |
304 | int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); |
305 | ||
328e5664 CD |
306 | void kvm_vgic_load(struct kvm_vcpu *vcpu); |
307 | void kvm_vgic_put(struct kvm_vcpu *vcpu); | |
308 | ||
f982cf4e | 309 | #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) |
50926d82 | 310 | #define vgic_initialized(k) ((k)->arch.vgic.initialized) |
c52edf5f | 311 | #define vgic_ready(k) ((k)->arch.vgic.ready) |
2defaff4 | 312 | #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \ |
50926d82 MZ |
313 | ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS)) |
314 | ||
315 | bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu); | |
316 | void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu); | |
317 | void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu); | |
9d949dce | 318 | |
50926d82 | 319 | void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg); |
8f186d52 | 320 | |
50926d82 MZ |
321 | /** |
322 | * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW | |
323 | * | |
324 | * The host's GIC naturally limits the maximum amount of VCPUs a guest | |
325 | * can use. | |
326 | */ | |
327 | static inline int kvm_vgic_get_max_vcpus(void) | |
328 | { | |
329 | return kvm_vgic_global_state.max_gic_vcpus; | |
330 | } | |
331 | ||
0e4e82f1 AP |
332 | int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi); |
333 | ||
180ae7b1 EA |
334 | /** |
335 | * kvm_vgic_setup_default_irq_routing: | |
336 | * Setup a default flat gsi routing table mapping all SPIs | |
337 | */ | |
338 | int kvm_vgic_setup_default_irq_routing(struct kvm *kvm); | |
339 | ||
50926d82 | 340 | #endif /* __KVM_ARM_VGIC_H */ |