[mirror_ubuntu-bionic-kernel.git] / include / kvm / arm_vgic.h

/*
 * Copyright (C) 2012 ARM Ltd.
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */

#ifndef __ASM_ARM_KVM_VGIC_H
#define __ASM_ARM_KVM_VGIC_H

#include <linux/kernel.h>
#include <linux/kvm.h>
#include <linux/irqreturn.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/irqchip/arm-gic.h>

#define VGIC_NR_IRQS		256
#define VGIC_NR_SGIS		16
#define VGIC_NR_PPIS		16
#define VGIC_NR_PRIVATE_IRQS	(VGIC_NR_SGIS + VGIC_NR_PPIS)
#define VGIC_NR_SHARED_IRQS	(VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
#define VGIC_MAX_CPUS		KVM_MAX_VCPUS
#define VGIC_MAX_LRS		(1 << 6)

/* Sanity checks... */
#if (VGIC_MAX_CPUS > 8)
#error	Invalid number of CPU interfaces
#endif

#if (VGIC_NR_IRQS & 31)
#error "VGIC_NR_IRQS must be a multiple of 32"
#endif

#if (VGIC_NR_IRQS > 1024)
#error "VGIC_NR_IRQS must be <= 1024"
#endif

/*
 * The GIC distributor registers describing interrupts have two parts:
 * - 32 per-CPU interrupts (SGI + PPI)
 * - a bunch of shared interrupts (SPI)
 */
struct vgic_bitmap {
	union {
		u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
		DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
	} percpu[VGIC_MAX_CPUS];
	union {
		u32 reg[VGIC_NR_SHARED_IRQS / 32];
		DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
	} shared;
};

struct vgic_bytemap {
	u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
	u32 shared[VGIC_NR_SHARED_IRQS  / 4];
};

struct kvm_vcpu;

#define LR_STATE_PENDING	(1 << 0)
#define LR_STATE_ACTIVE		(1 << 1)
#define LR_STATE_MASK		(3 << 0)
#define LR_EOI_INT		(1 << 2)

struct vgic_lr {
	u16	irq;
	u8	source;
	u8	state;
};

struct vgic_ops {
	struct vgic_lr	(*get_lr)(const struct kvm_vcpu *, int);
	void	(*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
	void	(*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr);
	u64	(*get_elrsr)(const struct kvm_vcpu *vcpu);
	u64	(*get_eisr)(const struct kvm_vcpu *vcpu);
	u32	(*get_interrupt_status)(const struct kvm_vcpu *vcpu);
	void	(*enable_underflow)(struct kvm_vcpu *vcpu);
	void	(*disable_underflow)(struct kvm_vcpu *vcpu);
};

struct vgic_dist {
#ifdef CONFIG_KVM_ARM_VGIC
	spinlock_t		lock;
	bool			ready;

	/* Virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* Distributor and vcpu interface mapping in the guest */
	phys_addr_t		vgic_dist_base;
	phys_addr_t		vgic_cpu_base;

	/* Distributor enabled */
	u32			enabled;

	/* Interrupt enabled (one bit per IRQ) */
	struct vgic_bitmap	irq_enabled;

	/* Interrupt 'pin' level */
	struct vgic_bitmap	irq_state;

	/* Level-triggered interrupt in progress */
	struct vgic_bitmap	irq_active;

	/* Interrupt priority. Not used yet. */
	struct vgic_bytemap	irq_priority;

	/* Level/edge triggered */
	struct vgic_bitmap	irq_cfg;

	/* Source CPU per SGI and target CPU */
	u8			irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];

	/* Target CPU for each IRQ */
	u8			irq_spi_cpu[VGIC_NR_SHARED_IRQS];
	struct vgic_bitmap	irq_spi_target[VGIC_MAX_CPUS];

	/* Bitmap indicating which CPU has something pending */
	unsigned long		irq_pending_on_cpu;
#endif
};

struct vgic_v2_cpu_if {
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_misr;	/* Saved only */
	u32		vgic_eisr[2];	/* Saved only */
	u32		vgic_elrsr[2];	/* Saved only */
	u32		vgic_apr;
	u32		vgic_lr[VGIC_MAX_LRS];
};

struct vgic_cpu {
#ifdef CONFIG_KVM_ARM_VGIC
	/* per IRQ to LR mapping */
	u8		vgic_irq_lr_map[VGIC_NR_IRQS];

	/* Pending interrupts on this VCPU */
	DECLARE_BITMAP(	pending_percpu, VGIC_NR_PRIVATE_IRQS);
	DECLARE_BITMAP(	pending_shared, VGIC_NR_SHARED_IRQS);

	/* Bitmap of used/free list registers */
	DECLARE_BITMAP(	lr_used, VGIC_MAX_LRS);

	/* Number of list registers on this CPU */
	int		nr_lr;

	/* CPU vif control registers for world switch */
	union {
		struct vgic_v2_cpu_if	vgic_v2;
	};
#endif
};

#define LR_EMPTY	0xff

#define INT_STATUS_EOI		(1 << 0)
#define INT_STATUS_UNDERFLOW	(1 << 1)

struct kvm;
struct kvm_vcpu;
struct kvm_run;
struct kvm_exit_mmio;

#ifdef CONFIG_KVM_ARM_VGIC
int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
int kvm_vgic_hyp_init(void);
int kvm_vgic_init(struct kvm *kvm);
int kvm_vgic_create(struct kvm *kvm);
int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
			bool level);
int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
		      struct kvm_exit_mmio *mmio);

#define irqchip_in_kernel(k)	(!!((k)->arch.vgic.vctrl_base))
#define vgic_initialized(k)	((k)->arch.vgic.ready)

#else
static inline int kvm_vgic_hyp_init(void)
{
	return 0;
}

static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
{
	return 0;
}

static inline int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
{
	return -ENXIO;
}

static inline int kvm_vgic_init(struct kvm *kvm)
{
	return 0;
}

static inline int kvm_vgic_create(struct kvm *kvm)
{
	return 0;
}

static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
{
	return 0;
}

static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}

static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
				      unsigned int irq_num, bool level)
{
	return 0;
}

static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
{
	return 0;
}

static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
				    struct kvm_exit_mmio *mmio)
{
	return false;
}

static inline int irqchip_in_kernel(struct kvm *kvm)
{
	return 0;
}

static inline bool vgic_initialized(struct kvm *kvm)
{
	return true;
}
#endif

#endif
Commit	Line	Data
1a89dd91 MZ	1	/*
	2	* Copyright (C) 2012 ARM Ltd.
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*/
	18
	19	#ifndef __ASM_ARM_KVM_VGIC_H
	20	#define __ASM_ARM_KVM_VGIC_H
	21
b47ef92a MZ	22	#include <linux/kernel.h>
b47ef92a MZ	23	#include <linux/kvm.h>
b47ef92a MZ	24	#include <linux/irqreturn.h>
	25	#include <linux/spinlock.h>
	26	#include <linux/types.h>
1a89dd91 MZ	27	#include <linux/irqchip/arm-gic.h>
1a89dd91 MZ	28
9b2d2e0d	29	#define VGIC_NR_IRQS 256
b47ef92a MZ	30	#define VGIC_NR_SGIS 16
	31	#define VGIC_NR_PPIS 16
	32	#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
	33	#define VGIC_NR_SHARED_IRQS (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
	34	#define VGIC_MAX_CPUS KVM_MAX_VCPUS
9d949dce	35	#define VGIC_MAX_LRS (1 << 6)
b47ef92a MZ	36
	37	/* Sanity checks... */
	38	#if (VGIC_MAX_CPUS > 8)
	39	#error Invalid number of CPU interfaces
	40	#endif
	41
	42	#if (VGIC_NR_IRQS & 31)
	43	#error "VGIC_NR_IRQS must be a multiple of 32"
	44	#endif
	45
	46	#if (VGIC_NR_IRQS > 1024)
	47	#error "VGIC_NR_IRQS must be <= 1024"
	48	#endif
	49
	50	/*
	51	* The GIC distributor registers describing interrupts have two parts:
	52	* - 32 per-CPU interrupts (SGI + PPI)
	53	* - a bunch of shared interrupts (SPI)
	54	*/
	55	struct vgic_bitmap {
	56	union {
	57	u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
	58	DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
	59	} percpu[VGIC_MAX_CPUS];
	60	union {
	61	u32 reg[VGIC_NR_SHARED_IRQS / 32];
	62	DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
	63	} shared;
	64	};
	65
	66	struct vgic_bytemap {
	67	u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
	68	u32 shared[VGIC_NR_SHARED_IRQS / 4];
	69	};
	70
8d5c6b06 MZ	71	struct kvm_vcpu;
	72
	73	#define LR_STATE_PENDING (1 << 0)
	74	#define LR_STATE_ACTIVE (1 << 1)
	75	#define LR_STATE_MASK (3 << 0)
	76	#define LR_EOI_INT (1 << 2)
	77
	78	struct vgic_lr {
	79	u16 irq;
	80	u8 source;
	81	u8 state;
	82	};
	83
	84	struct vgic_ops {
	85	struct vgic_lr (get_lr)(const struct kvm_vcpu , int);
	86	void (set_lr)(struct kvm_vcpu , int, struct vgic_lr);
69bb2c9f MZ	87	void (sync_lr_elrsr)(struct kvm_vcpu , int, struct vgic_lr);
69bb2c9f MZ	88	u64 (get_elrsr)(const struct kvm_vcpu vcpu);
8d6a0313	89	u64 (get_eisr)(const struct kvm_vcpu vcpu);
495dd859	90	u32 (get_interrupt_status)(const struct kvm_vcpu vcpu);
909d9b50 MZ	91	void (enable_underflow)(struct kvm_vcpu vcpu);
909d9b50 MZ	92	void (disable_underflow)(struct kvm_vcpu vcpu);
8d5c6b06 MZ	93	};
8d5c6b06 MZ	94
1a89dd91	95	struct vgic_dist {
b47ef92a MZ	96	#ifdef CONFIG_KVM_ARM_VGIC
b47ef92a MZ	97	spinlock_t lock;
01ac5e34	98	bool ready;
b47ef92a MZ	99
	100	/* Virtual control interface mapping */
	101	void __iomem *vctrl_base;
	102
330690cd CD	103	/* Distributor and vcpu interface mapping in the guest */
	104	phys_addr_t vgic_dist_base;
	105	phys_addr_t vgic_cpu_base;
b47ef92a MZ	106
	107	/* Distributor enabled */
	108	u32 enabled;
	109
	110	/* Interrupt enabled (one bit per IRQ) */
	111	struct vgic_bitmap irq_enabled;
	112
	113	/* Interrupt 'pin' level */
	114	struct vgic_bitmap irq_state;
	115
	116	/* Level-triggered interrupt in progress */
	117	struct vgic_bitmap irq_active;
	118
	119	/* Interrupt priority. Not used yet. */
	120	struct vgic_bytemap irq_priority;
	121
	122	/* Level/edge triggered */
	123	struct vgic_bitmap irq_cfg;
	124
	125	/* Source CPU per SGI and target CPU */
	126	u8 irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];
	127
	128	/* Target CPU for each IRQ */
	129	u8 irq_spi_cpu[VGIC_NR_SHARED_IRQS];
	130	struct vgic_bitmap irq_spi_target[VGIC_MAX_CPUS];
	131
	132	/* Bitmap indicating which CPU has something pending */
	133	unsigned long irq_pending_on_cpu;
	134	#endif
1a89dd91 MZ	135	};
1a89dd91 MZ	136
eede821d MZ	137	struct vgic_v2_cpu_if {
	138	u32 vgic_hcr;
	139	u32 vgic_vmcr;
	140	u32 vgic_misr; /* Saved only */
	141	u32 vgic_eisr[2]; /* Saved only */
	142	u32 vgic_elrsr[2]; /* Saved only */
	143	u32 vgic_apr;
	144	u32 vgic_lr[VGIC_MAX_LRS];
	145	};
	146
1a89dd91	147	struct vgic_cpu {
9d949dce MZ	148	#ifdef CONFIG_KVM_ARM_VGIC
	149	/* per IRQ to LR mapping */
	150	u8 vgic_irq_lr_map[VGIC_NR_IRQS];
	151
	152	/* Pending interrupts on this VCPU */
	153	DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
	154	DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS);
	155
	156	/* Bitmap of used/free list registers */
	157	DECLARE_BITMAP( lr_used, VGIC_MAX_LRS);
	158
	159	/* Number of list registers on this CPU */
	160	int nr_lr;
	161
	162	/* CPU vif control registers for world switch */
eede821d MZ	163	union {
	164	struct vgic_v2_cpu_if vgic_v2;
	165	};
9d949dce	166	#endif
1a89dd91 MZ	167	};
1a89dd91 MZ	168
9d949dce MZ	169	#define LR_EMPTY 0xff
9d949dce MZ	170
495dd859 MZ	171	#define INT_STATUS_EOI (1 << 0)
	172	#define INT_STATUS_UNDERFLOW (1 << 1)
	173
1a89dd91 MZ	174	struct kvm;
	175	struct kvm_vcpu;
	176	struct kvm_run;
	177	struct kvm_exit_mmio;
	178
	179	#ifdef CONFIG_KVM_ARM_VGIC
ce01e4e8	180	int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write);
01ac5e34 MZ	181	int kvm_vgic_hyp_init(void);
	182	int kvm_vgic_init(struct kvm *kvm);
	183	int kvm_vgic_create(struct kvm *kvm);
	184	int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
9d949dce MZ	185	void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
9d949dce MZ	186	void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
5863c2ce MZ	187	int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
5863c2ce MZ	188	bool level);
9d949dce	189	int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
1a89dd91 MZ	190	bool vgic_handle_mmio(struct kvm_vcpu vcpu, struct kvm_run run,
	191	struct kvm_exit_mmio *mmio);
	192
9d949dce	193	#define irqchip_in_kernel(k) (!!((k)->arch.vgic.vctrl_base))
01ac5e34	194	#define vgic_initialized(k) ((k)->arch.vgic.ready)
9d949dce	195
1a89dd91 MZ	196	#else
	197	static inline int kvm_vgic_hyp_init(void)
	198	{
	199	return 0;
	200	}
	201
330690cd CD	202	static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
	203	{
	204	return 0;
	205	}
	206
6cbde825 MZ	207	static inline int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write)
	208	{
	209	return -ENXIO;
	210	}
	211
1a89dd91 MZ	212	static inline int kvm_vgic_init(struct kvm *kvm)
	213	{
	214	return 0;
	215	}
	216
	217	static inline int kvm_vgic_create(struct kvm *kvm)
	218	{
	219	return 0;
	220	}
	221
	222	static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
	223	{
	224	return 0;
	225	}
	226
	227	static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
	228	static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
	229
5863c2ce MZ	230	static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
	231	unsigned int irq_num, bool level)
	232	{
	233	return 0;
	234	}
	235
1a89dd91 MZ	236	static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
	237	{
	238	return 0;
	239	}
	240
	241	static inline bool vgic_handle_mmio(struct kvm_vcpu vcpu, struct kvm_run run,
	242	struct kvm_exit_mmio *mmio)
	243	{
	244	return false;
	245	}
	246
	247	static inline int irqchip_in_kernel(struct kvm *kvm)
	248	{
	249	return 0;
	250	}
01ac5e34 MZ	251
	252	static inline bool vgic_initialized(struct kvm *kvm)
	253	{
	254	return true;
	255	}
1a89dd91 MZ	256	#endif
	257
	258	#endif