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1da177e4 LT |
1 | /* |
2 | * linux/include/asm-arm/hardware/amba_kmi.h | |
3 | * | |
4 | * Internal header file for AMBA KMI ports | |
5 | * | |
6 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | * | |
23 | * --------------------------------------------------------------------------- | |
24 | * From ARM PrimeCell(tm) PS2 Keyboard/Mouse Interface (PL050) Technical | |
25 | * Reference Manual - ARM DDI 0143B - see http://www.arm.com/ | |
26 | * --------------------------------------------------------------------------- | |
27 | */ | |
28 | #ifndef ASM_ARM_HARDWARE_AMBA_KMI_H | |
29 | #define ASM_ARM_HARDWARE_AMBA_KMI_H | |
30 | ||
31 | /* | |
32 | * KMI control register: | |
33 | * KMICR_TYPE 0 = PS2/AT mode, 1 = No line control bit mode | |
34 | * KMICR_RXINTREN 1 = enable RX interrupts | |
35 | * KMICR_TXINTREN 1 = enable TX interrupts | |
36 | * KMICR_EN 1 = enable KMI | |
37 | * KMICR_FD 1 = force KMI data low | |
38 | * KMICR_FC 1 = force KMI clock low | |
39 | */ | |
40 | #define KMICR (KMI_BASE + 0x00) | |
41 | #define KMICR_TYPE (1 << 5) | |
42 | #define KMICR_RXINTREN (1 << 4) | |
43 | #define KMICR_TXINTREN (1 << 3) | |
44 | #define KMICR_EN (1 << 2) | |
45 | #define KMICR_FD (1 << 1) | |
46 | #define KMICR_FC (1 << 0) | |
47 | ||
48 | /* | |
49 | * KMI status register: | |
50 | * KMISTAT_TXEMPTY 1 = transmitter register empty | |
51 | * KMISTAT_TXBUSY 1 = currently sending data | |
52 | * KMISTAT_RXFULL 1 = receiver register ready to be read | |
53 | * KMISTAT_RXBUSY 1 = currently receiving data | |
54 | * KMISTAT_RXPARITY parity of last databyte received | |
55 | * KMISTAT_IC current level of KMI clock input | |
56 | * KMISTAT_ID current level of KMI data input | |
57 | */ | |
58 | #define KMISTAT (KMI_BASE + 0x04) | |
59 | #define KMISTAT_TXEMPTY (1 << 6) | |
60 | #define KMISTAT_TXBUSY (1 << 5) | |
61 | #define KMISTAT_RXFULL (1 << 4) | |
62 | #define KMISTAT_RXBUSY (1 << 3) | |
63 | #define KMISTAT_RXPARITY (1 << 2) | |
64 | #define KMISTAT_IC (1 << 1) | |
65 | #define KMISTAT_ID (1 << 0) | |
66 | ||
67 | /* | |
68 | * KMI data register | |
69 | */ | |
70 | #define KMIDATA (KMI_BASE + 0x08) | |
71 | ||
72 | /* | |
73 | * KMI clock divisor: to generate 8MHz internal clock | |
74 | * div = (ref / 8MHz) - 1; 0 <= div <= 15 | |
75 | */ | |
76 | #define KMICLKDIV (KMI_BASE + 0x0c) | |
77 | ||
78 | /* | |
79 | * KMI interrupt register: | |
80 | * KMIIR_TXINTR 1 = transmit interrupt asserted | |
81 | * KMIIR_RXINTR 1 = receive interrupt asserted | |
82 | */ | |
83 | #define KMIIR (KMI_BASE + 0x10) | |
84 | #define KMIIR_TXINTR (1 << 1) | |
85 | #define KMIIR_RXINTR (1 << 0) | |
86 | ||
87 | /* | |
88 | * The size of the KMI primecell | |
89 | */ | |
90 | #define KMI_SIZE (0x100) | |
91 | ||
92 | #endif |