projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 3a95b9fb | 1 | /* include/linux/amba/pl080.h |
| fa7a7883 BD |
2 | * |
| 3 | * Copyright 2008 Openmoko, Inc. | |
| 4 | * Copyright 2008 Simtec Electronics | |
| 5 | * http://armlinux.simtec.co.uk/ | |
| 6 | * Ben Dooks <ben@simtec.co.uk> | |
| 7 | * | |
| 8 | * ARM PrimeCell PL080 DMA controller | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License version 2 as | |
| 12 | * published by the Free Software Foundation. | |
| 13 | */ | |
| 14 | ||
| 15 | /* Note, there are some Samsung updates to this controller block which | |
| 16 | * make it not entierly compatible with the PL080 specification from | |
| 17 | * ARM. When in doubt, check the Samsung documentation first. | |
| 18 | * | |
| 25985edc | 19 | * The Samsung defines are PL080S, and add an extra control register, |
| fa7a7883 BD |
20 | * the ability to move more than 2^11 counts of data and some extra |
| 21 | * OneNAND features. | |
| 22 | */ | |
| 23 | ||
| 47850a27 VK |
24 | #ifndef ASM_PL080_H |
| 25 | #define ASM_PL080_H | |
| 26 | ||
| fa7a7883 BD |
27 | #define PL080_INT_STATUS (0x00) |
| 28 | #define PL080_TC_STATUS (0x04) | |
| 29 | #define PL080_TC_CLEAR (0x08) | |
| 30 | #define PL080_ERR_STATUS (0x0C) | |
| 31 | #define PL080_ERR_CLEAR (0x10) | |
| 32 | #define PL080_RAW_TC_STATUS (0x14) | |
| 33 | #define PL080_RAW_ERR_STATUS (0x18) | |
| 34 | #define PL080_EN_CHAN (0x1c) | |
| 35 | #define PL080_SOFT_BREQ (0x20) | |
| 36 | #define PL080_SOFT_SREQ (0x24) | |
| 37 | #define PL080_SOFT_LBREQ (0x28) | |
| 38 | #define PL080_SOFT_LSREQ (0x2C) | |
| 39 | ||
| 40 | #define PL080_CONFIG (0x30) | |
| ded091fe LW |
41 | #define PL080_CONFIG_M2_BE BIT(2) |
| 42 | #define PL080_CONFIG_M1_BE BIT(1) | |
| 43 | #define PL080_CONFIG_ENABLE BIT(0) | |
| fa7a7883 BD |
44 | |
| 45 | #define PL080_SYNC (0x34) | |
| 46 | ||
| 47 | /* Per channel configuration registers */ | |
| 48 | ||
| 44f0aeec | 49 | /* Per channel configuration registers */ |
| fa7a7883 | 50 | #define PL080_Cx_BASE(x) ((0x100 + (x * 0x20))) |
| fa7a7883 BD |
51 | #define PL080_CH_SRC_ADDR (0x00) |
| 52 | #define PL080_CH_DST_ADDR (0x04) | |
| 53 | #define PL080_CH_LLI (0x08) | |
| 54 | #define PL080_CH_CONTROL (0x0C) | |
| 55 | #define PL080_CH_CONFIG (0x10) | |
| 56 | #define PL080S_CH_CONTROL2 (0x10) | |
| 57 | #define PL080S_CH_CONFIG (0x14) | |
| 58 | ||
| 59 | #define PL080_LLI_ADDR_MASK (0x3fffffff << 2) | |
| 60 | #define PL080_LLI_ADDR_SHIFT (2) | |
| ded091fe | 61 | #define PL080_LLI_LM_AHB2 BIT(0) |
| fa7a7883 | 62 | |
| ded091fe | 63 | #define PL080_CONTROL_TC_IRQ_EN BIT(31) |
| fa7a7883 BD |
64 | #define PL080_CONTROL_PROT_MASK (0x7 << 28) |
| 65 | #define PL080_CONTROL_PROT_SHIFT (28) | |
| ded091fe LW |
66 | #define PL080_CONTROL_PROT_CACHE BIT(30) |
| 67 | #define PL080_CONTROL_PROT_BUFF BIT(29) | |
| 68 | #define PL080_CONTROL_PROT_SYS BIT(28) | |
| 69 | #define PL080_CONTROL_DST_INCR BIT(27) | |
| 70 | #define PL080_CONTROL_SRC_INCR BIT(26) | |
| 71 | #define PL080_CONTROL_DST_AHB2 BIT(25) | |
| 72 | #define PL080_CONTROL_SRC_AHB2 BIT(24) | |
| fa7a7883 BD |
73 | #define PL080_CONTROL_DWIDTH_MASK (0x7 << 21) |
| 74 | #define PL080_CONTROL_DWIDTH_SHIFT (21) | |
| 75 | #define PL080_CONTROL_SWIDTH_MASK (0x7 << 18) | |
| 76 | #define PL080_CONTROL_SWIDTH_SHIFT (18) | |
| 77 | #define PL080_CONTROL_DB_SIZE_MASK (0x7 << 15) | |
| 78 | #define PL080_CONTROL_DB_SIZE_SHIFT (15) | |
| 79 | #define PL080_CONTROL_SB_SIZE_MASK (0x7 << 12) | |
| 80 | #define PL080_CONTROL_SB_SIZE_SHIFT (12) | |
| 81 | #define PL080_CONTROL_TRANSFER_SIZE_MASK (0xfff << 0) | |
| da1b6c05 | 82 | #define PL080S_CONTROL_TRANSFER_SIZE_MASK (0x1ffffff << 0) |
| fa7a7883 BD |
83 | #define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0) |
| 84 | ||
| 85 | #define PL080_BSIZE_1 (0x0) | |
| 86 | #define PL080_BSIZE_4 (0x1) | |
| 87 | #define PL080_BSIZE_8 (0x2) | |
| 88 | #define PL080_BSIZE_16 (0x3) | |
| 89 | #define PL080_BSIZE_32 (0x4) | |
| 90 | #define PL080_BSIZE_64 (0x5) | |
| 91 | #define PL080_BSIZE_128 (0x6) | |
| 92 | #define PL080_BSIZE_256 (0x7) | |
| 93 | ||
| 94 | #define PL080_WIDTH_8BIT (0x0) | |
| 95 | #define PL080_WIDTH_16BIT (0x1) | |
| 96 | #define PL080_WIDTH_32BIT (0x2) | |
| 97 | ||
| ded091fe LW |
98 | #define PL080N_CONFIG_ITPROT BIT(20) |
| 99 | #define PL080N_CONFIG_SECPROT BIT(19) | |
| 100 | #define PL080_CONFIG_HALT BIT(18) | |
| 101 | #define PL080_CONFIG_ACTIVE BIT(17) /* RO */ | |
| 102 | #define PL080_CONFIG_LOCK BIT(16) | |
| 103 | #define PL080_CONFIG_TC_IRQ_MASK BIT(15) | |
| 104 | #define PL080_CONFIG_ERR_IRQ_MASK BIT(14) | |
| fa7a7883 BD |
105 | #define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11) |
| 106 | #define PL080_CONFIG_FLOW_CONTROL_SHIFT (11) | |
| 107 | #define PL080_CONFIG_DST_SEL_MASK (0xf << 6) | |
| 108 | #define PL080_CONFIG_DST_SEL_SHIFT (6) | |
| 109 | #define PL080_CONFIG_SRC_SEL_MASK (0xf << 1) | |
| 110 | #define PL080_CONFIG_SRC_SEL_SHIFT (1) | |
| ded091fe | 111 | #define PL080_CONFIG_ENABLE BIT(0) |
| fa7a7883 BD |
112 | |
| 113 | #define PL080_FLOW_MEM2MEM (0x0) | |
| 114 | #define PL080_FLOW_MEM2PER (0x1) | |
| 115 | #define PL080_FLOW_PER2MEM (0x2) | |
| 116 | #define PL080_FLOW_SRC2DST (0x3) | |
| 117 | #define PL080_FLOW_SRC2DST_DST (0x4) | |
| 118 | #define PL080_FLOW_MEM2PER_PER (0x5) | |
| 119 | #define PL080_FLOW_PER2MEM_PER (0x6) | |
| 120 | #define PL080_FLOW_SRC2DST_SRC (0x7) | |
| 121 | ||
| 122 | /* DMA linked list chain structure */ | |
| 123 | ||
| 124 | struct pl080_lli { | |
| 125 | u32 src_addr; | |
| 126 | u32 dst_addr; | |
| 127 | u32 next_lli; | |
| 128 | u32 control0; | |
| 129 | }; | |
| 130 | ||
| 131 | struct pl080s_lli { | |
| 132 | u32 src_addr; | |
| 133 | u32 dst_addr; | |
| 134 | u32 next_lli; | |
| 135 | u32 control0; | |
| 136 | u32 control1; | |
| 137 | }; | |
| 138 | ||
| 47850a27 | 139 | #endif /* ASM_PL080_H */ |