[mirror_ubuntu-jammy-kernel.git] / include / linux / amd-iommu.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
 * Author: Joerg Roedel <joerg.roedel@amd.com>
 *         Leo Duran <leo.duran@amd.com>
 */

#ifndef _ASM_X86_AMD_IOMMU_H
#define _ASM_X86_AMD_IOMMU_H

#include <linux/types.h>

struct amd_iommu;

/*
 * This is mainly used to communicate information back-and-forth
 * between SVM and IOMMU for setting up and tearing down posted
 * interrupt
 */
struct amd_iommu_pi_data {
	u32 ga_tag;
	u32 prev_ga_tag;
	u64 base;
	bool is_guest_mode;
	struct vcpu_data *vcpu_data;
	void *ir_data;
};

#ifdef CONFIG_AMD_IOMMU

struct task_struct;
struct pci_dev;

extern int amd_iommu_detect(void);
extern int amd_iommu_init_hardware(void);

/**
 * amd_iommu_init_device() - Init device for use with IOMMUv2 driver
 * @pdev: The PCI device to initialize
 * @pasids: Number of PASIDs to support for this device
 *
 * This function does all setup for the device pdev so that it can be
 * used with IOMMUv2.
 * Returns 0 on success or negative value on error.
 */
extern int amd_iommu_init_device(struct pci_dev *pdev, int pasids);

/**
 * amd_iommu_free_device() - Free all IOMMUv2 related device resources
 *			     and disable IOMMUv2 usage for this device
 * @pdev: The PCI device to disable IOMMUv2 usage for'
 */
extern void amd_iommu_free_device(struct pci_dev *pdev);

/**
 * amd_iommu_bind_pasid() - Bind a given task to a PASID on a device
 * @pdev: The PCI device to bind the task to
 * @pasid: The PASID on the device the task should be bound to
 * @task: the task to bind
 *
 * The function returns 0 on success or a negative value on error.
 */
extern int amd_iommu_bind_pasid(struct pci_dev *pdev, u32 pasid,
				struct task_struct *task);

/**
 * amd_iommu_unbind_pasid() - Unbind a PASID from its task on
 *			      a device
 * @pdev: The device of the PASID
 * @pasid: The PASID to unbind
 *
 * When this function returns the device is no longer using the PASID
 * and the PASID is no longer bound to its task.
 */
extern void amd_iommu_unbind_pasid(struct pci_dev *pdev, u32 pasid);

/**
 * amd_iommu_set_invalid_ppr_cb() - Register a call-back for failed
 *				    PRI requests
 * @pdev: The PCI device the call-back should be registered for
 * @cb: The call-back function
 *
 * The IOMMUv2 driver invokes this call-back when it is unable to
 * successfully handle a PRI request. The device driver can then decide
 * which PRI response the device should see. Possible return values for
 * the call-back are:
 *
 * - AMD_IOMMU_INV_PRI_RSP_SUCCESS - Send SUCCESS back to the device
 * - AMD_IOMMU_INV_PRI_RSP_INVALID - Send INVALID back to the device
 * - AMD_IOMMU_INV_PRI_RSP_FAIL    - Send Failure back to the device,
 *				     the device is required to disable
 *				     PRI when it receives this response
 *
 * The function returns 0 on success or negative value on error.
 */
#define AMD_IOMMU_INV_PRI_RSP_SUCCESS	0
#define AMD_IOMMU_INV_PRI_RSP_INVALID	1
#define AMD_IOMMU_INV_PRI_RSP_FAIL	2

typedef int (*amd_iommu_invalid_ppr_cb)(struct pci_dev *pdev,
					u32 pasid,
					unsigned long address,
					u16);

extern int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev,
					amd_iommu_invalid_ppr_cb cb);

#define PPR_FAULT_EXEC	(1 << 1)
#define PPR_FAULT_READ  (1 << 2)
#define PPR_FAULT_WRITE (1 << 5)
#define PPR_FAULT_USER  (1 << 6)
#define PPR_FAULT_RSVD  (1 << 7)
#define PPR_FAULT_GN    (1 << 8)

/**
 * amd_iommu_device_info() - Get information about IOMMUv2 support of a
 *			     PCI device
 * @pdev: PCI device to query information from
 * @info: A pointer to an amd_iommu_device_info structure which will contain
 *	  the information about the PCI device
 *
 * Returns 0 on success, negative value on error
 */

#define AMD_IOMMU_DEVICE_FLAG_ATS_SUP     0x1    /* ATS feature supported */
#define AMD_IOMMU_DEVICE_FLAG_PRI_SUP     0x2    /* PRI feature supported */
#define AMD_IOMMU_DEVICE_FLAG_PASID_SUP   0x4    /* PASID context supported */
#define AMD_IOMMU_DEVICE_FLAG_EXEC_SUP    0x8    /* Device may request execution
						    on memory pages */
#define AMD_IOMMU_DEVICE_FLAG_PRIV_SUP   0x10    /* Device may request
						    super-user privileges */

struct amd_iommu_device_info {
	int max_pasids;
	u32 flags;
};

extern int amd_iommu_device_info(struct pci_dev *pdev,
				 struct amd_iommu_device_info *info);

/**
 * amd_iommu_set_invalidate_ctx_cb() - Register a call-back for invalidating
 *				       a pasid context. This call-back is
 *				       invoked when the IOMMUv2 driver needs to
 *				       invalidate a PASID context, for example
 *				       because the task that is bound to that
 *				       context is about to exit.
 *
 * @pdev: The PCI device the call-back should be registered for
 * @cb: The call-back function
 */

typedef void (*amd_iommu_invalidate_ctx)(struct pci_dev *pdev, u32 pasid);

extern int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev,
					   amd_iommu_invalidate_ctx cb);
#else /* CONFIG_AMD_IOMMU */

static inline int amd_iommu_detect(void) { return -ENODEV; }

#endif /* CONFIG_AMD_IOMMU */

#if defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP)

/* IOMMU AVIC Function */
extern int amd_iommu_register_ga_log_notifier(int (*notifier)(u32));

extern int
amd_iommu_update_ga(int cpu, bool is_run, void *data);

extern int amd_iommu_activate_guest_mode(void *data);
extern int amd_iommu_deactivate_guest_mode(void *data);

#else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */

static inline int
amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
{
	return 0;
}

static inline int
amd_iommu_update_ga(int cpu, bool is_run, void *data)
{
	return 0;
}

static inline int amd_iommu_activate_guest_mode(void *data)
{
	return 0;
}

static inline int amd_iommu_deactivate_guest_mode(void *data)
{
	return 0;
}
#endif /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */

int amd_iommu_get_num_iommus(void);
bool amd_iommu_pc_supported(void);
u8 amd_iommu_pc_get_max_banks(unsigned int idx);
u8 amd_iommu_pc_get_max_counters(unsigned int idx);
int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
		u64 *value);
int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
		u64 *value);
struct amd_iommu *get_amd_iommu(unsigned int idx);

#endif /* _ASM_X86_AMD_IOMMU_H */
Commit	Line	Data
45051539	1	/* SPDX-License-Identifier: GPL-2.0-only */
c6da992e	2	/*
5d0d7156	3	* Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
c6da992e JR	4	* Author: Joerg Roedel <joerg.roedel@amd.com>
c6da992e JR	5	* Leo Duran <leo.duran@amd.com>
c6da992e JR	6	*/
c6da992e JR	7
1965aae3 PA	8	#ifndef _ASM_X86_AMD_IOMMU_H
1965aae3 PA	9	#define _ASM_X86_AMD_IOMMU_H
c6da992e	10
ed96f228	11	#include <linux/types.h>
c6da992e	12
fc1b6620 CH	13	struct amd_iommu;
fc1b6620 CH	14
b9fc6b56 SS	15	/*
	16	* This is mainly used to communicate information back-and-forth
	17	* between SVM and IOMMU for setting up and tearing down posted
	18	* interrupt
	19	*/
	20	struct amd_iommu_pi_data {
	21	u32 ga_tag;
	22	u32 prev_ga_tag;
	23	u64 base;
	24	bool is_guest_mode;
	25	struct vcpu_data *vcpu_data;
	26	void *ir_data;
	27	};
	28
c6da992e	29	#ifdef CONFIG_AMD_IOMMU
6a9401a7	30
2d5503b6	31	struct task_struct;
ed96f228 JR	32	struct pci_dev;
ed96f228 JR	33
480125ba	34	extern int amd_iommu_detect(void);
8704a1ba	35	extern int amd_iommu_init_hardware(void);
6a113ddc	36
ed96f228 JR	37	/**
	38	* amd_iommu_init_device() - Init device for use with IOMMUv2 driver
	39	* @pdev: The PCI device to initialize
	40	* @pasids: Number of PASIDs to support for this device
	41	*
	42	* This function does all setup for the device pdev so that it can be
	43	* used with IOMMUv2.
	44	* Returns 0 on success or negative value on error.
	45	*/
	46	extern int amd_iommu_init_device(struct pci_dev *pdev, int pasids);
	47
	48	/**
	49	* amd_iommu_free_device() - Free all IOMMUv2 related device resources
	50	* and disable IOMMUv2 usage for this device
	51	* @pdev: The PCI device to disable IOMMUv2 usage for'
	52	*/
	53	extern void amd_iommu_free_device(struct pci_dev *pdev);
	54
2d5503b6 JR	55	/**
	56	* amd_iommu_bind_pasid() - Bind a given task to a PASID on a device
	57	* @pdev: The PCI device to bind the task to
	58	* @pasid: The PASID on the device the task should be bound to
	59	* @task: the task to bind
	60	*
	61	* The function returns 0 on success or a negative value on error.
	62	*/
c7b6bac9	63	extern int amd_iommu_bind_pasid(struct pci_dev *pdev, u32 pasid,
2d5503b6 JR	64	struct task_struct *task);
	65
	66	/**
	67	* amd_iommu_unbind_pasid() - Unbind a PASID from its task on
	68	* a device
	69	* @pdev: The device of the PASID
	70	* @pasid: The PASID to unbind
	71	*
	72	* When this function returns the device is no longer using the PASID
	73	* and the PASID is no longer bound to its task.
	74	*/
c7b6bac9	75	extern void amd_iommu_unbind_pasid(struct pci_dev *pdev, u32 pasid);
2d5503b6	76
175d6146 JR	77	/**
	78	* amd_iommu_set_invalid_ppr_cb() - Register a call-back for failed
	79	* PRI requests
	80	* @pdev: The PCI device the call-back should be registered for
	81	* @cb: The call-back function
	82	*
	83	* The IOMMUv2 driver invokes this call-back when it is unable to
	84	* successfully handle a PRI request. The device driver can then decide
	85	* which PRI response the device should see. Possible return values for
	86	* the call-back are:
	87	*
	88	* - AMD_IOMMU_INV_PRI_RSP_SUCCESS - Send SUCCESS back to the device
	89	* - AMD_IOMMU_INV_PRI_RSP_INVALID - Send INVALID back to the device
	90	* - AMD_IOMMU_INV_PRI_RSP_FAIL - Send Failure back to the device,
	91	* the device is required to disable
	92	* PRI when it receives this response
	93	*
	94	* The function returns 0 on success or negative value on error.
	95	*/
	96	#define AMD_IOMMU_INV_PRI_RSP_SUCCESS 0
	97	#define AMD_IOMMU_INV_PRI_RSP_INVALID 1
	98	#define AMD_IOMMU_INV_PRI_RSP_FAIL 2
	99
	100	typedef int (amd_iommu_invalid_ppr_cb)(struct pci_dev pdev,
c7b6bac9	101	u32 pasid,
175d6146 JR	102	unsigned long address,
	103	u16);
	104
	105	extern int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev,
	106	amd_iommu_invalid_ppr_cb cb);
	107
51499aa9 AS	108	#define PPR_FAULT_EXEC (1 << 1)
	109	#define PPR_FAULT_READ (1 << 2)
	110	#define PPR_FAULT_WRITE (1 << 5)
	111	#define PPR_FAULT_USER (1 << 6)
	112	#define PPR_FAULT_RSVD (1 << 7)
	113	#define PPR_FAULT_GN (1 << 8)
	114
52efdb89 JR	115	/**
	116	* amd_iommu_device_info() - Get information about IOMMUv2 support of a
	117	* PCI device
	118	* @pdev: PCI device to query information from
	119	* @info: A pointer to an amd_iommu_device_info structure which will contain
	120	* the information about the PCI device
	121	*
	122	* Returns 0 on success, negative value on error
	123	*/
	124
	125	#define AMD_IOMMU_DEVICE_FLAG_ATS_SUP 0x1 /* ATS feature supported */
	126	#define AMD_IOMMU_DEVICE_FLAG_PRI_SUP 0x2 /* PRI feature supported */
	127	#define AMD_IOMMU_DEVICE_FLAG_PASID_SUP 0x4 /* PASID context supported */
	128	#define AMD_IOMMU_DEVICE_FLAG_EXEC_SUP 0x8 /* Device may request execution
	129	on memory pages */
	130	#define AMD_IOMMU_DEVICE_FLAG_PRIV_SUP 0x10 /* Device may request
	131	super-user privileges */
	132
	133	struct amd_iommu_device_info {
	134	int max_pasids;
	135	u32 flags;
	136	};
	137
	138	extern int amd_iommu_device_info(struct pci_dev *pdev,
	139	struct amd_iommu_device_info *info);
	140
bc21662f JR	141	/**
	142	* amd_iommu_set_invalidate_ctx_cb() - Register a call-back for invalidating
	143	* a pasid context. This call-back is
	144	* invoked when the IOMMUv2 driver needs to
	145	* invalidate a PASID context, for example
	146	* because the task that is bound to that
	147	* context is about to exit.
	148	*
	149	* @pdev: The PCI device the call-back should be registered for
	150	* @cb: The call-back function
	151	*/
	152
c7b6bac9	153	typedef void (amd_iommu_invalidate_ctx)(struct pci_dev pdev, u32 pasid);
bc21662f JR	154
	155	extern int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev,
	156	amd_iommu_invalidate_ctx cb);
bd6fcefc	157	#else /* CONFIG_AMD_IOMMU */
6a9401a7	158
480125ba	159	static inline int amd_iommu_detect(void) { return -ENODEV; }
6a9401a7	160
bd6fcefc SS	161	#endif /* CONFIG_AMD_IOMMU */
	162
	163	#if defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP)
	164
	165	/* IOMMU AVIC Function */
	166	extern int amd_iommu_register_ga_log_notifier(int (*notifier)(u32));
	167
8dbea3fd SS	168	extern int
	169	amd_iommu_update_ga(int cpu, bool is_run, void *data);
	170
b9c6ff94 SS	171	extern int amd_iommu_activate_guest_mode(void *data);
	172	extern int amd_iommu_deactivate_guest_mode(void *data);
	173
bd6fcefc SS	174	#else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
	175
	176	static inline int
	177	amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
	178	{
	179	return 0;
	180	}
	181
8dbea3fd SS	182	static inline int
	183	amd_iommu_update_ga(int cpu, bool is_run, void *data)
	184	{
	185	return 0;
	186	}
	187
b9c6ff94 SS	188	static inline int amd_iommu_activate_guest_mode(void *data)
	189	{
	190	return 0;
	191	}
	192
	193	static inline int amd_iommu_deactivate_guest_mode(void *data)
	194	{
	195	return 0;
	196	}
bd6fcefc	197	#endif /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
c6da992e	198
fc1b6620 CH	199	int amd_iommu_get_num_iommus(void);
	200	bool amd_iommu_pc_supported(void);
	201	u8 amd_iommu_pc_get_max_banks(unsigned int idx);
	202	u8 amd_iommu_pc_get_max_counters(unsigned int idx);
	203	int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
	204	u64 *value);
	205	int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
	206	u64 *value);
	207	struct amd_iommu *get_amd_iommu(unsigned int idx);
	208
1965aae3	209	#endif /* _ASM_X86_AMD_IOMMU_H */