[mirror_ubuntu-bionic-kernel.git] / include / linux / arm-smccc.h

/*
 * Copyright (c) 2015, Linaro Limited
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */
#ifndef __LINUX_ARM_SMCCC_H
#define __LINUX_ARM_SMCCC_H

#include <uapi/linux/const.h>

/*
 * This file provides common defines for ARM SMC Calling Convention as
 * specified in
 * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
 */

#define ARM_SMCCC_STD_CALL	        _AC(0,U)
#define ARM_SMCCC_FAST_CALL	        _AC(1,U)
#define ARM_SMCCC_TYPE_SHIFT		31

#define ARM_SMCCC_SMC_32		0
#define ARM_SMCCC_SMC_64		1
#define ARM_SMCCC_CALL_CONV_SHIFT	30

#define ARM_SMCCC_OWNER_MASK		0x3F
#define ARM_SMCCC_OWNER_SHIFT		24

#define ARM_SMCCC_FUNC_MASK		0xFFFF

#define ARM_SMCCC_IS_FAST_CALL(smc_val)	\
	((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT))
#define ARM_SMCCC_IS_64(smc_val) \
	((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT))
#define ARM_SMCCC_FUNC_NUM(smc_val)	((smc_val) & ARM_SMCCC_FUNC_MASK)
#define ARM_SMCCC_OWNER_NUM(smc_val) \
	(((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK)

#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \
	(((type) << ARM_SMCCC_TYPE_SHIFT) | \
	((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \
	(((owner) & ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \
	((func_num) & ARM_SMCCC_FUNC_MASK))

#define ARM_SMCCC_OWNER_ARCH		0
#define ARM_SMCCC_OWNER_CPU		1
#define ARM_SMCCC_OWNER_SIP		2
#define ARM_SMCCC_OWNER_OEM		3
#define ARM_SMCCC_OWNER_STANDARD	4
#define ARM_SMCCC_OWNER_TRUSTED_APP	48
#define ARM_SMCCC_OWNER_TRUSTED_APP_END	49
#define ARM_SMCCC_OWNER_TRUSTED_OS	50
#define ARM_SMCCC_OWNER_TRUSTED_OS_END	63

#define ARM_SMCCC_QUIRK_NONE		0
#define ARM_SMCCC_QUIRK_QCOM_A6		1 /* Save/restore register a6 */

#define ARM_SMCCC_VERSION_1_0		0x10000
#define ARM_SMCCC_VERSION_1_1		0x10001

#define ARM_SMCCC_VERSION_FUNC_ID					\
	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL,				\
			   ARM_SMCCC_SMC_32,				\
			   0, 0)

#define ARM_SMCCC_ARCH_FEATURES_FUNC_ID					\
	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL,				\
			   ARM_SMCCC_SMC_32,				\
			   0, 1)

#define ARM_SMCCC_ARCH_WORKAROUND_1					\
	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL,				\
			   ARM_SMCCC_SMC_32,				\
			   0, 0x8000)

#ifndef __ASSEMBLY__

#include <linux/linkage.h>
#include <linux/types.h>
/**
 * struct arm_smccc_res - Result from SMC/HVC call
 * @a0-a3 result values from registers 0 to 3
 */
struct arm_smccc_res {
	unsigned long a0;
	unsigned long a1;
	unsigned long a2;
	unsigned long a3;
};

/**
 * struct arm_smccc_quirk - Contains quirk information
 * @id: quirk identification
 * @state: quirk specific information
 * @a6: Qualcomm quirk entry for returning post-smc call contents of a6
 */
struct arm_smccc_quirk {
	int	id;
	union {
		unsigned long a6;
	} state;
};

/**
 * __arm_smccc_smc() - make SMC calls
 * @a0-a7: arguments passed in registers 0 to 7
 * @res: result values from registers 0 to 3
 * @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required.
 *
 * This function is used to make SMC calls following SMC Calling Convention.
 * The content of the supplied param are copied to registers 0 to 7 prior
 * to the SMC instruction. The return values are updated with the content
 * from register 0 to 3 on return from the SMC instruction.  An optional
 * quirk structure provides vendor specific behavior.
 */
asmlinkage void __arm_smccc_smc(unsigned long a0, unsigned long a1,
			unsigned long a2, unsigned long a3, unsigned long a4,
			unsigned long a5, unsigned long a6, unsigned long a7,
			struct arm_smccc_res *res, struct arm_smccc_quirk *quirk);

/**
 * __arm_smccc_hvc() - make HVC calls
 * @a0-a7: arguments passed in registers 0 to 7
 * @res: result values from registers 0 to 3
 * @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required.
 *
 * This function is used to make HVC calls following SMC Calling
 * Convention.  The content of the supplied param are copied to registers 0
 * to 7 prior to the HVC instruction. The return values are updated with
 * the content from register 0 to 3 on return from the HVC instruction.  An
 * optional quirk structure provides vendor specific behavior.
 */
asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1,
			unsigned long a2, unsigned long a3, unsigned long a4,
			unsigned long a5, unsigned long a6, unsigned long a7,
			struct arm_smccc_res *res, struct arm_smccc_quirk *quirk);

#define arm_smccc_smc(...) __arm_smccc_smc(__VA_ARGS__, NULL)

#define arm_smccc_smc_quirk(...) __arm_smccc_smc(__VA_ARGS__)

#define arm_smccc_hvc(...) __arm_smccc_hvc(__VA_ARGS__, NULL)

#define arm_smccc_hvc_quirk(...) __arm_smccc_hvc(__VA_ARGS__)

/* SMCCC v1.1 implementation madness follows */
#ifdef CONFIG_ARM64

#define SMCCC_SMC_INST	"smc	#0"
#define SMCCC_HVC_INST	"hvc	#0"

#elif defined(CONFIG_ARM)
#include <asm/opcodes-sec.h>
#include <asm/opcodes-virt.h>

#define SMCCC_SMC_INST	__SMC(0)
#define SMCCC_HVC_INST	__HVC(0)

#endif

#define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x

#define __count_args(...)						\
	___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0)

#define __constraint_write_0						\
	"+r" (r0), "=&r" (r1), "=&r" (r2), "=&r" (r3)
#define __constraint_write_1						\
	"+r" (r0), "+r" (r1), "=&r" (r2), "=&r" (r3)
#define __constraint_write_2						\
	"+r" (r0), "+r" (r1), "+r" (r2), "=&r" (r3)
#define __constraint_write_3						\
	"+r" (r0), "+r" (r1), "+r" (r2), "+r" (r3)
#define __constraint_write_4	__constraint_write_3
#define __constraint_write_5	__constraint_write_4
#define __constraint_write_6	__constraint_write_5
#define __constraint_write_7	__constraint_write_6

#define __constraint_read_0
#define __constraint_read_1
#define __constraint_read_2
#define __constraint_read_3
#define __constraint_read_4	"r" (r4)
#define __constraint_read_5	__constraint_read_4, "r" (r5)
#define __constraint_read_6	__constraint_read_5, "r" (r6)
#define __constraint_read_7	__constraint_read_6, "r" (r7)

#define __declare_arg_0(a0, res)					\
	struct arm_smccc_res   *___res = res;				\
	register u32           r0 asm("r0") = a0;			\
	register unsigned long r1 asm("r1");				\
	register unsigned long r2 asm("r2");				\
	register unsigned long r3 asm("r3")

#define __declare_arg_1(a0, a1, res)					\
	struct arm_smccc_res   *___res = res;				\
	register u32           r0 asm("r0") = a0;			\
	register typeof(a1)    r1 asm("r1") = a1;			\
	register unsigned long r2 asm("r2");				\
	register unsigned long r3 asm("r3")

#define __declare_arg_2(a0, a1, a2, res)				\
	struct arm_smccc_res   *___res = res;				\
	register u32           r0 asm("r0") = a0;			\
	register typeof(a1)    r1 asm("r1") = a1;			\
	register typeof(a2)    r2 asm("r2") = a2;			\
	register unsigned long r3 asm("r3")

#define __declare_arg_3(a0, a1, a2, a3, res)				\
	struct arm_smccc_res   *___res = res;				\
	register u32           r0 asm("r0") = a0;			\
	register typeof(a1)    r1 asm("r1") = a1;			\
	register typeof(a2)    r2 asm("r2") = a2;			\
	register typeof(a3)    r3 asm("r3") = a3

#define __declare_arg_4(a0, a1, a2, a3, a4, res)			\
	__declare_arg_3(a0, a1, a2, a3, res);				\
	register typeof(a4) r4 asm("r4") = a4

#define __declare_arg_5(a0, a1, a2, a3, a4, a5, res)			\
	__declare_arg_4(a0, a1, a2, a3, a4, res);			\
	register typeof(a5) r5 asm("r5") = a5

#define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res)		\
	__declare_arg_5(a0, a1, a2, a3, a4, a5, res);			\
	register typeof(a6) r6 asm("r6") = a6

#define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res)		\
	__declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res);		\
	register typeof(a7) r7 asm("r7") = a7

#define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__)
#define __declare_args(count, ...)  ___declare_args(count, __VA_ARGS__)

#define ___constraints(count)						\
	: __constraint_write_ ## count					\
	: __constraint_read_ ## count					\
	: "memory"
#define __constraints(count)	___constraints(count)

/*
 * We have an output list that is not necessarily used, and GCC feels
 * entitled to optimise the whole sequence away. "volatile" is what
 * makes it stick.
 */
#define __arm_smccc_1_1(inst, ...)					\
	do {								\
		__declare_args(__count_args(__VA_ARGS__), __VA_ARGS__);	\
		asm volatile(inst "\n"					\
			     __constraints(__count_args(__VA_ARGS__)));	\
		if (___res)						\
			*___res = (typeof(*___res)){r0, r1, r2, r3};	\
	} while (0)

/*
 * arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call
 *
 * This is a variadic macro taking one to eight source arguments, and
 * an optional return structure.
 *
 * @a0-a7: arguments passed in registers 0 to 7
 * @res: result values from registers 0 to 3
 *
 * This macro is used to make SMC calls following SMC Calling Convention v1.1.
 * The content of the supplied param are copied to registers 0 to 7 prior
 * to the SMC instruction. The return values are updated with the content
 * from register 0 to 3 on return from the SMC instruction if not NULL.
 */
#define arm_smccc_1_1_smc(...)	__arm_smccc_1_1(SMCCC_SMC_INST, __VA_ARGS__)

/*
 * arm_smccc_1_1_hvc() - make an SMCCC v1.1 compliant HVC call
 *
 * This is a variadic macro taking one to eight source arguments, and
 * an optional return structure.
 *
 * @a0-a7: arguments passed in registers 0 to 7
 * @res: result values from registers 0 to 3
 *
 * This macro is used to make HVC calls following SMC Calling Convention v1.1.
 * The content of the supplied param are copied to registers 0 to 7 prior
 * to the HVC instruction. The return values are updated with the content
 * from register 0 to 3 on return from the HVC instruction if not NULL.
 */
#define arm_smccc_1_1_hvc(...)	__arm_smccc_1_1(SMCCC_HVC_INST, __VA_ARGS__)

/* Return codes defined in ARM DEN 0070A */
#define SMCCC_RET_SUCCESS			0
#define SMCCC_RET_NOT_SUPPORTED			-1
#define SMCCC_RET_NOT_REQUIRED			-2

#endif /*__ASSEMBLY__*/
#endif /*__LINUX_ARM_SMCCC_H*/
Commit	Line	Data
98dd64f3 JW	1	/*
	2	* Copyright (c) 2015, Linaro Limited
	3	*
	4	* This software is licensed under the terms of the GNU General Public
	5	* License version 2, as published by the Free Software Foundation, and
	6	* may be copied, distributed, and modified under those terms.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	*/
	14	#ifndef __LINUX_ARM_SMCCC_H
	15	#define __LINUX_ARM_SMCCC_H
	16
e391aa59 MZ	17	#include <uapi/linux/const.h>
e391aa59 MZ	18
98dd64f3 JW	19	/*
	20	* This file provides common defines for ARM SMC Calling Convention as
	21	* specified in
	22	* http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
	23	*/
	24
e391aa59 MZ	25	#define ARM_SMCCC_STD_CALL _AC(0,U)
e391aa59 MZ	26	#define ARM_SMCCC_FAST_CALL _AC(1,U)
98dd64f3 JW	27	#define ARM_SMCCC_TYPE_SHIFT 31
	28
	29	#define ARM_SMCCC_SMC_32 0
	30	#define ARM_SMCCC_SMC_64 1
	31	#define ARM_SMCCC_CALL_CONV_SHIFT 30
	32
	33	#define ARM_SMCCC_OWNER_MASK 0x3F
	34	#define ARM_SMCCC_OWNER_SHIFT 24
	35
	36	#define ARM_SMCCC_FUNC_MASK 0xFFFF
	37
	38	#define ARM_SMCCC_IS_FAST_CALL(smc_val) \
	39	((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT))
	40	#define ARM_SMCCC_IS_64(smc_val) \
	41	((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT))
	42	#define ARM_SMCCC_FUNC_NUM(smc_val) ((smc_val) & ARM_SMCCC_FUNC_MASK)
	43	#define ARM_SMCCC_OWNER_NUM(smc_val) \
	44	(((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK)
	45
	46	#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \
	47	(((type) << ARM_SMCCC_TYPE_SHIFT) \| \
	48	((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) \| \
	49	(((owner) & ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) \| \
	50	((func_num) & ARM_SMCCC_FUNC_MASK))
	51
	52	#define ARM_SMCCC_OWNER_ARCH 0
	53	#define ARM_SMCCC_OWNER_CPU 1
	54	#define ARM_SMCCC_OWNER_SIP 2
	55	#define ARM_SMCCC_OWNER_OEM 3
	56	#define ARM_SMCCC_OWNER_STANDARD 4
	57	#define ARM_SMCCC_OWNER_TRUSTED_APP 48
	58	#define ARM_SMCCC_OWNER_TRUSTED_APP_END 49
	59	#define ARM_SMCCC_OWNER_TRUSTED_OS 50
	60	#define ARM_SMCCC_OWNER_TRUSTED_OS_END 63
	61
82bcd087 AG	62	#define ARM_SMCCC_QUIRK_NONE 0
	63	#define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */
	64
7b5b30e9 MZ	65	#define ARM_SMCCC_VERSION_1_0 0x10000
	66	#define ARM_SMCCC_VERSION_1_1 0x10001
	67
	68	#define ARM_SMCCC_VERSION_FUNC_ID \
	69	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \
	70	ARM_SMCCC_SMC_32, \
	71	0, 0)
	72
	73	#define ARM_SMCCC_ARCH_FEATURES_FUNC_ID \
	74	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \
	75	ARM_SMCCC_SMC_32, \
	76	0, 1)
	77
d5a70971 MZ	78	#define ARM_SMCCC_ARCH_WORKAROUND_1 \
	79	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \
	80	ARM_SMCCC_SMC_32, \
	81	0, 0x8000)
	82
82bcd087 AG	83	#ifndef __ASSEMBLY__
	84
	85	#include <linux/linkage.h>
	86	#include <linux/types.h>
98dd64f3 JW	87	/**
	88	* struct arm_smccc_res - Result from SMC/HVC call
	89	* @a0-a3 result values from registers 0 to 3
	90	*/
	91	struct arm_smccc_res {
	92	unsigned long a0;
	93	unsigned long a1;
	94	unsigned long a2;
	95	unsigned long a3;
	96	};
	97
	98	/**
680a0873 AG	99	* struct arm_smccc_quirk - Contains quirk information
	100	* @id: quirk identification
	101	* @state: quirk specific information
	102	* @a6: Qualcomm quirk entry for returning post-smc call contents of a6
	103	*/
	104	struct arm_smccc_quirk {
	105	int id;
	106	union {
	107	unsigned long a6;
	108	} state;
	109	};
	110
	111	/**
	112	* __arm_smccc_smc() - make SMC calls
98dd64f3 JW	113	* @a0-a7: arguments passed in registers 0 to 7
98dd64f3 JW	114	* @res: result values from registers 0 to 3
680a0873	115	* @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required.
98dd64f3 JW	116	*
	117	* This function is used to make SMC calls following SMC Calling Convention.
	118	* The content of the supplied param are copied to registers 0 to 7 prior
	119	* to the SMC instruction. The return values are updated with the content
680a0873 AG	120	* from register 0 to 3 on return from the SMC instruction. An optional
680a0873 AG	121	* quirk structure provides vendor specific behavior.
98dd64f3	122	*/
680a0873	123	asmlinkage void __arm_smccc_smc(unsigned long a0, unsigned long a1,
98dd64f3 JW	124	unsigned long a2, unsigned long a3, unsigned long a4,
98dd64f3 JW	125	unsigned long a5, unsigned long a6, unsigned long a7,
680a0873	126	struct arm_smccc_res res, struct arm_smccc_quirk quirk);
98dd64f3 JW	127
98dd64f3 JW	128	/**
680a0873	129	* __arm_smccc_hvc() - make HVC calls
98dd64f3 JW	130	* @a0-a7: arguments passed in registers 0 to 7
98dd64f3 JW	131	* @res: result values from registers 0 to 3
3046ec67	132	* @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required.
98dd64f3 JW	133	*
	134	* This function is used to make HVC calls following SMC Calling
	135	* Convention. The content of the supplied param are copied to registers 0
	136	* to 7 prior to the HVC instruction. The return values are updated with
680a0873 AG	137	* the content from register 0 to 3 on return from the HVC instruction. An
680a0873 AG	138	* optional quirk structure provides vendor specific behavior.
98dd64f3	139	*/
680a0873	140	asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1,
98dd64f3 JW	141	unsigned long a2, unsigned long a3, unsigned long a4,
98dd64f3 JW	142	unsigned long a5, unsigned long a6, unsigned long a7,
680a0873 AG	143	struct arm_smccc_res res, struct arm_smccc_quirk quirk);
	144
	145	#define arm_smccc_smc(...) __arm_smccc_smc(__VA_ARGS__, NULL)
	146
	147	#define arm_smccc_smc_quirk(...) __arm_smccc_smc(__VA_ARGS__)
	148
	149	#define arm_smccc_hvc(...) __arm_smccc_hvc(__VA_ARGS__, NULL)
	150
	151	#define arm_smccc_hvc_quirk(...) __arm_smccc_hvc(__VA_ARGS__)
98dd64f3	152
79cead80 MZ	153	/* SMCCC v1.1 implementation madness follows */
	154	#ifdef CONFIG_ARM64
	155
	156	#define SMCCC_SMC_INST "smc #0"
	157	#define SMCCC_HVC_INST "hvc #0"
	158
	159	#elif defined(CONFIG_ARM)
	160	#include <asm/opcodes-sec.h>
	161	#include <asm/opcodes-virt.h>
	162
	163	#define SMCCC_SMC_INST __SMC(0)
	164	#define SMCCC_HVC_INST __HVC(0)
	165
	166	#endif
	167
	168	#define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x
	169
	170	#define __count_args(...) \
	171	___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0)
	172
	173	#define __constraint_write_0 \
	174	"+r" (r0), "=&r" (r1), "=&r" (r2), "=&r" (r3)
	175	#define __constraint_write_1 \
	176	"+r" (r0), "+r" (r1), "=&r" (r2), "=&r" (r3)
	177	#define __constraint_write_2 \
	178	"+r" (r0), "+r" (r1), "+r" (r2), "=&r" (r3)
	179	#define __constraint_write_3 \
	180	"+r" (r0), "+r" (r1), "+r" (r2), "+r" (r3)
	181	#define __constraint_write_4 __constraint_write_3
	182	#define __constraint_write_5 __constraint_write_4
	183	#define __constraint_write_6 __constraint_write_5
	184	#define __constraint_write_7 __constraint_write_6
	185
	186	#define __constraint_read_0
	187	#define __constraint_read_1
	188	#define __constraint_read_2
	189	#define __constraint_read_3
	190	#define __constraint_read_4 "r" (r4)
	191	#define __constraint_read_5 __constraint_read_4, "r" (r5)
	192	#define __constraint_read_6 __constraint_read_5, "r" (r6)
	193	#define __constraint_read_7 __constraint_read_6, "r" (r7)
	194
	195	#define __declare_arg_0(a0, res) \
	196	struct arm_smccc_res *___res = res; \
	197	register u32 r0 asm("r0") = a0; \
	198	register unsigned long r1 asm("r1"); \
	199	register unsigned long r2 asm("r2"); \
	200	register unsigned long r3 asm("r3")
	201
	202	#define __declare_arg_1(a0, a1, res) \
	203	struct arm_smccc_res *___res = res; \
	204	register u32 r0 asm("r0") = a0; \
	205	register typeof(a1) r1 asm("r1") = a1; \
	206	register unsigned long r2 asm("r2"); \
	207	register unsigned long r3 asm("r3")
	208
	209	#define __declare_arg_2(a0, a1, a2, res) \
	210	struct arm_smccc_res *___res = res; \
	211	register u32 r0 asm("r0") = a0; \
	212	register typeof(a1) r1 asm("r1") = a1; \
	213	register typeof(a2) r2 asm("r2") = a2; \
	214	register unsigned long r3 asm("r3")
	215
	216	#define __declare_arg_3(a0, a1, a2, a3, res) \
217	struct arm_smccc_res *___res = res; \
218	register u32 r0 asm("r0") = a0; \
219	register typeof(a1) r1 asm("r1") = a1; \
220	register typeof(a2) r2 asm("r2") = a2; \
221	register typeof(a3) r3 asm("r3") = a3
222
223	#define __declare_arg_4(a0, a1, a2, a3, a4, res) \
224	__declare_arg_3(a0, a1, a2, a3, res); \
225	register typeof(a4) r4 asm("r4") = a4
226
227	#define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \
228	__declare_arg_4(a0, a1, a2, a3, a4, res); \
229	register typeof(a5) r5 asm("r5") = a5
230
231	#define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \
232	__declare_arg_5(a0, a1, a2, a3, a4, a5, res); \
233	register typeof(a6) r6 asm("r6") = a6
234
235	#define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \
236	__declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \
237	register typeof(a7) r7 asm("r7") = a7
238
239	#define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__)
240	#define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__)
241
242	#define ___constraints(count) \
243	: __constraint_write_ ## count \
244	: __constraint_read_ ## count \
245	: "memory"
246	#define __constraints(count) ___constraints(count)
247
248	/*
249	* We have an output list that is not necessarily used, and GCC feels
250	* entitled to optimise the whole sequence away. "volatile" is what
251	* makes it stick.
252	*/
253	#define __arm_smccc_1_1(inst, ...) \
254	do { \
255	__declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \
256	asm volatile(inst "\n" \
257	__constraints(__count_args(__VA_ARGS__))); \
258	if (___res) \
259	___res = (typeof(___res)){r0, r1, r2, r3}; \
260	} while (0)
261
262	/*
263	* arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call
264	*
265	* This is a variadic macro taking one to eight source arguments, and
266	* an optional return structure.
267	*
268	* @a0-a7: arguments passed in registers 0 to 7
269	* @res: result values from registers 0 to 3
270	*
271	* This macro is used to make SMC calls following SMC Calling Convention v1.1.
272	* The content of the supplied param are copied to registers 0 to 7 prior
273	* to the SMC instruction. The return values are updated with the content
274	* from register 0 to 3 on return from the SMC instruction if not NULL.
275	*/
276	#define arm_smccc_1_1_smc(...) __arm_smccc_1_1(SMCCC_SMC_INST, __VA_ARGS__)
277
278	/*
279	* arm_smccc_1_1_hvc() - make an SMCCC v1.1 compliant HVC call
280	*
281	* This is a variadic macro taking one to eight source arguments, and
282	* an optional return structure.
283	*
284	* @a0-a7: arguments passed in registers 0 to 7
285	* @res: result values from registers 0 to 3
286	*
287	* This macro is used to make HVC calls following SMC Calling Convention v1.1.
288	* The content of the supplied param are copied to registers 0 to 7 prior
289	* to the HVC instruction. The return values are updated with the content
290	* from register 0 to 3 on return from the HVC instruction if not NULL.
291	*/
292	#define arm_smccc_1_1_hvc(...) __arm_smccc_1_1(SMCCC_HVC_INST, __VA_ARGS__)
293
f2ad53c9 MZ	294	/* Return codes defined in ARM DEN 0070A */
	295	#define SMCCC_RET_SUCCESS 0
	296	#define SMCCC_RET_NOT_SUPPORTED -1
	297	#define SMCCC_RET_NOT_REQUIRED -2
	298
82bcd087	299	#endif /__ASSEMBLY__/
98dd64f3	300	#endif /__LINUX_ARM_SMCCC_H/