[mirror_ubuntu-artful-kernel.git] / include / linux / atmel-ssc.h

#ifndef __INCLUDE_ATMEL_SSC_H
#define __INCLUDE_ATMEL_SSC_H

#include <linux/platform_device.h>
#include <linux/list.h>
#include <linux/io.h>

struct atmel_ssc_platform_data {
	int			use_dma;
	int			has_fslen_ext;
};

struct ssc_device {
	struct list_head	list;
	dma_addr_t		phybase;
	void __iomem		*regs;
	struct platform_device	*pdev;
	struct atmel_ssc_platform_data *pdata;
	struct clk		*clk;
	int			user;
	int			irq;
	bool			clk_from_rk_pin;
	bool			sound_dai;
};

struct ssc_device * __must_check ssc_request(unsigned int ssc_num);
void ssc_free(struct ssc_device *ssc);

/* SSC register offsets */

/* SSC Control Register */
#define SSC_CR				0x00000000
#define SSC_CR_RXDIS_SIZE			 1
#define SSC_CR_RXDIS_OFFSET			 1
#define SSC_CR_RXEN_SIZE			 1
#define SSC_CR_RXEN_OFFSET			 0
#define SSC_CR_SWRST_SIZE			 1
#define SSC_CR_SWRST_OFFSET			15
#define SSC_CR_TXDIS_SIZE			 1
#define SSC_CR_TXDIS_OFFSET			 9
#define SSC_CR_TXEN_SIZE			 1
#define SSC_CR_TXEN_OFFSET			 8

/* SSC Clock Mode Register */
#define SSC_CMR				0x00000004
#define SSC_CMR_DIV_SIZE			12
#define SSC_CMR_DIV_OFFSET			 0

/* SSC Receive Clock Mode Register */
#define SSC_RCMR			0x00000010
#define SSC_RCMR_CKG_SIZE			 2
#define SSC_RCMR_CKG_OFFSET			 6
#define SSC_RCMR_CKI_SIZE			 1
#define SSC_RCMR_CKI_OFFSET			 5
#define SSC_RCMR_CKO_SIZE			 3
#define SSC_RCMR_CKO_OFFSET			 2
#define SSC_RCMR_CKS_SIZE			 2
#define SSC_RCMR_CKS_OFFSET			 0
#define SSC_RCMR_PERIOD_SIZE			 8
#define SSC_RCMR_PERIOD_OFFSET			24
#define SSC_RCMR_START_SIZE			 4
#define SSC_RCMR_START_OFFSET			 8
#define SSC_RCMR_STOP_SIZE			 1
#define SSC_RCMR_STOP_OFFSET			12
#define SSC_RCMR_STTDLY_SIZE			 8
#define SSC_RCMR_STTDLY_OFFSET			16

/* SSC Receive Frame Mode Register */
#define SSC_RFMR			0x00000014
#define SSC_RFMR_DATLEN_SIZE			 5
#define SSC_RFMR_DATLEN_OFFSET			 0
#define SSC_RFMR_DATNB_SIZE			 4
#define SSC_RFMR_DATNB_OFFSET			 8
#define SSC_RFMR_FSEDGE_SIZE			 1
#define SSC_RFMR_FSEDGE_OFFSET			24
/*
 * The FSLEN_EXT exist on at91sam9rl, at91sam9g10,
 * at91sam9g20, and at91sam9g45 and newer SoCs
 */
#define SSC_RFMR_FSLEN_EXT_SIZE			 4
#define SSC_RFMR_FSLEN_EXT_OFFSET		28
#define SSC_RFMR_FSLEN_SIZE			 4
#define SSC_RFMR_FSLEN_OFFSET			16
#define SSC_RFMR_FSOS_SIZE			 4
#define SSC_RFMR_FSOS_OFFSET			20
#define SSC_RFMR_LOOP_SIZE			 1
#define SSC_RFMR_LOOP_OFFSET			 5
#define SSC_RFMR_MSBF_SIZE			 1
#define SSC_RFMR_MSBF_OFFSET			 7

/* SSC Transmit Clock Mode Register */
#define SSC_TCMR			0x00000018
#define SSC_TCMR_CKG_SIZE			 2
#define SSC_TCMR_CKG_OFFSET			 6
#define SSC_TCMR_CKI_SIZE			 1
#define SSC_TCMR_CKI_OFFSET			 5
#define SSC_TCMR_CKO_SIZE			 3
#define SSC_TCMR_CKO_OFFSET			 2
#define SSC_TCMR_CKS_SIZE			 2
#define SSC_TCMR_CKS_OFFSET			 0
#define SSC_TCMR_PERIOD_SIZE			 8
#define SSC_TCMR_PERIOD_OFFSET			24
#define SSC_TCMR_START_SIZE			 4
#define SSC_TCMR_START_OFFSET			 8
#define SSC_TCMR_STTDLY_SIZE			 8
#define SSC_TCMR_STTDLY_OFFSET			16

/* SSC Transmit Frame Mode Register */
#define SSC_TFMR			0x0000001c
#define SSC_TFMR_DATDEF_SIZE			 1
#define SSC_TFMR_DATDEF_OFFSET			 5
#define SSC_TFMR_DATLEN_SIZE			 5
#define SSC_TFMR_DATLEN_OFFSET			 0
#define SSC_TFMR_DATNB_SIZE			 4
#define SSC_TFMR_DATNB_OFFSET			 8
#define SSC_TFMR_FSDEN_SIZE			 1
#define SSC_TFMR_FSDEN_OFFSET			23
#define SSC_TFMR_FSEDGE_SIZE			 1
#define SSC_TFMR_FSEDGE_OFFSET			24
/*
 * The FSLEN_EXT exist on at91sam9rl, at91sam9g10,
 * at91sam9g20, and at91sam9g45 and newer SoCs
 */
#define SSC_TFMR_FSLEN_EXT_SIZE			 4
#define SSC_TFMR_FSLEN_EXT_OFFSET		28
#define SSC_TFMR_FSLEN_SIZE			 4
#define SSC_TFMR_FSLEN_OFFSET			16
#define SSC_TFMR_FSOS_SIZE			 3
#define SSC_TFMR_FSOS_OFFSET			20
#define SSC_TFMR_MSBF_SIZE			 1
#define SSC_TFMR_MSBF_OFFSET			 7

/* SSC Receive Hold Register */
#define SSC_RHR				0x00000020
#define SSC_RHR_RDAT_SIZE			32
#define SSC_RHR_RDAT_OFFSET			 0

/* SSC Transmit Hold Register */
#define SSC_THR				0x00000024
#define SSC_THR_TDAT_SIZE			32
#define SSC_THR_TDAT_OFFSET			 0

/* SSC Receive Sync. Holding Register */
#define SSC_RSHR			0x00000030
#define SSC_RSHR_RSDAT_SIZE			16
#define SSC_RSHR_RSDAT_OFFSET			 0

/* SSC Transmit Sync. Holding Register */
#define SSC_TSHR			0x00000034
#define SSC_TSHR_TSDAT_SIZE			16
#define SSC_TSHR_RSDAT_OFFSET			 0

/* SSC Receive Compare 0 Register */
#define SSC_RC0R			0x00000038
#define SSC_RC0R_CP0_SIZE			16
#define SSC_RC0R_CP0_OFFSET			 0

/* SSC Receive Compare 1 Register */
#define SSC_RC1R			0x0000003c
#define SSC_RC1R_CP1_SIZE			16
#define SSC_RC1R_CP1_OFFSET			 0

/* SSC Status Register */
#define SSC_SR				0x00000040
#define SSC_SR_CP0_SIZE				 1
#define SSC_SR_CP0_OFFSET			 8
#define SSC_SR_CP1_SIZE				 1
#define SSC_SR_CP1_OFFSET			 9
#define SSC_SR_ENDRX_SIZE			 1
#define SSC_SR_ENDRX_OFFSET			 6
#define SSC_SR_ENDTX_SIZE			 1
#define SSC_SR_ENDTX_OFFSET			 2
#define SSC_SR_OVRUN_SIZE			 1
#define SSC_SR_OVRUN_OFFSET			 5
#define SSC_SR_RXBUFF_SIZE			 1
#define SSC_SR_RXBUFF_OFFSET			 7
#define SSC_SR_RXEN_SIZE			 1
#define SSC_SR_RXEN_OFFSET			17
#define SSC_SR_RXRDY_SIZE			 1
#define SSC_SR_RXRDY_OFFSET			 4
#define SSC_SR_RXSYN_SIZE			 1
#define SSC_SR_RXSYN_OFFSET			11
#define SSC_SR_TXBUFE_SIZE			 1
#define SSC_SR_TXBUFE_OFFSET			 3
#define SSC_SR_TXEMPTY_SIZE			 1
#define SSC_SR_TXEMPTY_OFFSET			 1
#define SSC_SR_TXEN_SIZE			 1
#define SSC_SR_TXEN_OFFSET			16
#define SSC_SR_TXRDY_SIZE			 1
#define SSC_SR_TXRDY_OFFSET			 0
#define SSC_SR_TXSYN_SIZE			 1
#define SSC_SR_TXSYN_OFFSET			10

/* SSC Interrupt Enable Register */
#define SSC_IER				0x00000044
#define SSC_IER_CP0_SIZE			 1
#define SSC_IER_CP0_OFFSET			 8
#define SSC_IER_CP1_SIZE			 1
#define SSC_IER_CP1_OFFSET			 9
#define SSC_IER_ENDRX_SIZE			 1
#define SSC_IER_ENDRX_OFFSET			 6
#define SSC_IER_ENDTX_SIZE			 1
#define SSC_IER_ENDTX_OFFSET			 2
#define SSC_IER_OVRUN_SIZE			 1
#define SSC_IER_OVRUN_OFFSET			 5
#define SSC_IER_RXBUFF_SIZE			 1
#define SSC_IER_RXBUFF_OFFSET			 7
#define SSC_IER_RXRDY_SIZE			 1
#define SSC_IER_RXRDY_OFFSET			 4
#define SSC_IER_RXSYN_SIZE			 1
#define SSC_IER_RXSYN_OFFSET			11
#define SSC_IER_TXBUFE_SIZE			 1
#define SSC_IER_TXBUFE_OFFSET			 3
#define SSC_IER_TXEMPTY_SIZE			 1
#define SSC_IER_TXEMPTY_OFFSET			 1
#define SSC_IER_TXRDY_SIZE			 1
#define SSC_IER_TXRDY_OFFSET			 0
#define SSC_IER_TXSYN_SIZE			 1
#define SSC_IER_TXSYN_OFFSET			10

/* SSC Interrupt Disable Register */
#define SSC_IDR				0x00000048
#define SSC_IDR_CP0_SIZE			 1
#define SSC_IDR_CP0_OFFSET			 8
#define SSC_IDR_CP1_SIZE			 1
#define SSC_IDR_CP1_OFFSET			 9
#define SSC_IDR_ENDRX_SIZE			 1
#define SSC_IDR_ENDRX_OFFSET			 6
#define SSC_IDR_ENDTX_SIZE			 1
#define SSC_IDR_ENDTX_OFFSET			 2
#define SSC_IDR_OVRUN_SIZE			 1
#define SSC_IDR_OVRUN_OFFSET			 5
#define SSC_IDR_RXBUFF_SIZE			 1
#define SSC_IDR_RXBUFF_OFFSET			 7
#define SSC_IDR_RXRDY_SIZE			 1
#define SSC_IDR_RXRDY_OFFSET			 4
#define SSC_IDR_RXSYN_SIZE			 1
#define SSC_IDR_RXSYN_OFFSET			11
#define SSC_IDR_TXBUFE_SIZE			 1
#define SSC_IDR_TXBUFE_OFFSET			 3
#define SSC_IDR_TXEMPTY_SIZE			 1
#define SSC_IDR_TXEMPTY_OFFSET			 1
#define SSC_IDR_TXRDY_SIZE			 1
#define SSC_IDR_TXRDY_OFFSET			 0
#define SSC_IDR_TXSYN_SIZE			 1
#define SSC_IDR_TXSYN_OFFSET			10

/* SSC Interrupt Mask Register */
#define SSC_IMR				0x0000004c
#define SSC_IMR_CP0_SIZE			 1
#define SSC_IMR_CP0_OFFSET			 8
#define SSC_IMR_CP1_SIZE			 1
#define SSC_IMR_CP1_OFFSET			 9
#define SSC_IMR_ENDRX_SIZE			 1
#define SSC_IMR_ENDRX_OFFSET			 6
#define SSC_IMR_ENDTX_SIZE			 1
#define SSC_IMR_ENDTX_OFFSET			 2
#define SSC_IMR_OVRUN_SIZE			 1
#define SSC_IMR_OVRUN_OFFSET			 5
#define SSC_IMR_RXBUFF_SIZE			 1
#define SSC_IMR_RXBUFF_OFFSET			 7
#define SSC_IMR_RXRDY_SIZE			 1
#define SSC_IMR_RXRDY_OFFSET			 4
#define SSC_IMR_RXSYN_SIZE			 1
#define SSC_IMR_RXSYN_OFFSET			11
#define SSC_IMR_TXBUFE_SIZE			 1
#define SSC_IMR_TXBUFE_OFFSET			 3
#define SSC_IMR_TXEMPTY_SIZE			 1
#define SSC_IMR_TXEMPTY_OFFSET			 1
#define SSC_IMR_TXRDY_SIZE			 1
#define SSC_IMR_TXRDY_OFFSET			 0
#define SSC_IMR_TXSYN_SIZE			 1
#define SSC_IMR_TXSYN_OFFSET			10

/* SSC PDC Receive Pointer Register */
#define SSC_PDC_RPR			0x00000100

/* SSC PDC Receive Counter Register */
#define SSC_PDC_RCR			0x00000104

/* SSC PDC Transmit Pointer Register */
#define SSC_PDC_TPR			0x00000108

/* SSC PDC Receive Next Pointer Register */
#define SSC_PDC_RNPR			0x00000110

/* SSC PDC Receive Next Counter Register */
#define SSC_PDC_RNCR			0x00000114

/* SSC PDC Transmit Counter Register */
#define SSC_PDC_TCR			0x0000010c

/* SSC PDC Transmit Next Pointer Register */
#define SSC_PDC_TNPR			0x00000118

/* SSC PDC Transmit Next Counter Register */
#define SSC_PDC_TNCR			0x0000011c

/* SSC PDC Transfer Control Register */
#define SSC_PDC_PTCR			0x00000120
#define SSC_PDC_PTCR_RXTDIS_SIZE		 1
#define SSC_PDC_PTCR_RXTDIS_OFFSET		 1
#define SSC_PDC_PTCR_RXTEN_SIZE			 1
#define SSC_PDC_PTCR_RXTEN_OFFSET		 0
#define SSC_PDC_PTCR_TXTDIS_SIZE		 1
#define SSC_PDC_PTCR_TXTDIS_OFFSET		 9
#define SSC_PDC_PTCR_TXTEN_SIZE			 1
#define SSC_PDC_PTCR_TXTEN_OFFSET		 8

/* SSC PDC Transfer Status Register */
#define SSC_PDC_PTSR			0x00000124
#define SSC_PDC_PTSR_RXTEN_SIZE			 1
#define SSC_PDC_PTSR_RXTEN_OFFSET		 0
#define SSC_PDC_PTSR_TXTEN_SIZE			 1
#define SSC_PDC_PTSR_TXTEN_OFFSET		 8

/* Bit manipulation macros */
#define SSC_BIT(name)					\
	(1 << SSC_##name##_OFFSET)
#define SSC_BF(name, value)				\
	(((value) & ((1 << SSC_##name##_SIZE) - 1))	\
	 << SSC_##name##_OFFSET)
#define SSC_BFEXT(name, value)				\
	(((value) >> SSC_##name##_OFFSET)		\
	 & ((1 << SSC_##name##_SIZE) - 1))
#define SSC_BFINS(name, value, old)			\
	(((old) & ~(((1 << SSC_##name##_SIZE) - 1)	\
	<< SSC_##name##_OFFSET)) | SSC_BF(name, value))

/* Register access macros */
#define ssc_readl(base, reg)		__raw_readl(base + SSC_##reg)
#define ssc_writel(base, reg, value)	__raw_writel((value), base + SSC_##reg)

#endif /* __INCLUDE_ATMEL_SSC_H */
Commit	Line	Data
eb1f2930 HCE	1	#ifndef __INCLUDE_ATMEL_SSC_H
	2	#define __INCLUDE_ATMEL_SSC_H
	3
	4	#include <linux/platform_device.h>
	5	#include <linux/list.h>
b969afc8	6	#include <linux/io.h>
eb1f2930	7
636036d2 BS	8	struct atmel_ssc_platform_data {
636036d2 BS	9	int use_dma;
c4027faf	10	int has_fslen_ext;
636036d2 BS	11	};
636036d2 BS	12
eb1f2930 HCE	13	struct ssc_device {
eb1f2930 HCE	14	struct list_head list;
10175b3b	15	dma_addr_t phybase;
eb1f2930 HCE	16	void __iomem *regs;
eb1f2930 HCE	17	struct platform_device *pdev;
636036d2	18	struct atmel_ssc_platform_data *pdata;
eb1f2930 HCE	19	struct clk *clk;
	20	int user;
	21	int irq;
048d4ff8	22	bool clk_from_rk_pin;
e8314d7d	23	bool sound_dai;
eb1f2930 HCE	24	};
	25
	26	struct ssc_device * __must_check ssc_request(unsigned int ssc_num);
	27	void ssc_free(struct ssc_device *ssc);
	28
	29	/* SSC register offsets */
	30
	31	/* SSC Control Register */
	32	#define SSC_CR 0x00000000
	33	#define SSC_CR_RXDIS_SIZE 1
	34	#define SSC_CR_RXDIS_OFFSET 1
	35	#define SSC_CR_RXEN_SIZE 1
	36	#define SSC_CR_RXEN_OFFSET 0
	37	#define SSC_CR_SWRST_SIZE 1
	38	#define SSC_CR_SWRST_OFFSET 15
	39	#define SSC_CR_TXDIS_SIZE 1
	40	#define SSC_CR_TXDIS_OFFSET 9
	41	#define SSC_CR_TXEN_SIZE 1
	42	#define SSC_CR_TXEN_OFFSET 8
	43
	44	/* SSC Clock Mode Register */
	45	#define SSC_CMR 0x00000004
	46	#define SSC_CMR_DIV_SIZE 12
	47	#define SSC_CMR_DIV_OFFSET 0
	48
	49	/* SSC Receive Clock Mode Register */
	50	#define SSC_RCMR 0x00000010
	51	#define SSC_RCMR_CKG_SIZE 2
	52	#define SSC_RCMR_CKG_OFFSET 6
	53	#define SSC_RCMR_CKI_SIZE 1
	54	#define SSC_RCMR_CKI_OFFSET 5
	55	#define SSC_RCMR_CKO_SIZE 3
	56	#define SSC_RCMR_CKO_OFFSET 2
	57	#define SSC_RCMR_CKS_SIZE 2
	58	#define SSC_RCMR_CKS_OFFSET 0
	59	#define SSC_RCMR_PERIOD_SIZE 8
	60	#define SSC_RCMR_PERIOD_OFFSET 24
	61	#define SSC_RCMR_START_SIZE 4
	62	#define SSC_RCMR_START_OFFSET 8
	63	#define SSC_RCMR_STOP_SIZE 1
	64	#define SSC_RCMR_STOP_OFFSET 12
	65	#define SSC_RCMR_STTDLY_SIZE 8
	66	#define SSC_RCMR_STTDLY_OFFSET 16
	67
	68	/* SSC Receive Frame Mode Register */
	69	#define SSC_RFMR 0x00000014
	70	#define SSC_RFMR_DATLEN_SIZE 5
	71	#define SSC_RFMR_DATLEN_OFFSET 0
	72	#define SSC_RFMR_DATNB_SIZE 4
	73	#define SSC_RFMR_DATNB_OFFSET 8
	74	#define SSC_RFMR_FSEDGE_SIZE 1
	75	#define SSC_RFMR_FSEDGE_OFFSET 24
dfaf5356 BS	76	/*
	77	* The FSLEN_EXT exist on at91sam9rl, at91sam9g10,
	78	* at91sam9g20, and at91sam9g45 and newer SoCs
	79	*/
	80	#define SSC_RFMR_FSLEN_EXT_SIZE 4
	81	#define SSC_RFMR_FSLEN_EXT_OFFSET 28
eb1f2930 HCE	82	#define SSC_RFMR_FSLEN_SIZE 4
	83	#define SSC_RFMR_FSLEN_OFFSET 16
	84	#define SSC_RFMR_FSOS_SIZE 4
	85	#define SSC_RFMR_FSOS_OFFSET 20
	86	#define SSC_RFMR_LOOP_SIZE 1
	87	#define SSC_RFMR_LOOP_OFFSET 5
	88	#define SSC_RFMR_MSBF_SIZE 1
	89	#define SSC_RFMR_MSBF_OFFSET 7
	90
	91	/* SSC Transmit Clock Mode Register */
	92	#define SSC_TCMR 0x00000018
	93	#define SSC_TCMR_CKG_SIZE 2
	94	#define SSC_TCMR_CKG_OFFSET 6
	95	#define SSC_TCMR_CKI_SIZE 1
	96	#define SSC_TCMR_CKI_OFFSET 5
	97	#define SSC_TCMR_CKO_SIZE 3
	98	#define SSC_TCMR_CKO_OFFSET 2
	99	#define SSC_TCMR_CKS_SIZE 2
	100	#define SSC_TCMR_CKS_OFFSET 0
	101	#define SSC_TCMR_PERIOD_SIZE 8
	102	#define SSC_TCMR_PERIOD_OFFSET 24
	103	#define SSC_TCMR_START_SIZE 4
	104	#define SSC_TCMR_START_OFFSET 8
	105	#define SSC_TCMR_STTDLY_SIZE 8
	106	#define SSC_TCMR_STTDLY_OFFSET 16
	107
	108	/* SSC Transmit Frame Mode Register */
	109	#define SSC_TFMR 0x0000001c
	110	#define SSC_TFMR_DATDEF_SIZE 1
	111	#define SSC_TFMR_DATDEF_OFFSET 5
	112	#define SSC_TFMR_DATLEN_SIZE 5
	113	#define SSC_TFMR_DATLEN_OFFSET 0
	114	#define SSC_TFMR_DATNB_SIZE 4
	115	#define SSC_TFMR_DATNB_OFFSET 8
	116	#define SSC_TFMR_FSDEN_SIZE 1
	117	#define SSC_TFMR_FSDEN_OFFSET 23
	118	#define SSC_TFMR_FSEDGE_SIZE 1
	119	#define SSC_TFMR_FSEDGE_OFFSET 24
dfaf5356 BS	120	/*
	121	* The FSLEN_EXT exist on at91sam9rl, at91sam9g10,
	122	* at91sam9g20, and at91sam9g45 and newer SoCs
	123	*/
	124	#define SSC_TFMR_FSLEN_EXT_SIZE 4
	125	#define SSC_TFMR_FSLEN_EXT_OFFSET 28
eb1f2930 HCE	126	#define SSC_TFMR_FSLEN_SIZE 4
	127	#define SSC_TFMR_FSLEN_OFFSET 16
	128	#define SSC_TFMR_FSOS_SIZE 3
	129	#define SSC_TFMR_FSOS_OFFSET 20
	130	#define SSC_TFMR_MSBF_SIZE 1
	131	#define SSC_TFMR_MSBF_OFFSET 7
	132
	133	/* SSC Receive Hold Register */
	134	#define SSC_RHR 0x00000020
	135	#define SSC_RHR_RDAT_SIZE 32
	136	#define SSC_RHR_RDAT_OFFSET 0
	137
	138	/* SSC Transmit Hold Register */
	139	#define SSC_THR 0x00000024
	140	#define SSC_THR_TDAT_SIZE 32
	141	#define SSC_THR_TDAT_OFFSET 0
	142
	143	/* SSC Receive Sync. Holding Register */
	144	#define SSC_RSHR 0x00000030
	145	#define SSC_RSHR_RSDAT_SIZE 16
	146	#define SSC_RSHR_RSDAT_OFFSET 0
	147
	148	/* SSC Transmit Sync. Holding Register */
	149	#define SSC_TSHR 0x00000034
	150	#define SSC_TSHR_TSDAT_SIZE 16
	151	#define SSC_TSHR_RSDAT_OFFSET 0
	152
	153	/* SSC Receive Compare 0 Register */
	154	#define SSC_RC0R 0x00000038
	155	#define SSC_RC0R_CP0_SIZE 16
	156	#define SSC_RC0R_CP0_OFFSET 0
	157
	158	/* SSC Receive Compare 1 Register */
	159	#define SSC_RC1R 0x0000003c
	160	#define SSC_RC1R_CP1_SIZE 16
	161	#define SSC_RC1R_CP1_OFFSET 0
	162
	163	/* SSC Status Register */
	164	#define SSC_SR 0x00000040
	165	#define SSC_SR_CP0_SIZE 1
	166	#define SSC_SR_CP0_OFFSET 8
	167	#define SSC_SR_CP1_SIZE 1
	168	#define SSC_SR_CP1_OFFSET 9
	169	#define SSC_SR_ENDRX_SIZE 1
	170	#define SSC_SR_ENDRX_OFFSET 6
	171	#define SSC_SR_ENDTX_SIZE 1
	172	#define SSC_SR_ENDTX_OFFSET 2
	173	#define SSC_SR_OVRUN_SIZE 1
	174	#define SSC_SR_OVRUN_OFFSET 5
	175	#define SSC_SR_RXBUFF_SIZE 1
	176	#define SSC_SR_RXBUFF_OFFSET 7
	177	#define SSC_SR_RXEN_SIZE 1
	178	#define SSC_SR_RXEN_OFFSET 17
	179	#define SSC_SR_RXRDY_SIZE 1
	180	#define SSC_SR_RXRDY_OFFSET 4
	181	#define SSC_SR_RXSYN_SIZE 1
	182	#define SSC_SR_RXSYN_OFFSET 11
	183	#define SSC_SR_TXBUFE_SIZE 1
	184	#define SSC_SR_TXBUFE_OFFSET 3
	185	#define SSC_SR_TXEMPTY_SIZE 1
	186	#define SSC_SR_TXEMPTY_OFFSET 1
	187	#define SSC_SR_TXEN_SIZE 1
	188	#define SSC_SR_TXEN_OFFSET 16
	189	#define SSC_SR_TXRDY_SIZE 1
190	#define SSC_SR_TXRDY_OFFSET 0
191	#define SSC_SR_TXSYN_SIZE 1
192	#define SSC_SR_TXSYN_OFFSET 10
193
194	/* SSC Interrupt Enable Register */
195	#define SSC_IER 0x00000044
196	#define SSC_IER_CP0_SIZE 1
197	#define SSC_IER_CP0_OFFSET 8
198	#define SSC_IER_CP1_SIZE 1
199	#define SSC_IER_CP1_OFFSET 9
200	#define SSC_IER_ENDRX_SIZE 1
201	#define SSC_IER_ENDRX_OFFSET 6
202	#define SSC_IER_ENDTX_SIZE 1
203	#define SSC_IER_ENDTX_OFFSET 2
204	#define SSC_IER_OVRUN_SIZE 1
205	#define SSC_IER_OVRUN_OFFSET 5
206	#define SSC_IER_RXBUFF_SIZE 1
207	#define SSC_IER_RXBUFF_OFFSET 7
208	#define SSC_IER_RXRDY_SIZE 1
209	#define SSC_IER_RXRDY_OFFSET 4
210	#define SSC_IER_RXSYN_SIZE 1
211	#define SSC_IER_RXSYN_OFFSET 11
212	#define SSC_IER_TXBUFE_SIZE 1
213	#define SSC_IER_TXBUFE_OFFSET 3
214	#define SSC_IER_TXEMPTY_SIZE 1
215	#define SSC_IER_TXEMPTY_OFFSET 1
216	#define SSC_IER_TXRDY_SIZE 1
217	#define SSC_IER_TXRDY_OFFSET 0
218	#define SSC_IER_TXSYN_SIZE 1
219	#define SSC_IER_TXSYN_OFFSET 10
220
221	/* SSC Interrupt Disable Register */
222	#define SSC_IDR 0x00000048
223	#define SSC_IDR_CP0_SIZE 1
224	#define SSC_IDR_CP0_OFFSET 8
225	#define SSC_IDR_CP1_SIZE 1
226	#define SSC_IDR_CP1_OFFSET 9
227	#define SSC_IDR_ENDRX_SIZE 1
228	#define SSC_IDR_ENDRX_OFFSET 6
229	#define SSC_IDR_ENDTX_SIZE 1
230	#define SSC_IDR_ENDTX_OFFSET 2
231	#define SSC_IDR_OVRUN_SIZE 1
232	#define SSC_IDR_OVRUN_OFFSET 5
233	#define SSC_IDR_RXBUFF_SIZE 1
234	#define SSC_IDR_RXBUFF_OFFSET 7
235	#define SSC_IDR_RXRDY_SIZE 1
236	#define SSC_IDR_RXRDY_OFFSET 4
237	#define SSC_IDR_RXSYN_SIZE 1
238	#define SSC_IDR_RXSYN_OFFSET 11
239	#define SSC_IDR_TXBUFE_SIZE 1
240	#define SSC_IDR_TXBUFE_OFFSET 3
241	#define SSC_IDR_TXEMPTY_SIZE 1
242	#define SSC_IDR_TXEMPTY_OFFSET 1
243	#define SSC_IDR_TXRDY_SIZE 1
244	#define SSC_IDR_TXRDY_OFFSET 0
245	#define SSC_IDR_TXSYN_SIZE 1
246	#define SSC_IDR_TXSYN_OFFSET 10
247
248	/* SSC Interrupt Mask Register */
249	#define SSC_IMR 0x0000004c
250	#define SSC_IMR_CP0_SIZE 1
251	#define SSC_IMR_CP0_OFFSET 8
252	#define SSC_IMR_CP1_SIZE 1
253	#define SSC_IMR_CP1_OFFSET 9
254	#define SSC_IMR_ENDRX_SIZE 1
255	#define SSC_IMR_ENDRX_OFFSET 6
256	#define SSC_IMR_ENDTX_SIZE 1
257	#define SSC_IMR_ENDTX_OFFSET 2
258	#define SSC_IMR_OVRUN_SIZE 1
259	#define SSC_IMR_OVRUN_OFFSET 5
260	#define SSC_IMR_RXBUFF_SIZE 1
261	#define SSC_IMR_RXBUFF_OFFSET 7
262	#define SSC_IMR_RXRDY_SIZE 1
263	#define SSC_IMR_RXRDY_OFFSET 4
264	#define SSC_IMR_RXSYN_SIZE 1
265	#define SSC_IMR_RXSYN_OFFSET 11
266	#define SSC_IMR_TXBUFE_SIZE 1
267	#define SSC_IMR_TXBUFE_OFFSET 3
268	#define SSC_IMR_TXEMPTY_SIZE 1
269	#define SSC_IMR_TXEMPTY_OFFSET 1
270	#define SSC_IMR_TXRDY_SIZE 1
271	#define SSC_IMR_TXRDY_OFFSET 0
272	#define SSC_IMR_TXSYN_SIZE 1
273	#define SSC_IMR_TXSYN_OFFSET 10
274
275	/* SSC PDC Receive Pointer Register */
276	#define SSC_PDC_RPR 0x00000100
277
278	/* SSC PDC Receive Counter Register */
279	#define SSC_PDC_RCR 0x00000104
280
281	/* SSC PDC Transmit Pointer Register */
282	#define SSC_PDC_TPR 0x00000108
283
284	/* SSC PDC Receive Next Pointer Register */
285	#define SSC_PDC_RNPR 0x00000110
286
287	/* SSC PDC Receive Next Counter Register */
288	#define SSC_PDC_RNCR 0x00000114
289
290	/* SSC PDC Transmit Counter Register */
291	#define SSC_PDC_TCR 0x0000010c
292
293	/* SSC PDC Transmit Next Pointer Register */
294	#define SSC_PDC_TNPR 0x00000118
295
296	/* SSC PDC Transmit Next Counter Register */
297	#define SSC_PDC_TNCR 0x0000011c
298
299	/* SSC PDC Transfer Control Register */
300	#define SSC_PDC_PTCR 0x00000120
301	#define SSC_PDC_PTCR_RXTDIS_SIZE 1
302	#define SSC_PDC_PTCR_RXTDIS_OFFSET 1
303	#define SSC_PDC_PTCR_RXTEN_SIZE 1
304	#define SSC_PDC_PTCR_RXTEN_OFFSET 0
305	#define SSC_PDC_PTCR_TXTDIS_SIZE 1
306	#define SSC_PDC_PTCR_TXTDIS_OFFSET 9
307	#define SSC_PDC_PTCR_TXTEN_SIZE 1
308	#define SSC_PDC_PTCR_TXTEN_OFFSET 8
309
310	/* SSC PDC Transfer Status Register */
311	#define SSC_PDC_PTSR 0x00000124
312	#define SSC_PDC_PTSR_RXTEN_SIZE 1
313	#define SSC_PDC_PTSR_RXTEN_OFFSET 0
314	#define SSC_PDC_PTSR_TXTEN_SIZE 1
315	#define SSC_PDC_PTSR_TXTEN_OFFSET 8
316
317	/* Bit manipulation macros */
318	#define SSC_BIT(name) \
319	(1 << SSC_##name##_OFFSET)
320	#define SSC_BF(name, value) \
321	(((value) & ((1 << SSC_##name##_SIZE) - 1)) \
322	<< SSC_##name##_OFFSET)
323	#define SSC_BFEXT(name, value) \
324	(((value) >> SSC_##name##_OFFSET) \
325	& ((1 << SSC_##name##_SIZE) - 1))
326	#define SSC_BFINS(name, value, old) \
327	(((old) & ~(((1 << SSC_##name##_SIZE) - 1) \
328	<< SSC_##name##_OFFSET)) \| SSC_BF(name, value))
329
330	/* Register access macros */
331	#define ssc_readl(base, reg) __raw_readl(base + SSC_##reg)
332	#define ssc_writel(base, reg, value) __raw_writel((value), base + SSC_##reg)
333
334	#endif /* __INCLUDE_ATMEL_SSC_H */