[mirror_ubuntu-eoan-kernel.git] / include / linux / atomic.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Atomic operations usable in machine independent code */
#ifndef _LINUX_ATOMIC_H
#define _LINUX_ATOMIC_H
#include <linux/types.h>

#include <asm/atomic.h>
#include <asm/barrier.h>

/*
 * Relaxed variants of xchg, cmpxchg and some atomic operations.
 *
 * We support four variants:
 *
 * - Fully ordered: The default implementation, no suffix required.
 * - Acquire: Provides ACQUIRE semantics, _acquire suffix.
 * - Release: Provides RELEASE semantics, _release suffix.
 * - Relaxed: No ordering guarantees, _relaxed suffix.
 *
 * For compound atomics performing both a load and a store, ACQUIRE
 * semantics apply only to the load and RELEASE semantics only to the
 * store portion of the operation. Note that a failed cmpxchg_acquire
 * does -not- imply any memory ordering constraints.
 *
 * See Documentation/memory-barriers.txt for ACQUIRE/RELEASE definitions.
 */

/*
 * The idea here is to build acquire/release variants by adding explicit
 * barriers on top of the relaxed variant. In the case where the relaxed
 * variant is already fully ordered, no additional barriers are needed.
 *
 * If an architecture overrides __atomic_acquire_fence() it will probably
 * want to define smp_mb__after_spinlock().
 */
#ifndef __atomic_acquire_fence
#define __atomic_acquire_fence		smp_mb__after_atomic
#endif

#ifndef __atomic_release_fence
#define __atomic_release_fence		smp_mb__before_atomic
#endif

#ifndef __atomic_pre_full_fence
#define __atomic_pre_full_fence		smp_mb__before_atomic
#endif

#ifndef __atomic_post_full_fence
#define __atomic_post_full_fence	smp_mb__after_atomic
#endif

#define __atomic_op_acquire(op, args...)				\
({									\
	typeof(op##_relaxed(args)) __ret  = op##_relaxed(args);		\
	__atomic_acquire_fence();					\
	__ret;								\
})

#define __atomic_op_release(op, args...)				\
({									\
	__atomic_release_fence();					\
	op##_relaxed(args);						\
})

#define __atomic_op_fence(op, args...)					\
({									\
	typeof(op##_relaxed(args)) __ret;				\
	__atomic_pre_full_fence();					\
	__ret = op##_relaxed(args);					\
	__atomic_post_full_fence();					\
	__ret;								\
})

#include <linux/atomic-fallback.h>

#include <asm-generic/atomic-long.h>

#endif /* _LINUX_ATOMIC_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
acac43e2	2	/* Atomic operations usable in machine independent code */
3f9d35b9 ED	3	#ifndef _LINUX_ATOMIC_H
3f9d35b9 ED	4	#define _LINUX_ATOMIC_H
ade5ef92 MR	5	#include <linux/types.h>
ade5ef92 MR	6
3f9d35b9	7	#include <asm/atomic.h>
654672d4 WD	8	#include <asm/barrier.h>
	9
	10	/*
	11	* Relaxed variants of xchg, cmpxchg and some atomic operations.
	12	*
	13	* We support four variants:
	14	*
	15	* - Fully ordered: The default implementation, no suffix required.
	16	* - Acquire: Provides ACQUIRE semantics, _acquire suffix.
	17	* - Release: Provides RELEASE semantics, _release suffix.
	18	* - Relaxed: No ordering guarantees, _relaxed suffix.
	19	*
	20	* For compound atomics performing both a load and a store, ACQUIRE
	21	* semantics apply only to the load and RELEASE semantics only to the
	22	* store portion of the operation. Note that a failed cmpxchg_acquire
	23	* does -not- imply any memory ordering constraints.
	24	*
	25	* See Documentation/memory-barriers.txt for ACQUIRE/RELEASE definitions.
	26	*/
	27
654672d4 WD	28	/*
	29	* The idea here is to build acquire/release variants by adding explicit
	30	* barriers on top of the relaxed variant. In the case where the relaxed
	31	* variant is already fully ordered, no additional barriers are needed.
e1ab7f39	32	*
fd2efaa4 MR	33	* If an architecture overrides __atomic_acquire_fence() it will probably
fd2efaa4 MR	34	* want to define smp_mb__after_spinlock().
654672d4	35	*/
fd2efaa4 MR	36	#ifndef __atomic_acquire_fence
	37	#define __atomic_acquire_fence smp_mb__after_atomic
	38	#endif
	39
	40	#ifndef __atomic_release_fence
	41	#define __atomic_release_fence smp_mb__before_atomic
	42	#endif
	43
	44	#ifndef __atomic_pre_full_fence
	45	#define __atomic_pre_full_fence smp_mb__before_atomic
	46	#endif
	47
	48	#ifndef __atomic_post_full_fence
	49	#define __atomic_post_full_fence smp_mb__after_atomic
	50	#endif
	51
654672d4 WD	52	#define __atomic_op_acquire(op, args...) \
	53	({ \
	54	typeof(op##_relaxed(args)) __ret = op##_relaxed(args); \
fd2efaa4	55	__atomic_acquire_fence(); \
654672d4 WD	56	__ret; \
	57	})
	58
	59	#define __atomic_op_release(op, args...) \
	60	({ \
fd2efaa4	61	__atomic_release_fence(); \
654672d4 WD	62	op##_relaxed(args); \
	63	})
	64
	65	#define __atomic_op_fence(op, args...) \
	66	({ \
	67	typeof(op##_relaxed(args)) __ret; \
fd2efaa4	68	__atomic_pre_full_fence(); \
654672d4	69	__ret = op##_relaxed(args); \
fd2efaa4	70	__atomic_post_full_fence(); \
654672d4 WD	71	__ret; \
	72	})
	73
9fa45070	74	#include <linux/atomic-fallback.h>
4df714be	75
90fe6514 PZ	76	#include <asm-generic/atomic-long.h>
90fe6514 PZ	77
3f9d35b9	78	#endif /* _LINUX_ATOMIC_H */