[mirror_ubuntu-artful-kernel.git] / include / linux / bcma / bcma.h

#ifndef LINUX_BCMA_H_
#define LINUX_BCMA_H_

#include <linux/pci.h>
#include <linux/mod_devicetable.h>

#include <linux/bcma/bcma_driver_chipcommon.h>
#include <linux/bcma/bcma_driver_pci.h>
#include <linux/bcma/bcma_driver_mips.h>
#include <linux/bcma/bcma_driver_gmac_cmn.h>
#include <linux/ssb/ssb.h> /* SPROM sharing */

#include <linux/bcma/bcma_regs.h>

struct bcma_device;
struct bcma_bus;

enum bcma_hosttype {
	BCMA_HOSTTYPE_PCI,
	BCMA_HOSTTYPE_SDIO,
	BCMA_HOSTTYPE_SOC,
};

struct bcma_chipinfo {
	u16 id;
	u8 rev;
	u8 pkg;
};

struct bcma_boardinfo {
	u16 vendor;
	u16 type;
};

enum bcma_clkmode {
	BCMA_CLKMODE_FAST,
	BCMA_CLKMODE_DYNAMIC,
};

struct bcma_host_ops {
	u8 (*read8)(struct bcma_device *core, u16 offset);
	u16 (*read16)(struct bcma_device *core, u16 offset);
	u32 (*read32)(struct bcma_device *core, u16 offset);
	void (*write8)(struct bcma_device *core, u16 offset, u8 value);
	void (*write16)(struct bcma_device *core, u16 offset, u16 value);
	void (*write32)(struct bcma_device *core, u16 offset, u32 value);
#ifdef CONFIG_BCMA_BLOCKIO
	void (*block_read)(struct bcma_device *core, void *buffer,
			   size_t count, u16 offset, u8 reg_width);
	void (*block_write)(struct bcma_device *core, const void *buffer,
			    size_t count, u16 offset, u8 reg_width);
#endif
	/* Agent ops */
	u32 (*aread32)(struct bcma_device *core, u16 offset);
	void (*awrite32)(struct bcma_device *core, u16 offset, u32 value);
};

/* Core manufacturers */
#define BCMA_MANUF_ARM			0x43B
#define BCMA_MANUF_MIPS			0x4A7
#define BCMA_MANUF_BCM			0x4BF

/* Core class values. */
#define BCMA_CL_SIM			0x0
#define BCMA_CL_EROM			0x1
#define BCMA_CL_CORESIGHT		0x9
#define BCMA_CL_VERIF			0xB
#define BCMA_CL_OPTIMO			0xD
#define BCMA_CL_GEN			0xE
#define BCMA_CL_PRIMECELL		0xF

/* Core-ID values. */
#define BCMA_CORE_OOB_ROUTER		0x367	/* Out of band */
#define BCMA_CORE_4706_CHIPCOMMON	0x500
#define BCMA_CORE_4706_SOC_RAM		0x50E
#define BCMA_CORE_4706_MAC_GBIT		0x52D
#define BCMA_CORE_AMEMC			0x52E	/* DDR1/2 memory controller core */
#define BCMA_CORE_ALTA			0x534	/* I2S core */
#define BCMA_CORE_4706_MAC_GBIT_COMMON	0x5DC
#define BCMA_CORE_DDR23_PHY		0x5DD
#define BCMA_CORE_INVALID		0x700
#define BCMA_CORE_CHIPCOMMON		0x800
#define BCMA_CORE_ILINE20		0x801
#define BCMA_CORE_SRAM			0x802
#define BCMA_CORE_SDRAM			0x803
#define BCMA_CORE_PCI			0x804
#define BCMA_CORE_MIPS			0x805
#define BCMA_CORE_ETHERNET		0x806
#define BCMA_CORE_V90			0x807
#define BCMA_CORE_USB11_HOSTDEV		0x808
#define BCMA_CORE_ADSL			0x809
#define BCMA_CORE_ILINE100		0x80A
#define BCMA_CORE_IPSEC			0x80B
#define BCMA_CORE_UTOPIA		0x80C
#define BCMA_CORE_PCMCIA		0x80D
#define BCMA_CORE_INTERNAL_MEM		0x80E
#define BCMA_CORE_MEMC_SDRAM		0x80F
#define BCMA_CORE_OFDM			0x810
#define BCMA_CORE_EXTIF			0x811
#define BCMA_CORE_80211			0x812
#define BCMA_CORE_PHY_A			0x813
#define BCMA_CORE_PHY_B			0x814
#define BCMA_CORE_PHY_G			0x815
#define BCMA_CORE_MIPS_3302		0x816
#define BCMA_CORE_USB11_HOST		0x817
#define BCMA_CORE_USB11_DEV		0x818
#define BCMA_CORE_USB20_HOST		0x819
#define BCMA_CORE_USB20_DEV		0x81A
#define BCMA_CORE_SDIO_HOST		0x81B
#define BCMA_CORE_ROBOSWITCH		0x81C
#define BCMA_CORE_PARA_ATA		0x81D
#define BCMA_CORE_SATA_XORDMA		0x81E
#define BCMA_CORE_ETHERNET_GBIT		0x81F
#define BCMA_CORE_PCIE			0x820
#define BCMA_CORE_PHY_N			0x821
#define BCMA_CORE_SRAM_CTL		0x822
#define BCMA_CORE_MINI_MACPHY		0x823
#define BCMA_CORE_ARM_1176		0x824
#define BCMA_CORE_ARM_7TDMI		0x825
#define BCMA_CORE_PHY_LP		0x826
#define BCMA_CORE_PMU			0x827
#define BCMA_CORE_PHY_SSN		0x828
#define BCMA_CORE_SDIO_DEV		0x829
#define BCMA_CORE_ARM_CM3		0x82A
#define BCMA_CORE_PHY_HT		0x82B
#define BCMA_CORE_MIPS_74K		0x82C
#define BCMA_CORE_MAC_GBIT		0x82D
#define BCMA_CORE_DDR12_MEM_CTL		0x82E
#define BCMA_CORE_PCIE_RC		0x82F	/* PCIe Root Complex */
#define BCMA_CORE_OCP_OCP_BRIDGE	0x830
#define BCMA_CORE_SHARED_COMMON		0x831
#define BCMA_CORE_OCP_AHB_BRIDGE	0x832
#define BCMA_CORE_SPI_HOST		0x833
#define BCMA_CORE_I2S			0x834
#define BCMA_CORE_SDR_DDR1_MEM_CTL	0x835	/* SDR/DDR1 memory controller core */
#define BCMA_CORE_SHIM			0x837	/* SHIM component in ubus/6362 */
#define BCMA_CORE_PHY_AC		0x83B
#define BCMA_CORE_PCIE2			0x83C	/* PCI Express Gen2 */
#define BCMA_CORE_USB30_DEV		0x83D
#define BCMA_CORE_ARM_CR4		0x83E
#define BCMA_CORE_DEFAULT		0xFFF

#define BCMA_MAX_NR_CORES		16

/* Chip IDs of PCIe devices */
#define BCMA_CHIP_ID_BCM4313	0x4313
#define BCMA_CHIP_ID_BCM43224	43224
#define  BCMA_PKG_ID_BCM43224_FAB_CSM	0x8
#define  BCMA_PKG_ID_BCM43224_FAB_SMIC	0xa
#define BCMA_CHIP_ID_BCM43225	43225
#define BCMA_CHIP_ID_BCM43227	43227
#define BCMA_CHIP_ID_BCM43228	43228
#define BCMA_CHIP_ID_BCM43421	43421
#define BCMA_CHIP_ID_BCM43428	43428
#define BCMA_CHIP_ID_BCM43431	43431
#define BCMA_CHIP_ID_BCM43460	43460
#define BCMA_CHIP_ID_BCM4331	0x4331
#define BCMA_CHIP_ID_BCM6362	0x6362
#define BCMA_CHIP_ID_BCM4360	0x4360
#define BCMA_CHIP_ID_BCM4352	0x4352

/* Chip IDs of SoCs */
#define BCMA_CHIP_ID_BCM4706	0x5300
#define  BCMA_PKG_ID_BCM4706L	1
#define BCMA_CHIP_ID_BCM4716	0x4716
#define  BCMA_PKG_ID_BCM4716	8
#define  BCMA_PKG_ID_BCM4717	9
#define  BCMA_PKG_ID_BCM4718	10
#define BCMA_CHIP_ID_BCM47162	47162
#define BCMA_CHIP_ID_BCM4748	0x4748
#define BCMA_CHIP_ID_BCM4749	0x4749
#define BCMA_CHIP_ID_BCM5356	0x5356
#define BCMA_CHIP_ID_BCM5357	0x5357
#define  BCMA_PKG_ID_BCM5358	9
#define  BCMA_PKG_ID_BCM47186	10
#define  BCMA_PKG_ID_BCM5357	11
#define BCMA_CHIP_ID_BCM53572	53572
#define  BCMA_PKG_ID_BCM47188	9

/* Board types (on PCI usually equals to the subsystem dev id) */
/* BCM4313 */
#define BCMA_BOARD_TYPE_BCM94313BU	0X050F
#define BCMA_BOARD_TYPE_BCM94313HM	0X0510
#define BCMA_BOARD_TYPE_BCM94313EPA	0X0511
#define BCMA_BOARD_TYPE_BCM94313HMG	0X051C
/* BCM4716 */
#define BCMA_BOARD_TYPE_BCM94716NR2	0X04CD
/* BCM43224 */
#define BCMA_BOARD_TYPE_BCM943224X21	0X056E
#define BCMA_BOARD_TYPE_BCM943224X21_FCC	0X00D1
#define BCMA_BOARD_TYPE_BCM943224X21B	0X00E9
#define BCMA_BOARD_TYPE_BCM943224M93	0X008B
#define BCMA_BOARD_TYPE_BCM943224M93A	0X0090
#define BCMA_BOARD_TYPE_BCM943224X16	0X0093
#define BCMA_BOARD_TYPE_BCM94322X9	0X008D
#define BCMA_BOARD_TYPE_BCM94322M35E	0X008E
/* BCM43228 */
#define BCMA_BOARD_TYPE_BCM943228BU8	0X0540
#define BCMA_BOARD_TYPE_BCM943228BU9	0X0541
#define BCMA_BOARD_TYPE_BCM943228BU	0X0542
#define BCMA_BOARD_TYPE_BCM943227HM4L	0X0543
#define BCMA_BOARD_TYPE_BCM943227HMB	0X0544
#define BCMA_BOARD_TYPE_BCM943228HM4L	0X0545
#define BCMA_BOARD_TYPE_BCM943228SD	0X0573
/* BCM4331 */
#define BCMA_BOARD_TYPE_BCM94331X19	0X00D6
#define BCMA_BOARD_TYPE_BCM94331X28	0X00E4
#define BCMA_BOARD_TYPE_BCM94331X28B	0X010E
#define BCMA_BOARD_TYPE_BCM94331PCIEBT3AX	0X00E4
#define BCMA_BOARD_TYPE_BCM94331X12_2G	0X00EC
#define BCMA_BOARD_TYPE_BCM94331X12_5G	0X00ED
#define BCMA_BOARD_TYPE_BCM94331X29B	0X00EF
#define BCMA_BOARD_TYPE_BCM94331CSAX	0X00EF
#define BCMA_BOARD_TYPE_BCM94331X19C	0X00F5
#define BCMA_BOARD_TYPE_BCM94331X33	0X00F4
#define BCMA_BOARD_TYPE_BCM94331BU	0X0523
#define BCMA_BOARD_TYPE_BCM94331S9BU	0X0524
#define BCMA_BOARD_TYPE_BCM94331MC	0X0525
#define BCMA_BOARD_TYPE_BCM94331MCI	0X0526
#define BCMA_BOARD_TYPE_BCM94331PCIEBT4	0X0527
#define BCMA_BOARD_TYPE_BCM94331HM	0X0574
#define BCMA_BOARD_TYPE_BCM94331PCIEDUAL	0X059B
#define BCMA_BOARD_TYPE_BCM94331MCH5	0X05A9
#define BCMA_BOARD_TYPE_BCM94331CS	0X05C6
#define BCMA_BOARD_TYPE_BCM94331CD	0X05DA
/* BCM53572 */
#define BCMA_BOARD_TYPE_BCM953572BU	0X058D
#define BCMA_BOARD_TYPE_BCM953572NR2	0X058E
#define BCMA_BOARD_TYPE_BCM947188NR2	0X058F
#define BCMA_BOARD_TYPE_BCM953572SDRNR2	0X0590
/* BCM43142 */
#define BCMA_BOARD_TYPE_BCM943142HM	0X05E0

struct bcma_device {
	struct bcma_bus *bus;
	struct bcma_device_id id;

	struct device dev;
	struct device *dma_dev;

	unsigned int irq;
	bool dev_registered;

	u8 core_index;
	u8 core_unit;

	u32 addr;
	u32 addr1;
	u32 wrap;

	void __iomem *io_addr;
	void __iomem *io_wrap;

	void *drvdata;
	struct list_head list;
};

static inline void *bcma_get_drvdata(struct bcma_device *core)
{
	return core->drvdata;
}
static inline void bcma_set_drvdata(struct bcma_device *core, void *drvdata)
{
	core->drvdata = drvdata;
}

struct bcma_driver {
	const char *name;
	const struct bcma_device_id *id_table;

	int (*probe)(struct bcma_device *dev);
	void (*remove)(struct bcma_device *dev);
	int (*suspend)(struct bcma_device *dev);
	int (*resume)(struct bcma_device *dev);
	void (*shutdown)(struct bcma_device *dev);

	struct device_driver drv;
};
extern
int __bcma_driver_register(struct bcma_driver *drv, struct module *owner);
#define bcma_driver_register(drv) \
	__bcma_driver_register(drv, THIS_MODULE)

extern void bcma_driver_unregister(struct bcma_driver *drv);

/* Set a fallback SPROM.
 * See kdoc at the function definition for complete documentation. */
extern int bcma_arch_register_fallback_sprom(
		int (*sprom_callback)(struct bcma_bus *bus,
		struct ssb_sprom *out));

struct bcma_bus {
	/* The MMIO area. */
	void __iomem *mmio;

	const struct bcma_host_ops *ops;

	enum bcma_hosttype hosttype;
	union {
		/* Pointer to the PCI bus (only for BCMA_HOSTTYPE_PCI) */
		struct pci_dev *host_pci;
		/* Pointer to the SDIO device (only for BCMA_HOSTTYPE_SDIO) */
		struct sdio_func *host_sdio;
	};

	struct bcma_chipinfo chipinfo;

	struct bcma_boardinfo boardinfo;

	struct bcma_device *mapped_core;
	struct list_head cores;
	u8 nr_cores;
	u8 init_done:1;
	u8 num;

	struct bcma_drv_cc drv_cc;
	struct bcma_drv_pci drv_pci[2];
	struct bcma_drv_mips drv_mips;
	struct bcma_drv_gmac_cmn drv_gmac_cmn;

	/* We decided to share SPROM struct with SSB as long as we do not need
	 * any hacks for BCMA. This simplifies drivers code. */
	struct ssb_sprom sprom;
};

static inline u32 bcma_read8(struct bcma_device *core, u16 offset)
{
	return core->bus->ops->read8(core, offset);
}
static inline u32 bcma_read16(struct bcma_device *core, u16 offset)
{
	return core->bus->ops->read16(core, offset);
}
static inline u32 bcma_read32(struct bcma_device *core, u16 offset)
{
	return core->bus->ops->read32(core, offset);
}
static inline
void bcma_write8(struct bcma_device *core, u16 offset, u32 value)
{
	core->bus->ops->write8(core, offset, value);
}
static inline
void bcma_write16(struct bcma_device *core, u16 offset, u32 value)
{
	core->bus->ops->write16(core, offset, value);
}
static inline
void bcma_write32(struct bcma_device *core, u16 offset, u32 value)
{
	core->bus->ops->write32(core, offset, value);
}
#ifdef CONFIG_BCMA_BLOCKIO
static inline void bcma_block_read(struct bcma_device *core, void *buffer,
				   size_t count, u16 offset, u8 reg_width)
{
	core->bus->ops->block_read(core, buffer, count, offset, reg_width);
}
static inline void bcma_block_write(struct bcma_device *core,
				    const void *buffer, size_t count,
				    u16 offset, u8 reg_width)
{
	core->bus->ops->block_write(core, buffer, count, offset, reg_width);
}
#endif
static inline u32 bcma_aread32(struct bcma_device *core, u16 offset)
{
	return core->bus->ops->aread32(core, offset);
}
static inline
void bcma_awrite32(struct bcma_device *core, u16 offset, u32 value)
{
	core->bus->ops->awrite32(core, offset, value);
}

static inline void bcma_mask32(struct bcma_device *cc, u16 offset, u32 mask)
{
	bcma_write32(cc, offset, bcma_read32(cc, offset) & mask);
}
static inline void bcma_set32(struct bcma_device *cc, u16 offset, u32 set)
{
	bcma_write32(cc, offset, bcma_read32(cc, offset) | set);
}
static inline void bcma_maskset32(struct bcma_device *cc,
				  u16 offset, u32 mask, u32 set)
{
	bcma_write32(cc, offset, (bcma_read32(cc, offset) & mask) | set);
}
static inline void bcma_mask16(struct bcma_device *cc, u16 offset, u16 mask)
{
	bcma_write16(cc, offset, bcma_read16(cc, offset) & mask);
}
static inline void bcma_set16(struct bcma_device *cc, u16 offset, u16 set)
{
	bcma_write16(cc, offset, bcma_read16(cc, offset) | set);
}
static inline void bcma_maskset16(struct bcma_device *cc,
				  u16 offset, u16 mask, u16 set)
{
	bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
}

extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
extern bool bcma_core_is_enabled(struct bcma_device *core);
extern void bcma_core_disable(struct bcma_device *core, u32 flags);
extern int bcma_core_enable(struct bcma_device *core, u32 flags);
extern void bcma_core_set_clockmode(struct bcma_device *core,
				    enum bcma_clkmode clkmode);
extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
			      bool on);
extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset);
#define BCMA_DMA_TRANSLATION_MASK	0xC0000000
#define  BCMA_DMA_TRANSLATION_NONE	0x00000000
#define  BCMA_DMA_TRANSLATION_DMA32_CMT	0x40000000 /* Client Mode Translation for 32-bit DMA */
#define  BCMA_DMA_TRANSLATION_DMA64_CMT	0x80000000 /* Client Mode Translation for 64-bit DMA */
extern u32 bcma_core_dma_translation(struct bcma_device *core);

#endif /* LINUX_BCMA_H_ */
Commit	Line	Data
8369ae33 RM	1	#ifndef LINUX_BCMA_H_
	2	#define LINUX_BCMA_H_
	3
	4	#include <linux/pci.h>
	5	#include <linux/mod_devicetable.h>
	6
	7	#include <linux/bcma/bcma_driver_chipcommon.h>
	8	#include <linux/bcma/bcma_driver_pci.h>
21e0534a	9	#include <linux/bcma/bcma_driver_mips.h>
e1ac4b40	10	#include <linux/bcma/bcma_driver_gmac_cmn.h>
27f18dc2	11	#include <linux/ssb/ssb.h> /* SPROM sharing */
8369ae33	12
a1ce3928	13	#include <linux/bcma/bcma_regs.h>
8369ae33 RM	14
	15	struct bcma_device;
	16	struct bcma_bus;
	17
	18	enum bcma_hosttype {
8369ae33 RM	19	BCMA_HOSTTYPE_PCI,
8369ae33 RM	20	BCMA_HOSTTYPE_SDIO,
ecd177c2	21	BCMA_HOSTTYPE_SOC,
8369ae33 RM	22	};
	23
	24	struct bcma_chipinfo {
	25	u16 id;
	26	u8 rev;
	27	u8 pkg;
	28	};
	29
0a2fcaa7 HM	30	struct bcma_boardinfo {
	31	u16 vendor;
	32	u16 type;
	33	};
	34
7424dd0d RM	35	enum bcma_clkmode {
	36	BCMA_CLKMODE_FAST,
	37	BCMA_CLKMODE_DYNAMIC,
	38	};
	39
8369ae33 RM	40	struct bcma_host_ops {
	41	u8 (read8)(struct bcma_device core, u16 offset);
	42	u16 (read16)(struct bcma_device core, u16 offset);
	43	u32 (read32)(struct bcma_device core, u16 offset);
	44	void (write8)(struct bcma_device core, u16 offset, u8 value);
	45	void (write16)(struct bcma_device core, u16 offset, u16 value);
	46	void (write32)(struct bcma_device core, u16 offset, u32 value);
9d75ef0f RM	47	#ifdef CONFIG_BCMA_BLOCKIO
	48	void (block_read)(struct bcma_device core, void *buffer,
	49	size_t count, u16 offset, u8 reg_width);
	50	void (block_write)(struct bcma_device core, const void *buffer,
	51	size_t count, u16 offset, u8 reg_width);
	52	#endif
8369ae33 RM	53	/* Agent ops */
	54	u32 (aread32)(struct bcma_device core, u16 offset);
	55	void (awrite32)(struct bcma_device core, u16 offset, u32 value);
	56	};
	57
	58	/* Core manufacturers */
	59	#define BCMA_MANUF_ARM 0x43B
	60	#define BCMA_MANUF_MIPS 0x4A7
	61	#define BCMA_MANUF_BCM 0x4BF
	62
	63	/* Core class values. */
	64	#define BCMA_CL_SIM 0x0
	65	#define BCMA_CL_EROM 0x1
	66	#define BCMA_CL_CORESIGHT 0x9
	67	#define BCMA_CL_VERIF 0xB
	68	#define BCMA_CL_OPTIMO 0xD
	69	#define BCMA_CL_GEN 0xE
	70	#define BCMA_CL_PRIMECELL 0xF
	71
	72	/* Core-ID values. */
	73	#define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
d2bb2b9e RM	74	#define BCMA_CORE_4706_CHIPCOMMON 0x500
	75	#define BCMA_CORE_4706_SOC_RAM 0x50E
	76	#define BCMA_CORE_4706_MAC_GBIT 0x52D
	77	#define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
	78	#define BCMA_CORE_ALTA 0x534 /* I2S core */
	79	#define BCMA_CORE_4706_MAC_GBIT_COMMON 0x5DC
	80	#define BCMA_CORE_DDR23_PHY 0x5DD
8369ae33 RM	81	#define BCMA_CORE_INVALID 0x700
	82	#define BCMA_CORE_CHIPCOMMON 0x800
	83	#define BCMA_CORE_ILINE20 0x801
	84	#define BCMA_CORE_SRAM 0x802
	85	#define BCMA_CORE_SDRAM 0x803
	86	#define BCMA_CORE_PCI 0x804
	87	#define BCMA_CORE_MIPS 0x805
	88	#define BCMA_CORE_ETHERNET 0x806
	89	#define BCMA_CORE_V90 0x807
	90	#define BCMA_CORE_USB11_HOSTDEV 0x808
	91	#define BCMA_CORE_ADSL 0x809
	92	#define BCMA_CORE_ILINE100 0x80A
	93	#define BCMA_CORE_IPSEC 0x80B
	94	#define BCMA_CORE_UTOPIA 0x80C
	95	#define BCMA_CORE_PCMCIA 0x80D
	96	#define BCMA_CORE_INTERNAL_MEM 0x80E
	97	#define BCMA_CORE_MEMC_SDRAM 0x80F
	98	#define BCMA_CORE_OFDM 0x810
	99	#define BCMA_CORE_EXTIF 0x811
	100	#define BCMA_CORE_80211 0x812
	101	#define BCMA_CORE_PHY_A 0x813
	102	#define BCMA_CORE_PHY_B 0x814
	103	#define BCMA_CORE_PHY_G 0x815
	104	#define BCMA_CORE_MIPS_3302 0x816
	105	#define BCMA_CORE_USB11_HOST 0x817
	106	#define BCMA_CORE_USB11_DEV 0x818
	107	#define BCMA_CORE_USB20_HOST 0x819
	108	#define BCMA_CORE_USB20_DEV 0x81A
	109	#define BCMA_CORE_SDIO_HOST 0x81B
	110	#define BCMA_CORE_ROBOSWITCH 0x81C
	111	#define BCMA_CORE_PARA_ATA 0x81D
	112	#define BCMA_CORE_SATA_XORDMA 0x81E
	113	#define BCMA_CORE_ETHERNET_GBIT 0x81F
	114	#define BCMA_CORE_PCIE 0x820
	115	#define BCMA_CORE_PHY_N 0x821
	116	#define BCMA_CORE_SRAM_CTL 0x822
	117	#define BCMA_CORE_MINI_MACPHY 0x823
	118	#define BCMA_CORE_ARM_1176 0x824
	119	#define BCMA_CORE_ARM_7TDMI 0x825
	120	#define BCMA_CORE_PHY_LP 0x826
	121	#define BCMA_CORE_PMU 0x827
	122	#define BCMA_CORE_PHY_SSN 0x828
	123	#define BCMA_CORE_SDIO_DEV 0x829
	124	#define BCMA_CORE_ARM_CM3 0x82A
	125	#define BCMA_CORE_PHY_HT 0x82B
	126	#define BCMA_CORE_MIPS_74K 0x82C
	127	#define BCMA_CORE_MAC_GBIT 0x82D
	128	#define BCMA_CORE_DDR12_MEM_CTL 0x82E
	129	#define BCMA_CORE_PCIE_RC 0x82F /* PCIe Root Complex */
	130	#define BCMA_CORE_OCP_OCP_BRIDGE 0x830
	131	#define BCMA_CORE_SHARED_COMMON 0x831
	132	#define BCMA_CORE_OCP_AHB_BRIDGE 0x832
	133	#define BCMA_CORE_SPI_HOST 0x833
	134	#define BCMA_CORE_I2S 0x834
	135	#define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
	136	#define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
d4988d4c RM	137	#define BCMA_CORE_PHY_AC 0x83B
	138	#define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */
	139	#define BCMA_CORE_USB30_DEV 0x83D
	140	#define BCMA_CORE_ARM_CR4 0x83E
8369ae33 RM	141	#define BCMA_CORE_DEFAULT 0xFFF
	142
	143	#define BCMA_MAX_NR_CORES 16
	144
4b4f5be2 HM	145	/* Chip IDs of PCIe devices */
	146	#define BCMA_CHIP_ID_BCM4313 0x4313
	147	#define BCMA_CHIP_ID_BCM43224 43224
	148	#define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
	149	#define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
	150	#define BCMA_CHIP_ID_BCM43225 43225
	151	#define BCMA_CHIP_ID_BCM43227 43227
	152	#define BCMA_CHIP_ID_BCM43228 43228
	153	#define BCMA_CHIP_ID_BCM43421 43421
	154	#define BCMA_CHIP_ID_BCM43428 43428
	155	#define BCMA_CHIP_ID_BCM43431 43431
	156	#define BCMA_CHIP_ID_BCM43460 43460
	157	#define BCMA_CHIP_ID_BCM4331 0x4331
	158	#define BCMA_CHIP_ID_BCM6362 0x6362
	159	#define BCMA_CHIP_ID_BCM4360 0x4360
	160	#define BCMA_CHIP_ID_BCM4352 0x4352
	161
	162	/* Chip IDs of SoCs */
	163	#define BCMA_CHIP_ID_BCM4706 0x5300
0751f865	164	#define BCMA_PKG_ID_BCM4706L 1
4b4f5be2 HM	165	#define BCMA_CHIP_ID_BCM4716 0x4716
	166	#define BCMA_PKG_ID_BCM4716 8
	167	#define BCMA_PKG_ID_BCM4717 9
	168	#define BCMA_PKG_ID_BCM4718 10
	169	#define BCMA_CHIP_ID_BCM47162 47162
	170	#define BCMA_CHIP_ID_BCM4748 0x4748
	171	#define BCMA_CHIP_ID_BCM4749 0x4749
	172	#define BCMA_CHIP_ID_BCM5356 0x5356
	173	#define BCMA_CHIP_ID_BCM5357 0x5357
0751f865 HM	174	#define BCMA_PKG_ID_BCM5358 9
	175	#define BCMA_PKG_ID_BCM47186 10
	176	#define BCMA_PKG_ID_BCM5357 11
4b4f5be2	177	#define BCMA_CHIP_ID_BCM53572 53572
0751f865	178	#define BCMA_PKG_ID_BCM47188 9
4b4f5be2	179
3e699857 RM	180	/* Board types (on PCI usually equals to the subsystem dev id) */
	181	/* BCM4313 */
	182	#define BCMA_BOARD_TYPE_BCM94313BU 0X050F
	183	#define BCMA_BOARD_TYPE_BCM94313HM 0X0510
	184	#define BCMA_BOARD_TYPE_BCM94313EPA 0X0511
	185	#define BCMA_BOARD_TYPE_BCM94313HMG 0X051C
	186	/* BCM4716 */
	187	#define BCMA_BOARD_TYPE_BCM94716NR2 0X04CD
	188	/* BCM43224 */
	189	#define BCMA_BOARD_TYPE_BCM943224X21 0X056E
	190	#define BCMA_BOARD_TYPE_BCM943224X21_FCC 0X00D1
	191	#define BCMA_BOARD_TYPE_BCM943224X21B 0X00E9
	192	#define BCMA_BOARD_TYPE_BCM943224M93 0X008B
	193	#define BCMA_BOARD_TYPE_BCM943224M93A 0X0090
	194	#define BCMA_BOARD_TYPE_BCM943224X16 0X0093
	195	#define BCMA_BOARD_TYPE_BCM94322X9 0X008D
	196	#define BCMA_BOARD_TYPE_BCM94322M35E 0X008E
	197	/* BCM43228 */
	198	#define BCMA_BOARD_TYPE_BCM943228BU8 0X0540
	199	#define BCMA_BOARD_TYPE_BCM943228BU9 0X0541
	200	#define BCMA_BOARD_TYPE_BCM943228BU 0X0542
	201	#define BCMA_BOARD_TYPE_BCM943227HM4L 0X0543
	202	#define BCMA_BOARD_TYPE_BCM943227HMB 0X0544
	203	#define BCMA_BOARD_TYPE_BCM943228HM4L 0X0545
	204	#define BCMA_BOARD_TYPE_BCM943228SD 0X0573
	205	/* BCM4331 */
	206	#define BCMA_BOARD_TYPE_BCM94331X19 0X00D6
	207	#define BCMA_BOARD_TYPE_BCM94331X28 0X00E4
	208	#define BCMA_BOARD_TYPE_BCM94331X28B 0X010E
	209	#define BCMA_BOARD_TYPE_BCM94331PCIEBT3AX 0X00E4
	210	#define BCMA_BOARD_TYPE_BCM94331X12_2G 0X00EC
	211	#define BCMA_BOARD_TYPE_BCM94331X12_5G 0X00ED
	212	#define BCMA_BOARD_TYPE_BCM94331X29B 0X00EF
	213	#define BCMA_BOARD_TYPE_BCM94331CSAX 0X00EF
	214	#define BCMA_BOARD_TYPE_BCM94331X19C 0X00F5
	215	#define BCMA_BOARD_TYPE_BCM94331X33 0X00F4
	216	#define BCMA_BOARD_TYPE_BCM94331BU 0X0523
	217	#define BCMA_BOARD_TYPE_BCM94331S9BU 0X0524
	218	#define BCMA_BOARD_TYPE_BCM94331MC 0X0525
	219	#define BCMA_BOARD_TYPE_BCM94331MCI 0X0526
	220	#define BCMA_BOARD_TYPE_BCM94331PCIEBT4 0X0527
	221	#define BCMA_BOARD_TYPE_BCM94331HM 0X0574
	222	#define BCMA_BOARD_TYPE_BCM94331PCIEDUAL 0X059B
	223	#define BCMA_BOARD_TYPE_BCM94331MCH5 0X05A9
	224	#define BCMA_BOARD_TYPE_BCM94331CS 0X05C6
	225	#define BCMA_BOARD_TYPE_BCM94331CD 0X05DA
	226	/* BCM53572 */
	227	#define BCMA_BOARD_TYPE_BCM953572BU 0X058D
	228	#define BCMA_BOARD_TYPE_BCM953572NR2 0X058E
	229	#define BCMA_BOARD_TYPE_BCM947188NR2 0X058F
	230	#define BCMA_BOARD_TYPE_BCM953572SDRNR2 0X0590
	231	/* BCM43142 */
	232	#define BCMA_BOARD_TYPE_BCM943142HM 0X05E0
	233
8369ae33 RM	234	struct bcma_device {
	235	struct bcma_bus *bus;
	236	struct bcma_device_id id;
	237
	238	struct device dev;
1bdcd095	239	struct device *dma_dev;
21e0534a	240
1bdcd095	241	unsigned int irq;
8369ae33 RM	242	bool dev_registered;
	243
	244	u8 core_index;
5f2d6171	245	u8 core_unit;
8369ae33 RM	246
8369ae33 RM	247	u32 addr;
e167d9fb	248	u32 addr1;
8369ae33 RM	249	u32 wrap;
8369ae33 RM	250
ecd177c2 HM	251	void __iomem *io_addr;
	252	void __iomem *io_wrap;
	253
8369ae33 RM	254	void *drvdata;
	255	struct list_head list;
	256	};
	257
	258	static inline void bcma_get_drvdata(struct bcma_device core)
	259	{
	260	return core->drvdata;
	261	}
	262	static inline void bcma_set_drvdata(struct bcma_device core, void drvdata)
	263	{
	264	core->drvdata = drvdata;
	265	}
	266
	267	struct bcma_driver {
	268	const char *name;
	269	const struct bcma_device_id *id_table;
	270
	271	int (probe)(struct bcma_device dev);
	272	void (remove)(struct bcma_device dev);
7d5869e7	273	int (suspend)(struct bcma_device dev);
8369ae33 RM	274	int (resume)(struct bcma_device dev);
	275	void (shutdown)(struct bcma_device dev);
	276
	277	struct device_driver drv;
	278	};
	279	extern
	280	int __bcma_driver_register(struct bcma_driver drv, struct module owner);
eb5589a8 PG	281	#define bcma_driver_register(drv) \
	282	__bcma_driver_register(drv, THIS_MODULE)
	283
8369ae33 RM	284	extern void bcma_driver_unregister(struct bcma_driver *drv);
8369ae33 RM	285
a027237a HM	286	/* Set a fallback SPROM.
	287	* See kdoc at the function definition for complete documentation. */
	288	extern int bcma_arch_register_fallback_sprom(
	289	int (sprom_callback)(struct bcma_bus bus,
	290	struct ssb_sprom *out));
	291
8369ae33 RM	292	struct bcma_bus {
	293	/* The MMIO area. */
	294	void __iomem *mmio;
	295
	296	const struct bcma_host_ops *ops;
	297
	298	enum bcma_hosttype hosttype;
	299	union {
	300	/* Pointer to the PCI bus (only for BCMA_HOSTTYPE_PCI) */
	301	struct pci_dev *host_pci;
	302	/* Pointer to the SDIO device (only for BCMA_HOSTTYPE_SDIO) */
	303	struct sdio_func *host_sdio;
	304	};
	305
	306	struct bcma_chipinfo chipinfo;
	307
0a2fcaa7 HM	308	struct bcma_boardinfo boardinfo;
0a2fcaa7 HM	309
8369ae33 RM	310	struct bcma_device *mapped_core;
	311	struct list_head cores;
	312	u8 nr_cores;
517f43e5	313	u8 init_done:1;
8f9ada4f	314	u8 num;
8369ae33 RM	315
8369ae33 RM	316	struct bcma_drv_cc drv_cc;
dfae7143	317	struct bcma_drv_pci drv_pci[2];
21e0534a	318	struct bcma_drv_mips drv_mips;
e1ac4b40	319	struct bcma_drv_gmac_cmn drv_gmac_cmn;
27f18dc2 RM	320
	321	/* We decided to share SPROM struct with SSB as long as we do not need
	322	* any hacks for BCMA. This simplifies drivers code. */
	323	struct ssb_sprom sprom;
8369ae33 RM	324	};
8369ae33 RM	325
08445552	326	static inline u32 bcma_read8(struct bcma_device *core, u16 offset)
8369ae33 RM	327	{
	328	return core->bus->ops->read8(core, offset);
	329	}
08445552	330	static inline u32 bcma_read16(struct bcma_device *core, u16 offset)
8369ae33 RM	331	{
	332	return core->bus->ops->read16(core, offset);
	333	}
08445552	334	static inline u32 bcma_read32(struct bcma_device *core, u16 offset)
8369ae33 RM	335	{
	336	return core->bus->ops->read32(core, offset);
	337	}
08445552	338	static inline
8369ae33 RM	339	void bcma_write8(struct bcma_device *core, u16 offset, u32 value)
	340	{
	341	core->bus->ops->write8(core, offset, value);
	342	}
08445552	343	static inline
8369ae33 RM	344	void bcma_write16(struct bcma_device *core, u16 offset, u32 value)
	345	{
	346	core->bus->ops->write16(core, offset, value);
	347	}
08445552	348	static inline
8369ae33 RM	349	void bcma_write32(struct bcma_device *core, u16 offset, u32 value)
	350	{
	351	core->bus->ops->write32(core, offset, value);
	352	}
9d75ef0f	353	#ifdef CONFIG_BCMA_BLOCKIO
08445552	354	static inline void bcma_block_read(struct bcma_device core, void buffer,
9d75ef0f RM	355	size_t count, u16 offset, u8 reg_width)
	356	{
	357	core->bus->ops->block_read(core, buffer, count, offset, reg_width);
	358	}
08445552 AS	359	static inline void bcma_block_write(struct bcma_device *core,
	360	const void *buffer, size_t count,
	361	u16 offset, u8 reg_width)
9d75ef0f RM	362	{
	363	core->bus->ops->block_write(core, buffer, count, offset, reg_width);
	364	}
	365	#endif
08445552	366	static inline u32 bcma_aread32(struct bcma_device *core, u16 offset)
8369ae33 RM	367	{
	368	return core->bus->ops->aread32(core, offset);
	369	}
08445552	370	static inline
8369ae33 RM	371	void bcma_awrite32(struct bcma_device *core, u16 offset, u32 value)
	372	{
	373	core->bus->ops->awrite32(core, offset, value);
	374	}
	375
9d08f10d AS	376	static inline void bcma_mask32(struct bcma_device *cc, u16 offset, u32 mask)
	377	{
	378	bcma_write32(cc, offset, bcma_read32(cc, offset) & mask);
	379	}
	380	static inline void bcma_set32(struct bcma_device *cc, u16 offset, u32 set)
	381	{
	382	bcma_write32(cc, offset, bcma_read32(cc, offset) \| set);
	383	}
	384	static inline void bcma_maskset32(struct bcma_device *cc,
	385	u16 offset, u32 mask, u32 set)
	386	{
	387	bcma_write32(cc, offset, (bcma_read32(cc, offset) & mask) \| set);
	388	}
	389	static inline void bcma_mask16(struct bcma_device *cc, u16 offset, u16 mask)
	390	{
	391	bcma_write16(cc, offset, bcma_read16(cc, offset) & mask);
	392	}
	393	static inline void bcma_set16(struct bcma_device *cc, u16 offset, u16 set)
	394	{
	395	bcma_write16(cc, offset, bcma_read16(cc, offset) \| set);
	396	}
	397	static inline void bcma_maskset16(struct bcma_device *cc,
	398	u16 offset, u16 mask, u16 set)
	399	{
	400	bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) \| set);
	401	}
3de1a774	402
1c9351cf	403	extern struct bcma_device bcma_find_core(struct bcma_bus bus, u16 coreid);
8369ae33	404	extern bool bcma_core_is_enabled(struct bcma_device *core);
e3ae0cac	405	extern void bcma_core_disable(struct bcma_device *core, u32 flags);
8369ae33	406	extern int bcma_core_enable(struct bcma_device *core, u32 flags);
7424dd0d RM	407	extern void bcma_core_set_clockmode(struct bcma_device *core,
7424dd0d RM	408	enum bcma_clkmode clkmode);
6f53912f RM	409	extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
6f53912f RM	410	bool on);
8d4b9e31	411	extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset);
05aec233 RM	412	#define BCMA_DMA_TRANSLATION_MASK 0xC0000000
	413	#define BCMA_DMA_TRANSLATION_NONE 0x00000000
	414	#define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */
	415	#define BCMA_DMA_TRANSLATION_DMA64_CMT 0x80000000 /* Client Mode Translation for 64-bit DMA */
	416	extern u32 bcma_core_dma_translation(struct bcma_device *core);
3de1a774	417
8369ae33	418	#endif /* LINUX_BCMA_H_ */