[mirror_ubuntu-jammy-kernel.git] / include / linux / cacheinfo.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _LINUX_CACHEINFO_H
#define _LINUX_CACHEINFO_H

#include <linux/bitops.h>
#include <linux/cpu.h>
#include <linux/cpumask.h>
#include <linux/smp.h>

struct device_node;
struct attribute;

enum cache_type {
	CACHE_TYPE_NOCACHE = 0,
	CACHE_TYPE_INST = BIT(0),
	CACHE_TYPE_DATA = BIT(1),
	CACHE_TYPE_SEPARATE = CACHE_TYPE_INST | CACHE_TYPE_DATA,
	CACHE_TYPE_UNIFIED = BIT(2),
};

extern unsigned int coherency_max_size;

/**
 * struct cacheinfo - represent a cache leaf node
 * @id: This cache's id. It is unique among caches with the same (type, level).
 * @type: type of the cache - data, inst or unified
 * @level: represents the hierarchy in the multi-level cache
 * @coherency_line_size: size of each cache line usually representing
 *	the minimum amount of data that gets transferred from memory
 * @number_of_sets: total number of sets, a set is a collection of cache
 *	lines sharing the same index
 * @ways_of_associativity: number of ways in which a particular memory
 *	block can be placed in the cache
 * @physical_line_partition: number of physical cache lines sharing the
 *	same cachetag
 * @size: Total size of the cache
 * @shared_cpu_map: logical cpumask representing all the cpus sharing
 *	this cache node
 * @attributes: bitfield representing various cache attributes
 * @fw_token: Unique value used to determine if different cacheinfo
 *	structures represent a single hardware cache instance.
 * @disable_sysfs: indicates whether this node is visible to the user via
 *	sysfs or not
 * @priv: pointer to any private data structure specific to particular
 *	cache design
 *
 * While @of_node, @disable_sysfs and @priv are used for internal book
 * keeping, the remaining members form the core properties of the cache
 */
struct cacheinfo {
	unsigned int id;
	enum cache_type type;
	unsigned int level;
	unsigned int coherency_line_size;
	unsigned int number_of_sets;
	unsigned int ways_of_associativity;
	unsigned int physical_line_partition;
	unsigned int size;
	cpumask_t shared_cpu_map;
	unsigned int attributes;
#define CACHE_WRITE_THROUGH	BIT(0)
#define CACHE_WRITE_BACK	BIT(1)
#define CACHE_WRITE_POLICY_MASK		\
	(CACHE_WRITE_THROUGH | CACHE_WRITE_BACK)
#define CACHE_READ_ALLOCATE	BIT(2)
#define CACHE_WRITE_ALLOCATE	BIT(3)
#define CACHE_ALLOCATE_POLICY_MASK	\
	(CACHE_READ_ALLOCATE | CACHE_WRITE_ALLOCATE)
#define CACHE_ID		BIT(4)
	void *fw_token;
	bool disable_sysfs;
	void *priv;
};

struct cpu_cacheinfo {
	struct cacheinfo *info_list;
	unsigned int num_levels;
	unsigned int num_leaves;
	bool cpu_map_populated;
};

/*
 * Helpers to make sure "func" is executed on the cpu whose cache
 * attributes are being detected
 */
#define DEFINE_SMP_CALL_CACHE_FUNCTION(func)			\
static inline void _##func(void *ret)				\
{								\
	int cpu = smp_processor_id();				\
	*(int *)ret = __##func(cpu);				\
}								\
								\
int func(unsigned int cpu)					\
{								\
	int ret;						\
	smp_call_function_single(cpu, _##func, &ret, true);	\
	return ret;						\
}

struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu);
int init_cache_level(unsigned int cpu);
int populate_cache_leaves(unsigned int cpu);
int cache_setup_acpi(unsigned int cpu);
#ifndef CONFIG_ACPI_PPTT
/*
 * acpi_find_last_cache_level is only called on ACPI enabled
 * platforms using the PPTT for topology. This means that if
 * the platform supports other firmware configuration methods
 * we need to stub out the call when ACPI is disabled.
 * ACPI enabled platforms not using PPTT won't be making calls
 * to this function so we need not worry about them.
 */
static inline int acpi_find_last_cache_level(unsigned int cpu)
{
	return 0;
}
#else
int acpi_find_last_cache_level(unsigned int cpu);
#endif

const struct attribute_group *cache_get_priv_group(struct cacheinfo *this_leaf);

/*
 * Get the id of the cache associated with @cpu at level @level.
 * cpuhp lock must be held.
 */
static inline int get_cpu_cacheinfo_id(int cpu, int level)
{
	struct cpu_cacheinfo *ci = get_cpu_cacheinfo(cpu);
	int i;

	for (i = 0; i < ci->num_leaves; i++) {
		if (ci->info_list[i].level == level) {
			if (ci->info_list[i].attributes & CACHE_ID)
				return ci->info_list[i].id;
			return -1;
		}
	}

	return -1;
}

#endif /* _LINUX_CACHEINFO_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
246246cb SH	2	#ifndef _LINUX_CACHEINFO_H
	3	#define _LINUX_CACHEINFO_H
	4
	5	#include <linux/bitops.h>
709c4362	6	#include <linux/cpu.h>
246246cb SH	7	#include <linux/cpumask.h>
	8	#include <linux/smp.h>
	9
	10	struct device_node;
	11	struct attribute;
	12
	13	enum cache_type {
	14	CACHE_TYPE_NOCACHE = 0,
	15	CACHE_TYPE_INST = BIT(0),
	16	CACHE_TYPE_DATA = BIT(1),
	17	CACHE_TYPE_SEPARATE = CACHE_TYPE_INST \| CACHE_TYPE_DATA,
	18	CACHE_TYPE_UNIFIED = BIT(2),
	19	};
	20
9a83c84c SZ	21	extern unsigned int coherency_max_size;
9a83c84c SZ	22
246246cb SH	23	/**
246246cb SH	24	* struct cacheinfo - represent a cache leaf node
e9a2ea5a	25	* @id: This cache's id. It is unique among caches with the same (type, level).
246246cb	26	* @type: type of the cache - data, inst or unified
2539b258	27	* @level: represents the hierarchy in the multi-level cache
246246cb SH	28	* @coherency_line_size: size of each cache line usually representing
	29	* the minimum amount of data that gets transferred from memory
	30	* @number_of_sets: total number of sets, a set is a collection of cache
	31	* lines sharing the same index
	32	* @ways_of_associativity: number of ways in which a particular memory
	33	* block can be placed in the cache
	34	* @physical_line_partition: number of physical cache lines sharing the
	35	* same cachetag
	36	* @size: Total size of the cache
	37	* @shared_cpu_map: logical cpumask representing all the cpus sharing
	38	* this cache node
	39	* @attributes: bitfield representing various cache attributes
9b97387c JL	40	* @fw_token: Unique value used to determine if different cacheinfo
9b97387c JL	41	* structures represent a single hardware cache instance.
246246cb SH	42	* @disable_sysfs: indicates whether this node is visible to the user via
	43	* sysfs or not
	44	* @priv: pointer to any private data structure specific to particular
	45	* cache design
	46	*
	47	* While @of_node, @disable_sysfs and @priv are used for internal book
	48	* keeping, the remaining members form the core properties of the cache
	49	*/
	50	struct cacheinfo {
e9a2ea5a	51	unsigned int id;
246246cb SH	52	enum cache_type type;
	53	unsigned int level;
	54	unsigned int coherency_line_size;
	55	unsigned int number_of_sets;
	56	unsigned int ways_of_associativity;
	57	unsigned int physical_line_partition;
	58	unsigned int size;
	59	cpumask_t shared_cpu_map;
	60	unsigned int attributes;
	61	#define CACHE_WRITE_THROUGH BIT(0)
	62	#define CACHE_WRITE_BACK BIT(1)
	63	#define CACHE_WRITE_POLICY_MASK \
	64	(CACHE_WRITE_THROUGH \| CACHE_WRITE_BACK)
	65	#define CACHE_READ_ALLOCATE BIT(2)
	66	#define CACHE_WRITE_ALLOCATE BIT(3)
	67	#define CACHE_ALLOCATE_POLICY_MASK \
	68	(CACHE_READ_ALLOCATE \| CACHE_WRITE_ALLOCATE)
e9a2ea5a	69	#define CACHE_ID BIT(4)
9b97387c	70	void *fw_token;
246246cb SH	71	bool disable_sysfs;
	72	void *priv;
	73	};
	74
	75	struct cpu_cacheinfo {
	76	struct cacheinfo *info_list;
	77	unsigned int num_levels;
	78	unsigned int num_leaves;
fac51482	79	bool cpu_map_populated;
246246cb SH	80	};
	81
	82	/*
	83	* Helpers to make sure "func" is executed on the cpu whose cache
	84	* attributes are being detected
	85	*/
	86	#define DEFINE_SMP_CALL_CACHE_FUNCTION(func) \
	87	static inline void _##func(void *ret) \
	88	{ \
	89	int cpu = smp_processor_id(); \
	90	(int )ret = __##func(cpu); \
	91	} \
	92	\
	93	int func(unsigned int cpu) \
	94	{ \
	95	int ret; \
	96	smp_call_function_single(cpu, _##func, &ret, true); \
	97	return ret; \
	98	}
	99
	100	struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu);
	101	int init_cache_level(unsigned int cpu);
	102	int populate_cache_leaves(unsigned int cpu);
582b468b	103	int cache_setup_acpi(unsigned int cpu);
2520e627	104	#ifndef CONFIG_ACPI_PPTT
582b468b JL	105	/*
	106	* acpi_find_last_cache_level is only called on ACPI enabled
	107	* platforms using the PPTT for topology. This means that if
	108	* the platform supports other firmware configuration methods
	109	* we need to stub out the call when ACPI is disabled.
	110	* ACPI enabled platforms not using PPTT won't be making calls
	111	* to this function so we need not worry about them.
	112	*/
	113	static inline int acpi_find_last_cache_level(unsigned int cpu)
	114	{
	115	return 0;
	116	}
	117	#else
	118	int acpi_find_last_cache_level(unsigned int cpu);
	119	#endif
246246cb SH	120
	121	const struct attribute_group cache_get_priv_group(struct cacheinfo this_leaf);
	122
709c4362 JM	123	/*
	124	* Get the id of the cache associated with @cpu at level @level.
	125	* cpuhp lock must be held.
	126	*/
	127	static inline int get_cpu_cacheinfo_id(int cpu, int level)
	128	{
	129	struct cpu_cacheinfo *ci = get_cpu_cacheinfo(cpu);
	130	int i;
	131
	132	for (i = 0; i < ci->num_leaves; i++) {
	133	if (ci->info_list[i].level == level) {
	134	if (ci->info_list[i].attributes & CACHE_ID)
	135	return ci->info_list[i].id;
	136	return -1;
	137	}
	138	}
	139
	140	return -1;
	141	}
	142
246246cb	143	#endif /* _LINUX_CACHEINFO_H */