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b2476490 MT |
1 | /* |
2 | * linux/include/linux/clk-provider.h | |
3 | * | |
4 | * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> | |
5 | * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #ifndef __LINUX_CLK_PROVIDER_H | |
12 | #define __LINUX_CLK_PROVIDER_H | |
13 | ||
aa514ce3 | 14 | #include <linux/io.h> |
355bb165 | 15 | #include <linux/of.h> |
b2476490 MT |
16 | |
17 | #ifdef CONFIG_COMMON_CLK | |
18 | ||
b2476490 MT |
19 | /* |
20 | * flags used across common struct clk. these flags should only affect the | |
21 | * top-level framework. custom flags for dealing with hardware specifics | |
22 | * belong in struct clk_foo | |
23 | */ | |
24 | #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ | |
25 | #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ | |
26 | #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ | |
27 | #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ | |
47b0eeb3 | 28 | #define CLK_IS_ROOT BIT(4) /* Deprecated: Don't use */ |
f7d8caad | 29 | #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ |
a093bde2 | 30 | #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ |
819c1de3 | 31 | #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ |
5279fc40 | 32 | #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ |
d8d91987 | 33 | #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ |
2eb8c710 | 34 | #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ |
b2476490 | 35 | |
61ae7656 | 36 | struct clk; |
0197b3ea | 37 | struct clk_hw; |
035a61c3 | 38 | struct clk_core; |
c646cbf1 | 39 | struct dentry; |
0197b3ea | 40 | |
0817b62c BB |
41 | /** |
42 | * struct clk_rate_request - Structure encoding the clk constraints that | |
43 | * a clock user might require. | |
44 | * | |
45 | * @rate: Requested clock rate. This field will be adjusted by | |
46 | * clock drivers according to hardware capabilities. | |
47 | * @min_rate: Minimum rate imposed by clk users. | |
1971dfb7 | 48 | * @max_rate: Maximum rate imposed by clk users. |
0817b62c BB |
49 | * @best_parent_rate: The best parent rate a parent can provide to fulfill the |
50 | * requested constraints. | |
51 | * @best_parent_hw: The most appropriate parent clock that fulfills the | |
52 | * requested constraints. | |
53 | * | |
54 | */ | |
55 | struct clk_rate_request { | |
56 | unsigned long rate; | |
57 | unsigned long min_rate; | |
58 | unsigned long max_rate; | |
59 | unsigned long best_parent_rate; | |
60 | struct clk_hw *best_parent_hw; | |
61 | }; | |
62 | ||
b2476490 MT |
63 | /** |
64 | * struct clk_ops - Callback operations for hardware clocks; these are to | |
65 | * be provided by the clock implementation, and will be called by drivers | |
66 | * through the clk_* api. | |
67 | * | |
68 | * @prepare: Prepare the clock for enabling. This must not return until | |
725b418b GU |
69 | * the clock is fully prepared, and it's safe to call clk_enable. |
70 | * This callback is intended to allow clock implementations to | |
71 | * do any initialisation that may sleep. Called with | |
72 | * prepare_lock held. | |
b2476490 MT |
73 | * |
74 | * @unprepare: Release the clock from its prepared state. This will typically | |
725b418b GU |
75 | * undo any work done in the @prepare callback. Called with |
76 | * prepare_lock held. | |
b2476490 | 77 | * |
3d6ee287 UH |
78 | * @is_prepared: Queries the hardware to determine if the clock is prepared. |
79 | * This function is allowed to sleep. Optional, if this op is not | |
80 | * set then the prepare count will be used. | |
81 | * | |
3cc8247f UH |
82 | * @unprepare_unused: Unprepare the clock atomically. Only called from |
83 | * clk_disable_unused for prepare clocks with special needs. | |
84 | * Called with prepare mutex held. This function may sleep. | |
85 | * | |
b2476490 | 86 | * @enable: Enable the clock atomically. This must not return until the |
725b418b GU |
87 | * clock is generating a valid clock signal, usable by consumer |
88 | * devices. Called with enable_lock held. This function must not | |
89 | * sleep. | |
b2476490 MT |
90 | * |
91 | * @disable: Disable the clock atomically. Called with enable_lock held. | |
725b418b | 92 | * This function must not sleep. |
b2476490 | 93 | * |
119c7127 | 94 | * @is_enabled: Queries the hardware to determine if the clock is enabled. |
725b418b GU |
95 | * This function must not sleep. Optional, if this op is not |
96 | * set then the enable count will be used. | |
119c7127 | 97 | * |
7c045a55 MT |
98 | * @disable_unused: Disable the clock atomically. Only called from |
99 | * clk_disable_unused for gate clocks with special needs. | |
100 | * Called with enable_lock held. This function must not | |
101 | * sleep. | |
102 | * | |
7ce3e8cc | 103 | * @recalc_rate Recalculate the rate of this clock, by querying hardware. The |
725b418b GU |
104 | * parent rate is an input parameter. It is up to the caller to |
105 | * ensure that the prepare_mutex is held across this call. | |
106 | * Returns the calculated rate. Optional, but recommended - if | |
107 | * this op is not set then clock rate will be initialized to 0. | |
b2476490 MT |
108 | * |
109 | * @round_rate: Given a target rate as input, returns the closest rate actually | |
54e73016 GU |
110 | * supported by the clock. The parent rate is an input/output |
111 | * parameter. | |
b2476490 | 112 | * |
71472c0c JH |
113 | * @determine_rate: Given a target rate as input, returns the closest rate |
114 | * actually supported by the clock, and optionally the parent clock | |
115 | * that should be used to provide the clock rate. | |
116 | * | |
b2476490 | 117 | * @set_parent: Change the input source of this clock; for clocks with multiple |
54e73016 GU |
118 | * possible parents specify a new parent by passing in the index |
119 | * as a u8 corresponding to the parent in either the .parent_names | |
120 | * or .parents arrays. This function in affect translates an | |
121 | * array index into the value programmed into the hardware. | |
122 | * Returns 0 on success, -EERROR otherwise. | |
123 | * | |
b2476490 | 124 | * @get_parent: Queries the hardware to determine the parent of a clock. The |
725b418b GU |
125 | * return value is a u8 which specifies the index corresponding to |
126 | * the parent clock. This index can be applied to either the | |
127 | * .parent_names or .parents arrays. In short, this function | |
128 | * translates the parent value read from hardware into an array | |
129 | * index. Currently only called when the clock is initialized by | |
130 | * __clk_init. This callback is mandatory for clocks with | |
131 | * multiple parents. It is optional (and unnecessary) for clocks | |
132 | * with 0 or 1 parents. | |
b2476490 | 133 | * |
1c0035d7 SG |
134 | * @set_rate: Change the rate of this clock. The requested rate is specified |
135 | * by the second argument, which should typically be the return | |
136 | * of .round_rate call. The third argument gives the parent rate | |
137 | * which is likely helpful for most .set_rate implementation. | |
138 | * Returns 0 on success, -EERROR otherwise. | |
b2476490 | 139 | * |
3fa2252b SB |
140 | * @set_rate_and_parent: Change the rate and the parent of this clock. The |
141 | * requested rate is specified by the second argument, which | |
142 | * should typically be the return of .round_rate call. The | |
143 | * third argument gives the parent rate which is likely helpful | |
144 | * for most .set_rate_and_parent implementation. The fourth | |
145 | * argument gives the parent index. This callback is optional (and | |
146 | * unnecessary) for clocks with 0 or 1 parents as well as | |
147 | * for clocks that can tolerate switching the rate and the parent | |
148 | * separately via calls to .set_parent and .set_rate. | |
149 | * Returns 0 on success, -EERROR otherwise. | |
150 | * | |
54e73016 GU |
151 | * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy |
152 | * is expressed in ppb (parts per billion). The parent accuracy is | |
153 | * an input parameter. | |
154 | * Returns the calculated accuracy. Optional - if this op is not | |
155 | * set then clock accuracy will be initialized to parent accuracy | |
156 | * or 0 (perfect clock) if clock has no parent. | |
157 | * | |
9824cf73 MR |
158 | * @get_phase: Queries the hardware to get the current phase of a clock. |
159 | * Returned values are 0-359 degrees on success, negative | |
160 | * error codes on failure. | |
161 | * | |
e59c5371 MT |
162 | * @set_phase: Shift the phase this clock signal in degrees specified |
163 | * by the second argument. Valid values for degrees are | |
164 | * 0-359. Return 0 on success, otherwise -EERROR. | |
165 | * | |
54e73016 GU |
166 | * @init: Perform platform-specific initialization magic. |
167 | * This is not not used by any of the basic clock types. | |
168 | * Please consider other ways of solving initialization problems | |
169 | * before using this callback, as its use is discouraged. | |
170 | * | |
c646cbf1 AE |
171 | * @debug_init: Set up type-specific debugfs entries for this clock. This |
172 | * is called once, after the debugfs directory entry for this | |
173 | * clock has been created. The dentry pointer representing that | |
174 | * directory is provided as an argument. Called with | |
175 | * prepare_lock held. Returns 0 on success, -EERROR otherwise. | |
176 | * | |
3fa2252b | 177 | * |
b2476490 MT |
178 | * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow |
179 | * implementations to split any work between atomic (enable) and sleepable | |
180 | * (prepare) contexts. If enabling a clock requires code that might sleep, | |
181 | * this must be done in clk_prepare. Clock enable code that will never be | |
7ce3e8cc | 182 | * called in a sleepable context may be implemented in clk_enable. |
b2476490 MT |
183 | * |
184 | * Typically, drivers will call clk_prepare when a clock may be needed later | |
185 | * (eg. when a device is opened), and clk_enable when the clock is actually | |
186 | * required (eg. from an interrupt). Note that clk_prepare MUST have been | |
187 | * called before clk_enable. | |
188 | */ | |
189 | struct clk_ops { | |
190 | int (*prepare)(struct clk_hw *hw); | |
191 | void (*unprepare)(struct clk_hw *hw); | |
3d6ee287 | 192 | int (*is_prepared)(struct clk_hw *hw); |
3cc8247f | 193 | void (*unprepare_unused)(struct clk_hw *hw); |
b2476490 MT |
194 | int (*enable)(struct clk_hw *hw); |
195 | void (*disable)(struct clk_hw *hw); | |
196 | int (*is_enabled)(struct clk_hw *hw); | |
7c045a55 | 197 | void (*disable_unused)(struct clk_hw *hw); |
b2476490 MT |
198 | unsigned long (*recalc_rate)(struct clk_hw *hw, |
199 | unsigned long parent_rate); | |
54e73016 GU |
200 | long (*round_rate)(struct clk_hw *hw, unsigned long rate, |
201 | unsigned long *parent_rate); | |
0817b62c BB |
202 | int (*determine_rate)(struct clk_hw *hw, |
203 | struct clk_rate_request *req); | |
b2476490 MT |
204 | int (*set_parent)(struct clk_hw *hw, u8 index); |
205 | u8 (*get_parent)(struct clk_hw *hw); | |
54e73016 GU |
206 | int (*set_rate)(struct clk_hw *hw, unsigned long rate, |
207 | unsigned long parent_rate); | |
3fa2252b SB |
208 | int (*set_rate_and_parent)(struct clk_hw *hw, |
209 | unsigned long rate, | |
210 | unsigned long parent_rate, u8 index); | |
5279fc40 BB |
211 | unsigned long (*recalc_accuracy)(struct clk_hw *hw, |
212 | unsigned long parent_accuracy); | |
9824cf73 | 213 | int (*get_phase)(struct clk_hw *hw); |
e59c5371 | 214 | int (*set_phase)(struct clk_hw *hw, int degrees); |
b2476490 | 215 | void (*init)(struct clk_hw *hw); |
c646cbf1 | 216 | int (*debug_init)(struct clk_hw *hw, struct dentry *dentry); |
b2476490 MT |
217 | }; |
218 | ||
0197b3ea SK |
219 | /** |
220 | * struct clk_init_data - holds init data that's common to all clocks and is | |
221 | * shared between the clock provider and the common clock framework. | |
222 | * | |
223 | * @name: clock name | |
224 | * @ops: operations this clock supports | |
225 | * @parent_names: array of string names for all possible parents | |
226 | * @num_parents: number of possible parents | |
227 | * @flags: framework-level hints and quirks | |
228 | */ | |
229 | struct clk_init_data { | |
230 | const char *name; | |
231 | const struct clk_ops *ops; | |
2893c379 | 232 | const char * const *parent_names; |
0197b3ea SK |
233 | u8 num_parents; |
234 | unsigned long flags; | |
235 | }; | |
236 | ||
237 | /** | |
238 | * struct clk_hw - handle for traversing from a struct clk to its corresponding | |
239 | * hardware-specific structure. struct clk_hw should be declared within struct | |
240 | * clk_foo and then referenced by the struct clk instance that uses struct | |
241 | * clk_foo's clk_ops | |
242 | * | |
035a61c3 TV |
243 | * @core: pointer to the struct clk_core instance that points back to this |
244 | * struct clk_hw instance | |
245 | * | |
246 | * @clk: pointer to the per-user struct clk instance that can be used to call | |
247 | * into the clk API | |
0197b3ea SK |
248 | * |
249 | * @init: pointer to struct clk_init_data that contains the init data shared | |
250 | * with the common clock framework. | |
251 | */ | |
252 | struct clk_hw { | |
035a61c3 | 253 | struct clk_core *core; |
0197b3ea | 254 | struct clk *clk; |
dc4cd941 | 255 | const struct clk_init_data *init; |
0197b3ea SK |
256 | }; |
257 | ||
9d9f78ed MT |
258 | /* |
259 | * DOC: Basic clock implementations common to many platforms | |
260 | * | |
261 | * Each basic clock hardware type is comprised of a structure describing the | |
262 | * clock hardware, implementations of the relevant callbacks in struct clk_ops, | |
263 | * unique flags for that hardware type, a registration function and an | |
264 | * alternative macro for static initialization | |
265 | */ | |
266 | ||
267 | /** | |
268 | * struct clk_fixed_rate - fixed-rate clock | |
269 | * @hw: handle between common and hardware-specific interfaces | |
270 | * @fixed_rate: constant frequency of clock | |
271 | */ | |
272 | struct clk_fixed_rate { | |
273 | struct clk_hw hw; | |
274 | unsigned long fixed_rate; | |
0903ea60 | 275 | unsigned long fixed_accuracy; |
9d9f78ed MT |
276 | u8 flags; |
277 | }; | |
278 | ||
5fd9c05c GT |
279 | #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw) |
280 | ||
bffad66e | 281 | extern const struct clk_ops clk_fixed_rate_ops; |
9d9f78ed MT |
282 | struct clk *clk_register_fixed_rate(struct device *dev, const char *name, |
283 | const char *parent_name, unsigned long flags, | |
284 | unsigned long fixed_rate); | |
0903ea60 BB |
285 | struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, |
286 | const char *name, const char *parent_name, unsigned long flags, | |
287 | unsigned long fixed_rate, unsigned long fixed_accuracy); | |
0b225e41 | 288 | void clk_unregister_fixed_rate(struct clk *clk); |
015ba402 GL |
289 | void of_fixed_clk_setup(struct device_node *np); |
290 | ||
9d9f78ed MT |
291 | /** |
292 | * struct clk_gate - gating clock | |
293 | * | |
294 | * @hw: handle between common and hardware-specific interfaces | |
295 | * @reg: register controlling gate | |
296 | * @bit_idx: single bit controlling gate | |
297 | * @flags: hardware-specific flags | |
298 | * @lock: register lock | |
299 | * | |
300 | * Clock which can gate its output. Implements .enable & .disable | |
301 | * | |
302 | * Flags: | |
1f73f31a | 303 | * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to |
725b418b GU |
304 | * enable the clock. Setting this flag does the opposite: setting the bit |
305 | * disable the clock and clearing it enables the clock | |
04577994 | 306 | * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit |
725b418b GU |
307 | * of this register, and mask of gate bits are in higher 16-bit of this |
308 | * register. While setting the gate bits, higher 16-bit should also be | |
309 | * updated to indicate changing gate bits. | |
9d9f78ed MT |
310 | */ |
311 | struct clk_gate { | |
312 | struct clk_hw hw; | |
313 | void __iomem *reg; | |
314 | u8 bit_idx; | |
315 | u8 flags; | |
316 | spinlock_t *lock; | |
9d9f78ed MT |
317 | }; |
318 | ||
5fd9c05c GT |
319 | #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) |
320 | ||
9d9f78ed | 321 | #define CLK_GATE_SET_TO_DISABLE BIT(0) |
04577994 | 322 | #define CLK_GATE_HIWORD_MASK BIT(1) |
9d9f78ed | 323 | |
bffad66e | 324 | extern const struct clk_ops clk_gate_ops; |
9d9f78ed MT |
325 | struct clk *clk_register_gate(struct device *dev, const char *name, |
326 | const char *parent_name, unsigned long flags, | |
327 | void __iomem *reg, u8 bit_idx, | |
328 | u8 clk_gate_flags, spinlock_t *lock); | |
e270d8cb SB |
329 | struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name, |
330 | const char *parent_name, unsigned long flags, | |
331 | void __iomem *reg, u8 bit_idx, | |
332 | u8 clk_gate_flags, spinlock_t *lock); | |
4e3c021f | 333 | void clk_unregister_gate(struct clk *clk); |
e270d8cb | 334 | void clk_hw_unregister_gate(struct clk_hw *hw); |
9d9f78ed | 335 | |
357c3f0a RN |
336 | struct clk_div_table { |
337 | unsigned int val; | |
338 | unsigned int div; | |
339 | }; | |
340 | ||
9d9f78ed MT |
341 | /** |
342 | * struct clk_divider - adjustable divider clock | |
343 | * | |
344 | * @hw: handle between common and hardware-specific interfaces | |
345 | * @reg: register containing the divider | |
346 | * @shift: shift to the divider bit field | |
347 | * @width: width of the divider bit field | |
357c3f0a | 348 | * @table: array of value/divider pairs, last entry should have div = 0 |
9d9f78ed MT |
349 | * @lock: register lock |
350 | * | |
351 | * Clock with an adjustable divider affecting its output frequency. Implements | |
352 | * .recalc_rate, .set_rate and .round_rate | |
353 | * | |
354 | * Flags: | |
355 | * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the | |
725b418b GU |
356 | * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is |
357 | * the raw value read from the register, with the value of zero considered | |
056b2053 | 358 | * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. |
9d9f78ed | 359 | * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from |
725b418b | 360 | * the hardware register |
056b2053 SB |
361 | * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have |
362 | * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. | |
363 | * Some hardware implementations gracefully handle this case and allow a | |
364 | * zero divisor by not modifying their input clock | |
365 | * (divide by one / bypass). | |
d57dfe75 | 366 | * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit |
725b418b GU |
367 | * of this register, and mask of divider bits are in higher 16-bit of this |
368 | * register. While setting the divider bits, higher 16-bit should also be | |
369 | * updated to indicate changing divider bits. | |
774b5143 MC |
370 | * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded |
371 | * to the closest integer instead of the up one. | |
79c6ab50 HS |
372 | * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should |
373 | * not be changed by the clock framework. | |
afe76c8f JQ |
374 | * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED |
375 | * except when the value read from the register is zero, the divisor is | |
376 | * 2^width of the field. | |
9d9f78ed MT |
377 | */ |
378 | struct clk_divider { | |
379 | struct clk_hw hw; | |
380 | void __iomem *reg; | |
381 | u8 shift; | |
382 | u8 width; | |
383 | u8 flags; | |
357c3f0a | 384 | const struct clk_div_table *table; |
9d9f78ed | 385 | spinlock_t *lock; |
9d9f78ed MT |
386 | }; |
387 | ||
5fd9c05c GT |
388 | #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) |
389 | ||
9d9f78ed MT |
390 | #define CLK_DIVIDER_ONE_BASED BIT(0) |
391 | #define CLK_DIVIDER_POWER_OF_TWO BIT(1) | |
056b2053 | 392 | #define CLK_DIVIDER_ALLOW_ZERO BIT(2) |
d57dfe75 | 393 | #define CLK_DIVIDER_HIWORD_MASK BIT(3) |
774b5143 | 394 | #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) |
79c6ab50 | 395 | #define CLK_DIVIDER_READ_ONLY BIT(5) |
afe76c8f | 396 | #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) |
9d9f78ed | 397 | |
bffad66e | 398 | extern const struct clk_ops clk_divider_ops; |
50359819 | 399 | extern const struct clk_ops clk_divider_ro_ops; |
bca9690b SB |
400 | |
401 | unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, | |
402 | unsigned int val, const struct clk_div_table *table, | |
403 | unsigned long flags); | |
404 | long divider_round_rate(struct clk_hw *hw, unsigned long rate, | |
405 | unsigned long *prate, const struct clk_div_table *table, | |
406 | u8 width, unsigned long flags); | |
407 | int divider_get_val(unsigned long rate, unsigned long parent_rate, | |
408 | const struct clk_div_table *table, u8 width, | |
409 | unsigned long flags); | |
410 | ||
9d9f78ed MT |
411 | struct clk *clk_register_divider(struct device *dev, const char *name, |
412 | const char *parent_name, unsigned long flags, | |
413 | void __iomem *reg, u8 shift, u8 width, | |
414 | u8 clk_divider_flags, spinlock_t *lock); | |
eb7d264f SB |
415 | struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name, |
416 | const char *parent_name, unsigned long flags, | |
417 | void __iomem *reg, u8 shift, u8 width, | |
418 | u8 clk_divider_flags, spinlock_t *lock); | |
357c3f0a RN |
419 | struct clk *clk_register_divider_table(struct device *dev, const char *name, |
420 | const char *parent_name, unsigned long flags, | |
421 | void __iomem *reg, u8 shift, u8 width, | |
422 | u8 clk_divider_flags, const struct clk_div_table *table, | |
423 | spinlock_t *lock); | |
eb7d264f SB |
424 | struct clk_hw *clk_hw_register_divider_table(struct device *dev, |
425 | const char *name, const char *parent_name, unsigned long flags, | |
426 | void __iomem *reg, u8 shift, u8 width, | |
427 | u8 clk_divider_flags, const struct clk_div_table *table, | |
428 | spinlock_t *lock); | |
4e3c021f | 429 | void clk_unregister_divider(struct clk *clk); |
eb7d264f | 430 | void clk_hw_unregister_divider(struct clk_hw *hw); |
9d9f78ed MT |
431 | |
432 | /** | |
433 | * struct clk_mux - multiplexer clock | |
434 | * | |
435 | * @hw: handle between common and hardware-specific interfaces | |
436 | * @reg: register controlling multiplexer | |
437 | * @shift: shift to multiplexer bit field | |
438 | * @width: width of mutliplexer bit field | |
3566d40c | 439 | * @flags: hardware-specific flags |
9d9f78ed MT |
440 | * @lock: register lock |
441 | * | |
442 | * Clock with multiple selectable parents. Implements .get_parent, .set_parent | |
443 | * and .recalc_rate | |
444 | * | |
445 | * Flags: | |
446 | * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 | |
1f73f31a | 447 | * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) |
ba492e90 | 448 | * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this |
725b418b GU |
449 | * register, and mask of mux bits are in higher 16-bit of this register. |
450 | * While setting the mux bits, higher 16-bit should also be updated to | |
451 | * indicate changing mux bits. | |
15a02c1f SB |
452 | * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired |
453 | * frequency. | |
9d9f78ed MT |
454 | */ |
455 | struct clk_mux { | |
456 | struct clk_hw hw; | |
457 | void __iomem *reg; | |
ce4f3313 PDS |
458 | u32 *table; |
459 | u32 mask; | |
9d9f78ed | 460 | u8 shift; |
9d9f78ed MT |
461 | u8 flags; |
462 | spinlock_t *lock; | |
463 | }; | |
464 | ||
5fd9c05c GT |
465 | #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) |
466 | ||
9d9f78ed MT |
467 | #define CLK_MUX_INDEX_ONE BIT(0) |
468 | #define CLK_MUX_INDEX_BIT BIT(1) | |
ba492e90 | 469 | #define CLK_MUX_HIWORD_MASK BIT(2) |
15a02c1f SB |
470 | #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ |
471 | #define CLK_MUX_ROUND_CLOSEST BIT(4) | |
9d9f78ed | 472 | |
bffad66e | 473 | extern const struct clk_ops clk_mux_ops; |
c57acd14 | 474 | extern const struct clk_ops clk_mux_ro_ops; |
ce4f3313 | 475 | |
9d9f78ed | 476 | struct clk *clk_register_mux(struct device *dev, const char *name, |
2893c379 SH |
477 | const char * const *parent_names, u8 num_parents, |
478 | unsigned long flags, | |
9d9f78ed MT |
479 | void __iomem *reg, u8 shift, u8 width, |
480 | u8 clk_mux_flags, spinlock_t *lock); | |
264b3171 SB |
481 | struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name, |
482 | const char * const *parent_names, u8 num_parents, | |
483 | unsigned long flags, | |
484 | void __iomem *reg, u8 shift, u8 width, | |
485 | u8 clk_mux_flags, spinlock_t *lock); | |
b2476490 | 486 | |
ce4f3313 | 487 | struct clk *clk_register_mux_table(struct device *dev, const char *name, |
2893c379 SH |
488 | const char * const *parent_names, u8 num_parents, |
489 | unsigned long flags, | |
ce4f3313 PDS |
490 | void __iomem *reg, u8 shift, u32 mask, |
491 | u8 clk_mux_flags, u32 *table, spinlock_t *lock); | |
264b3171 SB |
492 | struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name, |
493 | const char * const *parent_names, u8 num_parents, | |
494 | unsigned long flags, | |
495 | void __iomem *reg, u8 shift, u32 mask, | |
496 | u8 clk_mux_flags, u32 *table, spinlock_t *lock); | |
ce4f3313 | 497 | |
4e3c021f | 498 | void clk_unregister_mux(struct clk *clk); |
264b3171 | 499 | void clk_hw_unregister_mux(struct clk_hw *hw); |
4e3c021f | 500 | |
79b16641 GC |
501 | void of_fixed_factor_clk_setup(struct device_node *node); |
502 | ||
f0948f59 SH |
503 | /** |
504 | * struct clk_fixed_factor - fixed multiplier and divider clock | |
505 | * | |
506 | * @hw: handle between common and hardware-specific interfaces | |
507 | * @mult: multiplier | |
508 | * @div: divider | |
509 | * | |
510 | * Clock with a fixed multiplier and divider. The output frequency is the | |
511 | * parent clock rate divided by div and multiplied by mult. | |
512 | * Implements .recalc_rate, .set_rate and .round_rate | |
513 | */ | |
514 | ||
515 | struct clk_fixed_factor { | |
516 | struct clk_hw hw; | |
517 | unsigned int mult; | |
518 | unsigned int div; | |
519 | }; | |
520 | ||
5fd9c05c GT |
521 | #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) |
522 | ||
3037e9ea | 523 | extern const struct clk_ops clk_fixed_factor_ops; |
f0948f59 SH |
524 | struct clk *clk_register_fixed_factor(struct device *dev, const char *name, |
525 | const char *parent_name, unsigned long flags, | |
526 | unsigned int mult, unsigned int div); | |
cbf9591f | 527 | void clk_unregister_fixed_factor(struct clk *clk); |
0759ac8a SB |
528 | struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, |
529 | const char *name, const char *parent_name, unsigned long flags, | |
530 | unsigned int mult, unsigned int div); | |
531 | void clk_hw_unregister_fixed_factor(struct clk_hw *hw); | |
f0948f59 | 532 | |
e2d0e90f HK |
533 | /** |
534 | * struct clk_fractional_divider - adjustable fractional divider clock | |
535 | * | |
536 | * @hw: handle between common and hardware-specific interfaces | |
537 | * @reg: register containing the divider | |
538 | * @mshift: shift to the numerator bit field | |
539 | * @mwidth: width of the numerator bit field | |
540 | * @nshift: shift to the denominator bit field | |
541 | * @nwidth: width of the denominator bit field | |
542 | * @lock: register lock | |
543 | * | |
544 | * Clock with adjustable fractional divider affecting its output frequency. | |
545 | */ | |
e2d0e90f HK |
546 | struct clk_fractional_divider { |
547 | struct clk_hw hw; | |
548 | void __iomem *reg; | |
549 | u8 mshift; | |
934e2536 | 550 | u8 mwidth; |
e2d0e90f HK |
551 | u32 mmask; |
552 | u8 nshift; | |
934e2536 | 553 | u8 nwidth; |
e2d0e90f HK |
554 | u32 nmask; |
555 | u8 flags; | |
556 | spinlock_t *lock; | |
557 | }; | |
558 | ||
5fd9c05c GT |
559 | #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) |
560 | ||
e2d0e90f HK |
561 | extern const struct clk_ops clk_fractional_divider_ops; |
562 | struct clk *clk_register_fractional_divider(struct device *dev, | |
563 | const char *name, const char *parent_name, unsigned long flags, | |
564 | void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, | |
565 | u8 clk_divider_flags, spinlock_t *lock); | |
566 | ||
f2e0a532 MR |
567 | /** |
568 | * struct clk_multiplier - adjustable multiplier clock | |
569 | * | |
570 | * @hw: handle between common and hardware-specific interfaces | |
571 | * @reg: register containing the multiplier | |
572 | * @shift: shift to the multiplier bit field | |
573 | * @width: width of the multiplier bit field | |
574 | * @lock: register lock | |
575 | * | |
576 | * Clock with an adjustable multiplier affecting its output frequency. | |
577 | * Implements .recalc_rate, .set_rate and .round_rate | |
578 | * | |
579 | * Flags: | |
580 | * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read | |
581 | * from the register, with 0 being a valid value effectively | |
582 | * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is | |
583 | * set, then a null multiplier will be considered as a bypass, | |
584 | * leaving the parent rate unmodified. | |
585 | * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be | |
586 | * rounded to the closest integer instead of the down one. | |
587 | */ | |
588 | struct clk_multiplier { | |
589 | struct clk_hw hw; | |
590 | void __iomem *reg; | |
591 | u8 shift; | |
592 | u8 width; | |
593 | u8 flags; | |
594 | spinlock_t *lock; | |
595 | }; | |
596 | ||
5fd9c05c GT |
597 | #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) |
598 | ||
f2e0a532 MR |
599 | #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) |
600 | #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) | |
601 | ||
602 | extern const struct clk_ops clk_multiplier_ops; | |
603 | ||
ece70094 PG |
604 | /*** |
605 | * struct clk_composite - aggregate clock of mux, divider and gate clocks | |
606 | * | |
607 | * @hw: handle between common and hardware-specific interfaces | |
d3a1c7be MT |
608 | * @mux_hw: handle between composite and hardware-specific mux clock |
609 | * @rate_hw: handle between composite and hardware-specific rate clock | |
610 | * @gate_hw: handle between composite and hardware-specific gate clock | |
ece70094 | 611 | * @mux_ops: clock ops for mux |
d3a1c7be | 612 | * @rate_ops: clock ops for rate |
ece70094 PG |
613 | * @gate_ops: clock ops for gate |
614 | */ | |
615 | struct clk_composite { | |
616 | struct clk_hw hw; | |
617 | struct clk_ops ops; | |
618 | ||
619 | struct clk_hw *mux_hw; | |
d3a1c7be | 620 | struct clk_hw *rate_hw; |
ece70094 PG |
621 | struct clk_hw *gate_hw; |
622 | ||
623 | const struct clk_ops *mux_ops; | |
d3a1c7be | 624 | const struct clk_ops *rate_ops; |
ece70094 PG |
625 | const struct clk_ops *gate_ops; |
626 | }; | |
627 | ||
5fd9c05c GT |
628 | #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) |
629 | ||
ece70094 | 630 | struct clk *clk_register_composite(struct device *dev, const char *name, |
2893c379 | 631 | const char * const *parent_names, int num_parents, |
ece70094 | 632 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
d3a1c7be | 633 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
ece70094 PG |
634 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
635 | unsigned long flags); | |
636 | ||
c873d14d JS |
637 | /*** |
638 | * struct clk_gpio_gate - gpio gated clock | |
639 | * | |
640 | * @hw: handle between common and hardware-specific interfaces | |
641 | * @gpiod: gpio descriptor | |
642 | * | |
643 | * Clock with a gpio control for enabling and disabling the parent clock. | |
644 | * Implements .enable, .disable and .is_enabled | |
645 | */ | |
646 | ||
647 | struct clk_gpio { | |
648 | struct clk_hw hw; | |
649 | struct gpio_desc *gpiod; | |
650 | }; | |
651 | ||
5fd9c05c GT |
652 | #define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw) |
653 | ||
c873d14d JS |
654 | extern const struct clk_ops clk_gpio_gate_ops; |
655 | struct clk *clk_register_gpio_gate(struct device *dev, const char *name, | |
820ad975 | 656 | const char *parent_name, unsigned gpio, bool active_low, |
c873d14d JS |
657 | unsigned long flags); |
658 | ||
80eeb1f0 SS |
659 | /** |
660 | * struct clk_gpio_mux - gpio controlled clock multiplexer | |
661 | * | |
662 | * @hw: see struct clk_gpio | |
663 | * @gpiod: gpio descriptor to select the parent of this clock multiplexer | |
664 | * | |
665 | * Clock with a gpio control for selecting the parent clock. | |
666 | * Implements .get_parent, .set_parent and .determine_rate | |
667 | */ | |
668 | ||
669 | extern const struct clk_ops clk_gpio_mux_ops; | |
670 | struct clk *clk_register_gpio_mux(struct device *dev, const char *name, | |
37bff2c1 | 671 | const char * const *parent_names, u8 num_parents, unsigned gpio, |
80eeb1f0 SS |
672 | bool active_low, unsigned long flags); |
673 | ||
b2476490 MT |
674 | /** |
675 | * clk_register - allocate a new clock, register it and return an opaque cookie | |
676 | * @dev: device that is registering this clock | |
b2476490 | 677 | * @hw: link to hardware-specific clock data |
b2476490 MT |
678 | * |
679 | * clk_register is the primary interface for populating the clock tree with new | |
680 | * clock nodes. It returns a pointer to the newly allocated struct clk which | |
681 | * cannot be dereferenced by driver code but may be used in conjuction with the | |
d1302a36 MT |
682 | * rest of the clock API. In the event of an error clk_register will return an |
683 | * error code; drivers must test for an error code after calling clk_register. | |
b2476490 | 684 | */ |
0197b3ea | 685 | struct clk *clk_register(struct device *dev, struct clk_hw *hw); |
46c8773a | 686 | struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); |
b2476490 | 687 | |
4143804c SB |
688 | int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw); |
689 | int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw); | |
690 | ||
1df5c939 | 691 | void clk_unregister(struct clk *clk); |
46c8773a | 692 | void devm_clk_unregister(struct device *dev, struct clk *clk); |
1df5c939 | 693 | |
4143804c SB |
694 | void clk_hw_unregister(struct clk_hw *hw); |
695 | void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw); | |
696 | ||
b2476490 | 697 | /* helper functions */ |
b76281cb | 698 | const char *__clk_get_name(const struct clk *clk); |
e7df6f6e | 699 | const char *clk_hw_get_name(const struct clk_hw *hw); |
b2476490 | 700 | struct clk_hw *__clk_get_hw(struct clk *clk); |
e7df6f6e SB |
701 | unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); |
702 | struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); | |
703 | struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, | |
1a9c069c | 704 | unsigned int index); |
93874681 | 705 | unsigned int __clk_get_enable_count(struct clk *clk); |
e7df6f6e | 706 | unsigned long clk_hw_get_rate(const struct clk_hw *hw); |
b2476490 | 707 | unsigned long __clk_get_flags(struct clk *clk); |
e7df6f6e SB |
708 | unsigned long clk_hw_get_flags(const struct clk_hw *hw); |
709 | bool clk_hw_is_prepared(const struct clk_hw *hw); | |
be68bf88 | 710 | bool clk_hw_is_enabled(const struct clk_hw *hw); |
2ac6b1f5 | 711 | bool __clk_is_enabled(struct clk *clk); |
b2476490 | 712 | struct clk *__clk_lookup(const char *name); |
0817b62c BB |
713 | int __clk_mux_determine_rate(struct clk_hw *hw, |
714 | struct clk_rate_request *req); | |
715 | int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req); | |
716 | int __clk_mux_determine_rate_closest(struct clk_hw *hw, | |
717 | struct clk_rate_request *req); | |
42c86547 | 718 | void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent); |
9783c0d9 SB |
719 | void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, |
720 | unsigned long max_rate); | |
b2476490 | 721 | |
2e65d8bf JMC |
722 | static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) |
723 | { | |
724 | dst->clk = src->clk; | |
725 | dst->core = src->core; | |
726 | } | |
727 | ||
b2476490 MT |
728 | /* |
729 | * FIXME clock api without lock protection | |
730 | */ | |
1a9c069c | 731 | unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); |
b2476490 | 732 | |
766e6a4e GL |
733 | struct of_device_id; |
734 | ||
735 | typedef void (*of_clk_init_cb_t)(struct device_node *); | |
736 | ||
0b151deb SH |
737 | struct clk_onecell_data { |
738 | struct clk **clks; | |
739 | unsigned int clk_num; | |
740 | }; | |
741 | ||
0861e5b8 SB |
742 | struct clk_hw_onecell_data { |
743 | size_t num; | |
744 | struct clk_hw *hws[]; | |
745 | }; | |
746 | ||
819b4861 TK |
747 | extern struct of_device_id __clk_of_table; |
748 | ||
54196ccb | 749 | #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) |
0b151deb SH |
750 | |
751 | #ifdef CONFIG_OF | |
766e6a4e GL |
752 | int of_clk_add_provider(struct device_node *np, |
753 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | |
754 | void *data), | |
755 | void *data); | |
0861e5b8 SB |
756 | int of_clk_add_hw_provider(struct device_node *np, |
757 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
758 | void *data), | |
759 | void *data); | |
766e6a4e GL |
760 | void of_clk_del_provider(struct device_node *np); |
761 | struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, | |
762 | void *data); | |
0861e5b8 SB |
763 | struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, |
764 | void *data); | |
494bfec9 | 765 | struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); |
0861e5b8 SB |
766 | struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, |
767 | void *data); | |
929e7f3b | 768 | unsigned int of_clk_get_parent_count(struct device_node *np); |
2e61dfb3 DN |
769 | int of_clk_parent_fill(struct device_node *np, const char **parents, |
770 | unsigned int size); | |
766e6a4e | 771 | const char *of_clk_get_parent_name(struct device_node *np, int index); |
f2f6c255 | 772 | |
766e6a4e GL |
773 | void of_clk_init(const struct of_device_id *matches); |
774 | ||
0b151deb | 775 | #else /* !CONFIG_OF */ |
f2f6c255 | 776 | |
0b151deb SH |
777 | static inline int of_clk_add_provider(struct device_node *np, |
778 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | |
779 | void *data), | |
780 | void *data) | |
781 | { | |
782 | return 0; | |
783 | } | |
0861e5b8 SB |
784 | static inline int of_clk_add_hw_provider(struct device_node *np, |
785 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
786 | void *data), | |
787 | void *data) | |
788 | { | |
789 | return 0; | |
790 | } | |
20dd882a | 791 | static inline void of_clk_del_provider(struct device_node *np) {} |
0b151deb SH |
792 | static inline struct clk *of_clk_src_simple_get( |
793 | struct of_phandle_args *clkspec, void *data) | |
794 | { | |
795 | return ERR_PTR(-ENOENT); | |
796 | } | |
0861e5b8 SB |
797 | static inline struct clk_hw * |
798 | of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) | |
799 | { | |
800 | return ERR_PTR(-ENOENT); | |
801 | } | |
0b151deb SH |
802 | static inline struct clk *of_clk_src_onecell_get( |
803 | struct of_phandle_args *clkspec, void *data) | |
804 | { | |
805 | return ERR_PTR(-ENOENT); | |
806 | } | |
0861e5b8 SB |
807 | static inline struct clk_hw * |
808 | of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) | |
809 | { | |
810 | return ERR_PTR(-ENOENT); | |
811 | } | |
679c51cf SB |
812 | static inline int of_clk_get_parent_count(struct device_node *np) |
813 | { | |
814 | return 0; | |
815 | } | |
816 | static inline int of_clk_parent_fill(struct device_node *np, | |
817 | const char **parents, unsigned int size) | |
818 | { | |
819 | return 0; | |
820 | } | |
0b151deb SH |
821 | static inline const char *of_clk_get_parent_name(struct device_node *np, |
822 | int index) | |
823 | { | |
824 | return NULL; | |
825 | } | |
20dd882a | 826 | static inline void of_clk_init(const struct of_device_id *matches) {} |
0b151deb | 827 | #endif /* CONFIG_OF */ |
aa514ce3 GS |
828 | |
829 | /* | |
830 | * wrap access to peripherals in accessor routines | |
831 | * for improved portability across platforms | |
832 | */ | |
833 | ||
6d8cdb68 GS |
834 | #if IS_ENABLED(CONFIG_PPC) |
835 | ||
836 | static inline u32 clk_readl(u32 __iomem *reg) | |
837 | { | |
838 | return ioread32be(reg); | |
839 | } | |
840 | ||
841 | static inline void clk_writel(u32 val, u32 __iomem *reg) | |
842 | { | |
843 | iowrite32be(val, reg); | |
844 | } | |
845 | ||
846 | #else /* platform dependent I/O accessors */ | |
847 | ||
aa514ce3 GS |
848 | static inline u32 clk_readl(u32 __iomem *reg) |
849 | { | |
850 | return readl(reg); | |
851 | } | |
852 | ||
853 | static inline void clk_writel(u32 val, u32 __iomem *reg) | |
854 | { | |
855 | writel(val, reg); | |
856 | } | |
857 | ||
6d8cdb68 GS |
858 | #endif /* platform dependent I/O accessors */ |
859 | ||
fb2b3c9f | 860 | #ifdef CONFIG_DEBUG_FS |
61c7cddf | 861 | struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode, |
fb2b3c9f PDS |
862 | void *data, const struct file_operations *fops); |
863 | #endif | |
864 | ||
b2476490 MT |
865 | #endif /* CONFIG_COMMON_CLK */ |
866 | #endif /* CLK_PROVIDER_H */ |