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b2476490 MT |
1 | /* |
2 | * linux/include/linux/clk-provider.h | |
3 | * | |
4 | * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> | |
5 | * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #ifndef __LINUX_CLK_PROVIDER_H | |
12 | #define __LINUX_CLK_PROVIDER_H | |
13 | ||
14 | #include <linux/clk.h> | |
aa514ce3 | 15 | #include <linux/io.h> |
355bb165 | 16 | #include <linux/of.h> |
b2476490 MT |
17 | |
18 | #ifdef CONFIG_COMMON_CLK | |
19 | ||
b2476490 MT |
20 | /* |
21 | * flags used across common struct clk. these flags should only affect the | |
22 | * top-level framework. custom flags for dealing with hardware specifics | |
23 | * belong in struct clk_foo | |
24 | */ | |
25 | #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ | |
26 | #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ | |
27 | #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ | |
28 | #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ | |
29 | #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ | |
f7d8caad | 30 | #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ |
a093bde2 | 31 | #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ |
819c1de3 | 32 | #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ |
5279fc40 | 33 | #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ |
b2476490 | 34 | |
0197b3ea | 35 | struct clk_hw; |
c646cbf1 | 36 | struct dentry; |
0197b3ea | 37 | |
b2476490 MT |
38 | /** |
39 | * struct clk_ops - Callback operations for hardware clocks; these are to | |
40 | * be provided by the clock implementation, and will be called by drivers | |
41 | * through the clk_* api. | |
42 | * | |
43 | * @prepare: Prepare the clock for enabling. This must not return until | |
725b418b GU |
44 | * the clock is fully prepared, and it's safe to call clk_enable. |
45 | * This callback is intended to allow clock implementations to | |
46 | * do any initialisation that may sleep. Called with | |
47 | * prepare_lock held. | |
b2476490 MT |
48 | * |
49 | * @unprepare: Release the clock from its prepared state. This will typically | |
725b418b GU |
50 | * undo any work done in the @prepare callback. Called with |
51 | * prepare_lock held. | |
b2476490 | 52 | * |
3d6ee287 UH |
53 | * @is_prepared: Queries the hardware to determine if the clock is prepared. |
54 | * This function is allowed to sleep. Optional, if this op is not | |
55 | * set then the prepare count will be used. | |
56 | * | |
3cc8247f UH |
57 | * @unprepare_unused: Unprepare the clock atomically. Only called from |
58 | * clk_disable_unused for prepare clocks with special needs. | |
59 | * Called with prepare mutex held. This function may sleep. | |
60 | * | |
b2476490 | 61 | * @enable: Enable the clock atomically. This must not return until the |
725b418b GU |
62 | * clock is generating a valid clock signal, usable by consumer |
63 | * devices. Called with enable_lock held. This function must not | |
64 | * sleep. | |
b2476490 MT |
65 | * |
66 | * @disable: Disable the clock atomically. Called with enable_lock held. | |
725b418b | 67 | * This function must not sleep. |
b2476490 | 68 | * |
119c7127 | 69 | * @is_enabled: Queries the hardware to determine if the clock is enabled. |
725b418b GU |
70 | * This function must not sleep. Optional, if this op is not |
71 | * set then the enable count will be used. | |
119c7127 | 72 | * |
7c045a55 MT |
73 | * @disable_unused: Disable the clock atomically. Only called from |
74 | * clk_disable_unused for gate clocks with special needs. | |
75 | * Called with enable_lock held. This function must not | |
76 | * sleep. | |
77 | * | |
7ce3e8cc | 78 | * @recalc_rate Recalculate the rate of this clock, by querying hardware. The |
725b418b GU |
79 | * parent rate is an input parameter. It is up to the caller to |
80 | * ensure that the prepare_mutex is held across this call. | |
81 | * Returns the calculated rate. Optional, but recommended - if | |
82 | * this op is not set then clock rate will be initialized to 0. | |
b2476490 MT |
83 | * |
84 | * @round_rate: Given a target rate as input, returns the closest rate actually | |
54e73016 GU |
85 | * supported by the clock. The parent rate is an input/output |
86 | * parameter. | |
b2476490 | 87 | * |
71472c0c JH |
88 | * @determine_rate: Given a target rate as input, returns the closest rate |
89 | * actually supported by the clock, and optionally the parent clock | |
90 | * that should be used to provide the clock rate. | |
91 | * | |
b2476490 | 92 | * @set_parent: Change the input source of this clock; for clocks with multiple |
54e73016 GU |
93 | * possible parents specify a new parent by passing in the index |
94 | * as a u8 corresponding to the parent in either the .parent_names | |
95 | * or .parents arrays. This function in affect translates an | |
96 | * array index into the value programmed into the hardware. | |
97 | * Returns 0 on success, -EERROR otherwise. | |
98 | * | |
b2476490 | 99 | * @get_parent: Queries the hardware to determine the parent of a clock. The |
725b418b GU |
100 | * return value is a u8 which specifies the index corresponding to |
101 | * the parent clock. This index can be applied to either the | |
102 | * .parent_names or .parents arrays. In short, this function | |
103 | * translates the parent value read from hardware into an array | |
104 | * index. Currently only called when the clock is initialized by | |
105 | * __clk_init. This callback is mandatory for clocks with | |
106 | * multiple parents. It is optional (and unnecessary) for clocks | |
107 | * with 0 or 1 parents. | |
b2476490 | 108 | * |
1c0035d7 SG |
109 | * @set_rate: Change the rate of this clock. The requested rate is specified |
110 | * by the second argument, which should typically be the return | |
111 | * of .round_rate call. The third argument gives the parent rate | |
112 | * which is likely helpful for most .set_rate implementation. | |
113 | * Returns 0 on success, -EERROR otherwise. | |
b2476490 | 114 | * |
3fa2252b SB |
115 | * @set_rate_and_parent: Change the rate and the parent of this clock. The |
116 | * requested rate is specified by the second argument, which | |
117 | * should typically be the return of .round_rate call. The | |
118 | * third argument gives the parent rate which is likely helpful | |
119 | * for most .set_rate_and_parent implementation. The fourth | |
120 | * argument gives the parent index. This callback is optional (and | |
121 | * unnecessary) for clocks with 0 or 1 parents as well as | |
122 | * for clocks that can tolerate switching the rate and the parent | |
123 | * separately via calls to .set_parent and .set_rate. | |
124 | * Returns 0 on success, -EERROR otherwise. | |
125 | * | |
54e73016 GU |
126 | * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy |
127 | * is expressed in ppb (parts per billion). The parent accuracy is | |
128 | * an input parameter. | |
129 | * Returns the calculated accuracy. Optional - if this op is not | |
130 | * set then clock accuracy will be initialized to parent accuracy | |
131 | * or 0 (perfect clock) if clock has no parent. | |
132 | * | |
e59c5371 MT |
133 | * @set_phase: Shift the phase this clock signal in degrees specified |
134 | * by the second argument. Valid values for degrees are | |
135 | * 0-359. Return 0 on success, otherwise -EERROR. | |
136 | * | |
54e73016 GU |
137 | * @init: Perform platform-specific initialization magic. |
138 | * This is not not used by any of the basic clock types. | |
139 | * Please consider other ways of solving initialization problems | |
140 | * before using this callback, as its use is discouraged. | |
141 | * | |
c646cbf1 AE |
142 | * @debug_init: Set up type-specific debugfs entries for this clock. This |
143 | * is called once, after the debugfs directory entry for this | |
144 | * clock has been created. The dentry pointer representing that | |
145 | * directory is provided as an argument. Called with | |
146 | * prepare_lock held. Returns 0 on success, -EERROR otherwise. | |
147 | * | |
3fa2252b | 148 | * |
b2476490 MT |
149 | * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow |
150 | * implementations to split any work between atomic (enable) and sleepable | |
151 | * (prepare) contexts. If enabling a clock requires code that might sleep, | |
152 | * this must be done in clk_prepare. Clock enable code that will never be | |
7ce3e8cc | 153 | * called in a sleepable context may be implemented in clk_enable. |
b2476490 MT |
154 | * |
155 | * Typically, drivers will call clk_prepare when a clock may be needed later | |
156 | * (eg. when a device is opened), and clk_enable when the clock is actually | |
157 | * required (eg. from an interrupt). Note that clk_prepare MUST have been | |
158 | * called before clk_enable. | |
159 | */ | |
160 | struct clk_ops { | |
161 | int (*prepare)(struct clk_hw *hw); | |
162 | void (*unprepare)(struct clk_hw *hw); | |
3d6ee287 | 163 | int (*is_prepared)(struct clk_hw *hw); |
3cc8247f | 164 | void (*unprepare_unused)(struct clk_hw *hw); |
b2476490 MT |
165 | int (*enable)(struct clk_hw *hw); |
166 | void (*disable)(struct clk_hw *hw); | |
167 | int (*is_enabled)(struct clk_hw *hw); | |
7c045a55 | 168 | void (*disable_unused)(struct clk_hw *hw); |
b2476490 MT |
169 | unsigned long (*recalc_rate)(struct clk_hw *hw, |
170 | unsigned long parent_rate); | |
54e73016 GU |
171 | long (*round_rate)(struct clk_hw *hw, unsigned long rate, |
172 | unsigned long *parent_rate); | |
71472c0c JH |
173 | long (*determine_rate)(struct clk_hw *hw, unsigned long rate, |
174 | unsigned long *best_parent_rate, | |
175 | struct clk **best_parent_clk); | |
b2476490 MT |
176 | int (*set_parent)(struct clk_hw *hw, u8 index); |
177 | u8 (*get_parent)(struct clk_hw *hw); | |
54e73016 GU |
178 | int (*set_rate)(struct clk_hw *hw, unsigned long rate, |
179 | unsigned long parent_rate); | |
3fa2252b SB |
180 | int (*set_rate_and_parent)(struct clk_hw *hw, |
181 | unsigned long rate, | |
182 | unsigned long parent_rate, u8 index); | |
5279fc40 BB |
183 | unsigned long (*recalc_accuracy)(struct clk_hw *hw, |
184 | unsigned long parent_accuracy); | |
e59c5371 | 185 | int (*set_phase)(struct clk_hw *hw, int degrees); |
b2476490 | 186 | void (*init)(struct clk_hw *hw); |
c646cbf1 | 187 | int (*debug_init)(struct clk_hw *hw, struct dentry *dentry); |
b2476490 MT |
188 | }; |
189 | ||
0197b3ea SK |
190 | /** |
191 | * struct clk_init_data - holds init data that's common to all clocks and is | |
192 | * shared between the clock provider and the common clock framework. | |
193 | * | |
194 | * @name: clock name | |
195 | * @ops: operations this clock supports | |
196 | * @parent_names: array of string names for all possible parents | |
197 | * @num_parents: number of possible parents | |
198 | * @flags: framework-level hints and quirks | |
199 | */ | |
200 | struct clk_init_data { | |
201 | const char *name; | |
202 | const struct clk_ops *ops; | |
203 | const char **parent_names; | |
204 | u8 num_parents; | |
205 | unsigned long flags; | |
206 | }; | |
207 | ||
208 | /** | |
209 | * struct clk_hw - handle for traversing from a struct clk to its corresponding | |
210 | * hardware-specific structure. struct clk_hw should be declared within struct | |
211 | * clk_foo and then referenced by the struct clk instance that uses struct | |
212 | * clk_foo's clk_ops | |
213 | * | |
214 | * @clk: pointer to the struct clk instance that points back to this struct | |
215 | * clk_hw instance | |
216 | * | |
217 | * @init: pointer to struct clk_init_data that contains the init data shared | |
218 | * with the common clock framework. | |
219 | */ | |
220 | struct clk_hw { | |
221 | struct clk *clk; | |
dc4cd941 | 222 | const struct clk_init_data *init; |
0197b3ea SK |
223 | }; |
224 | ||
9d9f78ed MT |
225 | /* |
226 | * DOC: Basic clock implementations common to many platforms | |
227 | * | |
228 | * Each basic clock hardware type is comprised of a structure describing the | |
229 | * clock hardware, implementations of the relevant callbacks in struct clk_ops, | |
230 | * unique flags for that hardware type, a registration function and an | |
231 | * alternative macro for static initialization | |
232 | */ | |
233 | ||
234 | /** | |
235 | * struct clk_fixed_rate - fixed-rate clock | |
236 | * @hw: handle between common and hardware-specific interfaces | |
237 | * @fixed_rate: constant frequency of clock | |
238 | */ | |
239 | struct clk_fixed_rate { | |
240 | struct clk_hw hw; | |
241 | unsigned long fixed_rate; | |
0903ea60 | 242 | unsigned long fixed_accuracy; |
9d9f78ed MT |
243 | u8 flags; |
244 | }; | |
245 | ||
bffad66e | 246 | extern const struct clk_ops clk_fixed_rate_ops; |
9d9f78ed MT |
247 | struct clk *clk_register_fixed_rate(struct device *dev, const char *name, |
248 | const char *parent_name, unsigned long flags, | |
249 | unsigned long fixed_rate); | |
0903ea60 BB |
250 | struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, |
251 | const char *name, const char *parent_name, unsigned long flags, | |
252 | unsigned long fixed_rate, unsigned long fixed_accuracy); | |
9d9f78ed | 253 | |
015ba402 GL |
254 | void of_fixed_clk_setup(struct device_node *np); |
255 | ||
9d9f78ed MT |
256 | /** |
257 | * struct clk_gate - gating clock | |
258 | * | |
259 | * @hw: handle between common and hardware-specific interfaces | |
260 | * @reg: register controlling gate | |
261 | * @bit_idx: single bit controlling gate | |
262 | * @flags: hardware-specific flags | |
263 | * @lock: register lock | |
264 | * | |
265 | * Clock which can gate its output. Implements .enable & .disable | |
266 | * | |
267 | * Flags: | |
1f73f31a | 268 | * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to |
725b418b GU |
269 | * enable the clock. Setting this flag does the opposite: setting the bit |
270 | * disable the clock and clearing it enables the clock | |
04577994 | 271 | * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit |
725b418b GU |
272 | * of this register, and mask of gate bits are in higher 16-bit of this |
273 | * register. While setting the gate bits, higher 16-bit should also be | |
274 | * updated to indicate changing gate bits. | |
9d9f78ed MT |
275 | */ |
276 | struct clk_gate { | |
277 | struct clk_hw hw; | |
278 | void __iomem *reg; | |
279 | u8 bit_idx; | |
280 | u8 flags; | |
281 | spinlock_t *lock; | |
9d9f78ed MT |
282 | }; |
283 | ||
284 | #define CLK_GATE_SET_TO_DISABLE BIT(0) | |
04577994 | 285 | #define CLK_GATE_HIWORD_MASK BIT(1) |
9d9f78ed | 286 | |
bffad66e | 287 | extern const struct clk_ops clk_gate_ops; |
9d9f78ed MT |
288 | struct clk *clk_register_gate(struct device *dev, const char *name, |
289 | const char *parent_name, unsigned long flags, | |
290 | void __iomem *reg, u8 bit_idx, | |
291 | u8 clk_gate_flags, spinlock_t *lock); | |
292 | ||
357c3f0a RN |
293 | struct clk_div_table { |
294 | unsigned int val; | |
295 | unsigned int div; | |
296 | }; | |
297 | ||
9d9f78ed MT |
298 | /** |
299 | * struct clk_divider - adjustable divider clock | |
300 | * | |
301 | * @hw: handle between common and hardware-specific interfaces | |
302 | * @reg: register containing the divider | |
303 | * @shift: shift to the divider bit field | |
304 | * @width: width of the divider bit field | |
357c3f0a | 305 | * @table: array of value/divider pairs, last entry should have div = 0 |
9d9f78ed MT |
306 | * @lock: register lock |
307 | * | |
308 | * Clock with an adjustable divider affecting its output frequency. Implements | |
309 | * .recalc_rate, .set_rate and .round_rate | |
310 | * | |
311 | * Flags: | |
312 | * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the | |
725b418b GU |
313 | * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is |
314 | * the raw value read from the register, with the value of zero considered | |
056b2053 | 315 | * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. |
9d9f78ed | 316 | * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from |
725b418b | 317 | * the hardware register |
056b2053 SB |
318 | * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have |
319 | * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. | |
320 | * Some hardware implementations gracefully handle this case and allow a | |
321 | * zero divisor by not modifying their input clock | |
322 | * (divide by one / bypass). | |
d57dfe75 | 323 | * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit |
725b418b GU |
324 | * of this register, and mask of divider bits are in higher 16-bit of this |
325 | * register. While setting the divider bits, higher 16-bit should also be | |
326 | * updated to indicate changing divider bits. | |
774b5143 MC |
327 | * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded |
328 | * to the closest integer instead of the up one. | |
79c6ab50 HS |
329 | * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should |
330 | * not be changed by the clock framework. | |
9d9f78ed MT |
331 | */ |
332 | struct clk_divider { | |
333 | struct clk_hw hw; | |
334 | void __iomem *reg; | |
335 | u8 shift; | |
336 | u8 width; | |
337 | u8 flags; | |
357c3f0a | 338 | const struct clk_div_table *table; |
9d9f78ed | 339 | spinlock_t *lock; |
9d9f78ed MT |
340 | }; |
341 | ||
342 | #define CLK_DIVIDER_ONE_BASED BIT(0) | |
343 | #define CLK_DIVIDER_POWER_OF_TWO BIT(1) | |
056b2053 | 344 | #define CLK_DIVIDER_ALLOW_ZERO BIT(2) |
d57dfe75 | 345 | #define CLK_DIVIDER_HIWORD_MASK BIT(3) |
774b5143 | 346 | #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) |
79c6ab50 | 347 | #define CLK_DIVIDER_READ_ONLY BIT(5) |
9d9f78ed | 348 | |
bffad66e | 349 | extern const struct clk_ops clk_divider_ops; |
79c6ab50 | 350 | extern const struct clk_ops clk_divider_ro_ops; |
9d9f78ed MT |
351 | struct clk *clk_register_divider(struct device *dev, const char *name, |
352 | const char *parent_name, unsigned long flags, | |
353 | void __iomem *reg, u8 shift, u8 width, | |
354 | u8 clk_divider_flags, spinlock_t *lock); | |
357c3f0a RN |
355 | struct clk *clk_register_divider_table(struct device *dev, const char *name, |
356 | const char *parent_name, unsigned long flags, | |
357 | void __iomem *reg, u8 shift, u8 width, | |
358 | u8 clk_divider_flags, const struct clk_div_table *table, | |
359 | spinlock_t *lock); | |
9d9f78ed MT |
360 | |
361 | /** | |
362 | * struct clk_mux - multiplexer clock | |
363 | * | |
364 | * @hw: handle between common and hardware-specific interfaces | |
365 | * @reg: register controlling multiplexer | |
366 | * @shift: shift to multiplexer bit field | |
367 | * @width: width of mutliplexer bit field | |
3566d40c | 368 | * @flags: hardware-specific flags |
9d9f78ed MT |
369 | * @lock: register lock |
370 | * | |
371 | * Clock with multiple selectable parents. Implements .get_parent, .set_parent | |
372 | * and .recalc_rate | |
373 | * | |
374 | * Flags: | |
375 | * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 | |
1f73f31a | 376 | * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) |
ba492e90 | 377 | * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this |
725b418b GU |
378 | * register, and mask of mux bits are in higher 16-bit of this register. |
379 | * While setting the mux bits, higher 16-bit should also be updated to | |
380 | * indicate changing mux bits. | |
9d9f78ed MT |
381 | */ |
382 | struct clk_mux { | |
383 | struct clk_hw hw; | |
384 | void __iomem *reg; | |
ce4f3313 PDS |
385 | u32 *table; |
386 | u32 mask; | |
9d9f78ed | 387 | u8 shift; |
9d9f78ed MT |
388 | u8 flags; |
389 | spinlock_t *lock; | |
390 | }; | |
391 | ||
392 | #define CLK_MUX_INDEX_ONE BIT(0) | |
393 | #define CLK_MUX_INDEX_BIT BIT(1) | |
ba492e90 | 394 | #define CLK_MUX_HIWORD_MASK BIT(2) |
c57acd14 | 395 | #define CLK_MUX_READ_ONLY BIT(3) /* mux setting cannot be changed */ |
9d9f78ed | 396 | |
bffad66e | 397 | extern const struct clk_ops clk_mux_ops; |
c57acd14 | 398 | extern const struct clk_ops clk_mux_ro_ops; |
ce4f3313 | 399 | |
9d9f78ed | 400 | struct clk *clk_register_mux(struct device *dev, const char *name, |
d305fb78 | 401 | const char **parent_names, u8 num_parents, unsigned long flags, |
9d9f78ed MT |
402 | void __iomem *reg, u8 shift, u8 width, |
403 | u8 clk_mux_flags, spinlock_t *lock); | |
b2476490 | 404 | |
ce4f3313 PDS |
405 | struct clk *clk_register_mux_table(struct device *dev, const char *name, |
406 | const char **parent_names, u8 num_parents, unsigned long flags, | |
407 | void __iomem *reg, u8 shift, u32 mask, | |
408 | u8 clk_mux_flags, u32 *table, spinlock_t *lock); | |
409 | ||
79b16641 GC |
410 | void of_fixed_factor_clk_setup(struct device_node *node); |
411 | ||
f0948f59 SH |
412 | /** |
413 | * struct clk_fixed_factor - fixed multiplier and divider clock | |
414 | * | |
415 | * @hw: handle between common and hardware-specific interfaces | |
416 | * @mult: multiplier | |
417 | * @div: divider | |
418 | * | |
419 | * Clock with a fixed multiplier and divider. The output frequency is the | |
420 | * parent clock rate divided by div and multiplied by mult. | |
421 | * Implements .recalc_rate, .set_rate and .round_rate | |
422 | */ | |
423 | ||
424 | struct clk_fixed_factor { | |
425 | struct clk_hw hw; | |
426 | unsigned int mult; | |
427 | unsigned int div; | |
428 | }; | |
429 | ||
430 | extern struct clk_ops clk_fixed_factor_ops; | |
431 | struct clk *clk_register_fixed_factor(struct device *dev, const char *name, | |
432 | const char *parent_name, unsigned long flags, | |
433 | unsigned int mult, unsigned int div); | |
434 | ||
e2d0e90f HK |
435 | /** |
436 | * struct clk_fractional_divider - adjustable fractional divider clock | |
437 | * | |
438 | * @hw: handle between common and hardware-specific interfaces | |
439 | * @reg: register containing the divider | |
440 | * @mshift: shift to the numerator bit field | |
441 | * @mwidth: width of the numerator bit field | |
442 | * @nshift: shift to the denominator bit field | |
443 | * @nwidth: width of the denominator bit field | |
444 | * @lock: register lock | |
445 | * | |
446 | * Clock with adjustable fractional divider affecting its output frequency. | |
447 | */ | |
448 | ||
449 | struct clk_fractional_divider { | |
450 | struct clk_hw hw; | |
451 | void __iomem *reg; | |
452 | u8 mshift; | |
453 | u32 mmask; | |
454 | u8 nshift; | |
455 | u32 nmask; | |
456 | u8 flags; | |
457 | spinlock_t *lock; | |
458 | }; | |
459 | ||
460 | extern const struct clk_ops clk_fractional_divider_ops; | |
461 | struct clk *clk_register_fractional_divider(struct device *dev, | |
462 | const char *name, const char *parent_name, unsigned long flags, | |
463 | void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, | |
464 | u8 clk_divider_flags, spinlock_t *lock); | |
465 | ||
ece70094 PG |
466 | /*** |
467 | * struct clk_composite - aggregate clock of mux, divider and gate clocks | |
468 | * | |
469 | * @hw: handle between common and hardware-specific interfaces | |
d3a1c7be MT |
470 | * @mux_hw: handle between composite and hardware-specific mux clock |
471 | * @rate_hw: handle between composite and hardware-specific rate clock | |
472 | * @gate_hw: handle between composite and hardware-specific gate clock | |
ece70094 | 473 | * @mux_ops: clock ops for mux |
d3a1c7be | 474 | * @rate_ops: clock ops for rate |
ece70094 PG |
475 | * @gate_ops: clock ops for gate |
476 | */ | |
477 | struct clk_composite { | |
478 | struct clk_hw hw; | |
479 | struct clk_ops ops; | |
480 | ||
481 | struct clk_hw *mux_hw; | |
d3a1c7be | 482 | struct clk_hw *rate_hw; |
ece70094 PG |
483 | struct clk_hw *gate_hw; |
484 | ||
485 | const struct clk_ops *mux_ops; | |
d3a1c7be | 486 | const struct clk_ops *rate_ops; |
ece70094 PG |
487 | const struct clk_ops *gate_ops; |
488 | }; | |
489 | ||
490 | struct clk *clk_register_composite(struct device *dev, const char *name, | |
491 | const char **parent_names, int num_parents, | |
492 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, | |
d3a1c7be | 493 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
ece70094 PG |
494 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
495 | unsigned long flags); | |
496 | ||
b2476490 MT |
497 | /** |
498 | * clk_register - allocate a new clock, register it and return an opaque cookie | |
499 | * @dev: device that is registering this clock | |
b2476490 | 500 | * @hw: link to hardware-specific clock data |
b2476490 MT |
501 | * |
502 | * clk_register is the primary interface for populating the clock tree with new | |
503 | * clock nodes. It returns a pointer to the newly allocated struct clk which | |
504 | * cannot be dereferenced by driver code but may be used in conjuction with the | |
d1302a36 MT |
505 | * rest of the clock API. In the event of an error clk_register will return an |
506 | * error code; drivers must test for an error code after calling clk_register. | |
b2476490 | 507 | */ |
0197b3ea | 508 | struct clk *clk_register(struct device *dev, struct clk_hw *hw); |
46c8773a | 509 | struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); |
b2476490 | 510 | |
1df5c939 | 511 | void clk_unregister(struct clk *clk); |
46c8773a | 512 | void devm_clk_unregister(struct device *dev, struct clk *clk); |
1df5c939 | 513 | |
b2476490 MT |
514 | /* helper functions */ |
515 | const char *__clk_get_name(struct clk *clk); | |
516 | struct clk_hw *__clk_get_hw(struct clk *clk); | |
517 | u8 __clk_get_num_parents(struct clk *clk); | |
518 | struct clk *__clk_get_parent(struct clk *clk); | |
7ef3dcc8 | 519 | struct clk *clk_get_parent_by_index(struct clk *clk, u8 index); |
93874681 LT |
520 | unsigned int __clk_get_enable_count(struct clk *clk); |
521 | unsigned int __clk_get_prepare_count(struct clk *clk); | |
b2476490 | 522 | unsigned long __clk_get_rate(struct clk *clk); |
5279fc40 | 523 | unsigned long __clk_get_accuracy(struct clk *clk); |
b2476490 | 524 | unsigned long __clk_get_flags(struct clk *clk); |
3d6ee287 | 525 | bool __clk_is_prepared(struct clk *clk); |
2ac6b1f5 | 526 | bool __clk_is_enabled(struct clk *clk); |
b2476490 | 527 | struct clk *__clk_lookup(const char *name); |
e366fdd7 JH |
528 | long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate, |
529 | unsigned long *best_parent_rate, | |
530 | struct clk **best_parent_p); | |
b2476490 MT |
531 | |
532 | /* | |
533 | * FIXME clock api without lock protection | |
534 | */ | |
535 | int __clk_prepare(struct clk *clk); | |
536 | void __clk_unprepare(struct clk *clk); | |
537 | void __clk_reparent(struct clk *clk, struct clk *new_parent); | |
538 | unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); | |
539 | ||
766e6a4e GL |
540 | struct of_device_id; |
541 | ||
542 | typedef void (*of_clk_init_cb_t)(struct device_node *); | |
543 | ||
0b151deb SH |
544 | struct clk_onecell_data { |
545 | struct clk **clks; | |
546 | unsigned int clk_num; | |
547 | }; | |
548 | ||
819b4861 TK |
549 | extern struct of_device_id __clk_of_table; |
550 | ||
54196ccb | 551 | #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) |
0b151deb SH |
552 | |
553 | #ifdef CONFIG_OF | |
766e6a4e GL |
554 | int of_clk_add_provider(struct device_node *np, |
555 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | |
556 | void *data), | |
557 | void *data); | |
558 | void of_clk_del_provider(struct device_node *np); | |
559 | struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, | |
560 | void *data); | |
494bfec9 | 561 | struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); |
f6102742 | 562 | int of_clk_get_parent_count(struct device_node *np); |
766e6a4e | 563 | const char *of_clk_get_parent_name(struct device_node *np, int index); |
f2f6c255 | 564 | |
766e6a4e GL |
565 | void of_clk_init(const struct of_device_id *matches); |
566 | ||
0b151deb | 567 | #else /* !CONFIG_OF */ |
f2f6c255 | 568 | |
0b151deb SH |
569 | static inline int of_clk_add_provider(struct device_node *np, |
570 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | |
571 | void *data), | |
572 | void *data) | |
573 | { | |
574 | return 0; | |
575 | } | |
576 | #define of_clk_del_provider(np) \ | |
577 | { while (0); } | |
578 | static inline struct clk *of_clk_src_simple_get( | |
579 | struct of_phandle_args *clkspec, void *data) | |
580 | { | |
581 | return ERR_PTR(-ENOENT); | |
582 | } | |
583 | static inline struct clk *of_clk_src_onecell_get( | |
584 | struct of_phandle_args *clkspec, void *data) | |
585 | { | |
586 | return ERR_PTR(-ENOENT); | |
587 | } | |
588 | static inline const char *of_clk_get_parent_name(struct device_node *np, | |
589 | int index) | |
590 | { | |
591 | return NULL; | |
592 | } | |
593 | #define of_clk_init(matches) \ | |
594 | { while (0); } | |
595 | #endif /* CONFIG_OF */ | |
aa514ce3 GS |
596 | |
597 | /* | |
598 | * wrap access to peripherals in accessor routines | |
599 | * for improved portability across platforms | |
600 | */ | |
601 | ||
6d8cdb68 GS |
602 | #if IS_ENABLED(CONFIG_PPC) |
603 | ||
604 | static inline u32 clk_readl(u32 __iomem *reg) | |
605 | { | |
606 | return ioread32be(reg); | |
607 | } | |
608 | ||
609 | static inline void clk_writel(u32 val, u32 __iomem *reg) | |
610 | { | |
611 | iowrite32be(val, reg); | |
612 | } | |
613 | ||
614 | #else /* platform dependent I/O accessors */ | |
615 | ||
aa514ce3 GS |
616 | static inline u32 clk_readl(u32 __iomem *reg) |
617 | { | |
618 | return readl(reg); | |
619 | } | |
620 | ||
621 | static inline void clk_writel(u32 val, u32 __iomem *reg) | |
622 | { | |
623 | writel(val, reg); | |
624 | } | |
625 | ||
6d8cdb68 GS |
626 | #endif /* platform dependent I/O accessors */ |
627 | ||
fb2b3c9f PDS |
628 | #ifdef CONFIG_DEBUG_FS |
629 | struct dentry *clk_debugfs_add_file(struct clk *clk, char *name, umode_t mode, | |
630 | void *data, const struct file_operations *fops); | |
631 | #endif | |
632 | ||
b2476490 MT |
633 | #endif /* CONFIG_COMMON_CLK */ |
634 | #endif /* CLK_PROVIDER_H */ |