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ad0dfdfd MP |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* | |
3 | * Copyright (c) 2012, The Linux Foundation. All rights reserved. | |
a06ae860 PP |
4 | */ |
5 | ||
6 | #ifndef _LINUX_CORESIGHT_H | |
7 | #define _LINUX_CORESIGHT_H | |
8 | ||
9 | #include <linux/device.h> | |
882d5e11 | 10 | #include <linux/perf_event.h> |
ff63ec13 | 11 | #include <linux/sched.h> |
a06ae860 PP |
12 | |
13 | /* Peripheral id registers (0xFD0-0xFEC) */ | |
14 | #define CORESIGHT_PERIPHIDR4 0xfd0 | |
15 | #define CORESIGHT_PERIPHIDR5 0xfd4 | |
16 | #define CORESIGHT_PERIPHIDR6 0xfd8 | |
17 | #define CORESIGHT_PERIPHIDR7 0xfdC | |
18 | #define CORESIGHT_PERIPHIDR0 0xfe0 | |
19 | #define CORESIGHT_PERIPHIDR1 0xfe4 | |
20 | #define CORESIGHT_PERIPHIDR2 0xfe8 | |
21 | #define CORESIGHT_PERIPHIDR3 0xfeC | |
22 | /* Component id registers (0xFF0-0xFFC) */ | |
23 | #define CORESIGHT_COMPIDR0 0xff0 | |
24 | #define CORESIGHT_COMPIDR1 0xff4 | |
25 | #define CORESIGHT_COMPIDR2 0xff8 | |
26 | #define CORESIGHT_COMPIDR3 0xffC | |
27 | ||
28 | #define ETM_ARCH_V3_3 0x23 | |
29 | #define ETM_ARCH_V3_5 0x25 | |
30 | #define PFT_ARCH_V1_0 0x30 | |
31 | #define PFT_ARCH_V1_1 0x31 | |
32 | ||
33 | #define CORESIGHT_UNLOCK 0xc5acce55 | |
34 | ||
35 | extern struct bus_type coresight_bustype; | |
36 | ||
37 | enum coresight_dev_type { | |
38 | CORESIGHT_DEV_TYPE_NONE, | |
39 | CORESIGHT_DEV_TYPE_SINK, | |
40 | CORESIGHT_DEV_TYPE_LINK, | |
41 | CORESIGHT_DEV_TYPE_LINKSINK, | |
42 | CORESIGHT_DEV_TYPE_SOURCE, | |
8a091d84 | 43 | CORESIGHT_DEV_TYPE_HELPER, |
a06ae860 PP |
44 | }; |
45 | ||
46 | enum coresight_dev_subtype_sink { | |
47 | CORESIGHT_DEV_SUBTYPE_SINK_NONE, | |
48 | CORESIGHT_DEV_SUBTYPE_SINK_PORT, | |
49 | CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, | |
50 | }; | |
51 | ||
52 | enum coresight_dev_subtype_link { | |
53 | CORESIGHT_DEV_SUBTYPE_LINK_NONE, | |
54 | CORESIGHT_DEV_SUBTYPE_LINK_MERG, | |
55 | CORESIGHT_DEV_SUBTYPE_LINK_SPLIT, | |
56 | CORESIGHT_DEV_SUBTYPE_LINK_FIFO, | |
57 | }; | |
58 | ||
59 | enum coresight_dev_subtype_source { | |
60 | CORESIGHT_DEV_SUBTYPE_SOURCE_NONE, | |
61 | CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, | |
62 | CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, | |
63 | CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, | |
64 | }; | |
65 | ||
8a091d84 SP |
66 | enum coresight_dev_subtype_helper { |
67 | CORESIGHT_DEV_SUBTYPE_HELPER_NONE, | |
fcacb5c1 | 68 | CORESIGHT_DEV_SUBTYPE_HELPER_CATU, |
8a091d84 SP |
69 | }; |
70 | ||
a06ae860 | 71 | /** |
00b78e8b | 72 | * union coresight_dev_subtype - further characterisation of a type |
a06ae860 | 73 | * @sink_subtype: type of sink this component is, as defined |
00b78e8b | 74 | * by @coresight_dev_subtype_sink. |
a06ae860 | 75 | * @link_subtype: type of link this component is, as defined |
00b78e8b | 76 | * by @coresight_dev_subtype_link. |
a06ae860 | 77 | * @source_subtype: type of source this component is, as defined |
00b78e8b | 78 | * by @coresight_dev_subtype_source. |
8a091d84 SP |
79 | * @helper_subtype: type of helper this component is, as defined |
80 | * by @coresight_dev_subtype_helper. | |
a06ae860 | 81 | */ |
00b78e8b SP |
82 | union coresight_dev_subtype { |
83 | /* We have some devices which acts as LINK and SINK */ | |
84 | struct { | |
85 | enum coresight_dev_subtype_sink sink_subtype; | |
86 | enum coresight_dev_subtype_link link_subtype; | |
87 | }; | |
a06ae860 | 88 | enum coresight_dev_subtype_source source_subtype; |
8a091d84 | 89 | enum coresight_dev_subtype_helper helper_subtype; |
a06ae860 PP |
90 | }; |
91 | ||
92 | /** | |
93 | * struct coresight_platform_data - data harvested from the DT specification | |
94 | * @cpu: the CPU a source belongs to. Only applicable for ETM/PTMs. | |
95 | * @name: name of the component as shown under sysfs. | |
96 | * @nr_inport: number of input ports for this component. | |
a06ae860 | 97 | * @nr_outport: number of output ports for this component. |
c2c72941 | 98 | * @conns: Array of nr_outport connections from this component |
a06ae860 PP |
99 | */ |
100 | struct coresight_platform_data { | |
101 | int cpu; | |
102 | const char *name; | |
103 | int nr_inport; | |
a06ae860 | 104 | int nr_outport; |
c2c72941 | 105 | struct coresight_connection *conns; |
a06ae860 PP |
106 | }; |
107 | ||
108 | /** | |
109 | * struct coresight_desc - description of a component required from drivers | |
110 | * @type: as defined by @coresight_dev_type. | |
111 | * @subtype: as defined by @coresight_dev_subtype. | |
112 | * @ops: generic operations for this component, as defined | |
113 | by @coresight_ops. | |
114 | * @pdata: platform data collected from DT. | |
115 | * @dev: The device entity associated to this component. | |
8ee885a9 | 116 | * @groups: operations specific to this component. These will end up |
a06ae860 PP |
117 | in the component's sysfs sub-directory. |
118 | */ | |
119 | struct coresight_desc { | |
120 | enum coresight_dev_type type; | |
00b78e8b | 121 | union coresight_dev_subtype subtype; |
a06ae860 PP |
122 | const struct coresight_ops *ops; |
123 | struct coresight_platform_data *pdata; | |
124 | struct device *dev; | |
125 | const struct attribute_group **groups; | |
126 | }; | |
127 | ||
128 | /** | |
129 | * struct coresight_connection - representation of a single connection | |
a06ae860 PP |
130 | * @outport: a connection's output port number. |
131 | * @chid_name: remote component's name. | |
132 | * @child_port: remote component's port number @output is connected to. | |
133 | * @child_dev: a @coresight_device representation of the component | |
134 | connected to @outport. | |
135 | */ | |
136 | struct coresight_connection { | |
137 | int outport; | |
138 | const char *child_name; | |
139 | int child_port; | |
140 | struct coresight_device *child_dev; | |
141 | }; | |
142 | ||
143 | /** | |
144 | * struct coresight_device - representation of a device as used by the framework | |
8ee885a9 | 145 | * @conns: array of coresight_connections associated to this component. |
a06ae860 PP |
146 | * @nr_inport: number of input port associated to this component. |
147 | * @nr_outport: number of output port associated to this component. | |
148 | * @type: as defined by @coresight_dev_type. | |
149 | * @subtype: as defined by @coresight_dev_subtype. | |
150 | * @ops: generic operations for this component, as defined | |
151 | by @coresight_ops. | |
152 | * @dev: The device entity associated to this component. | |
153 | * @refcnt: keep track of what is in use. | |
a06ae860 PP |
154 | * @orphan: true if the component has connections that haven't been linked. |
155 | * @enable: 'true' if component is currently part of an active path. | |
156 | * @activated: 'true' only if a _sink_ has been activated. A sink can be | |
bb8e370b MP |
157 | * activated but not yet enabled. Enabling for a _sink_ |
158 | * appens when a source has been selected for that it. | |
159 | * @ea: Device attribute for sink representation under PMU directory. | |
a06ae860 PP |
160 | */ |
161 | struct coresight_device { | |
162 | struct coresight_connection *conns; | |
163 | int nr_inport; | |
164 | int nr_outport; | |
165 | enum coresight_dev_type type; | |
00b78e8b | 166 | union coresight_dev_subtype subtype; |
a06ae860 PP |
167 | const struct coresight_ops *ops; |
168 | struct device dev; | |
169 | atomic_t *refcnt; | |
a06ae860 PP |
170 | bool orphan; |
171 | bool enable; /* true only if configured as part of a path */ | |
bb8e370b | 172 | /* sink specific fields */ |
a06ae860 | 173 | bool activated; /* true only if a sink is part of a path */ |
bb8e370b | 174 | struct dev_ext_attribute *ea; |
a06ae860 PP |
175 | }; |
176 | ||
177 | #define to_coresight_device(d) container_of(d, struct coresight_device, dev) | |
178 | ||
179 | #define source_ops(csdev) csdev->ops->source_ops | |
180 | #define sink_ops(csdev) csdev->ops->sink_ops | |
181 | #define link_ops(csdev) csdev->ops->link_ops | |
8a091d84 | 182 | #define helper_ops(csdev) csdev->ops->helper_ops |
a06ae860 | 183 | |
a06ae860 PP |
184 | /** |
185 | * struct coresight_ops_sink - basic operations for a sink | |
186 | * Operations available for sinks | |
2997aa40 MP |
187 | * @enable: enables the sink. |
188 | * @disable: disables the sink. | |
189 | * @alloc_buffer: initialises perf's ring buffer for trace collection. | |
190 | * @free_buffer: release memory allocated in @get_config. | |
2997aa40 | 191 | * @update_buffer: update buffer pointers after a trace session. |
a06ae860 PP |
192 | */ |
193 | struct coresight_ops_sink { | |
3d6e8935 | 194 | int (*enable)(struct coresight_device *csdev, u32 mode, void *data); |
6c817a95 | 195 | int (*disable)(struct coresight_device *csdev); |
a0f08a6a MP |
196 | void *(*alloc_buffer)(struct coresight_device *csdev, |
197 | struct perf_event *event, void **pages, | |
198 | int nr_pages, bool overwrite); | |
2997aa40 | 199 | void (*free_buffer)(void *config); |
7ec786ad | 200 | unsigned long (*update_buffer)(struct coresight_device *csdev, |
2997aa40 MP |
201 | struct perf_output_handle *handle, |
202 | void *sink_config); | |
a06ae860 PP |
203 | }; |
204 | ||
205 | /** | |
206 | * struct coresight_ops_link - basic operations for a link | |
207 | * Operations available for links. | |
208 | * @enable: enables flow between iport and oport. | |
209 | * @disable: disables flow between iport and oport. | |
210 | */ | |
211 | struct coresight_ops_link { | |
212 | int (*enable)(struct coresight_device *csdev, int iport, int oport); | |
213 | void (*disable)(struct coresight_device *csdev, int iport, int oport); | |
214 | }; | |
215 | ||
216 | /** | |
217 | * struct coresight_ops_source - basic operations for a source | |
218 | * Operations available for sources. | |
52210c87 MP |
219 | * @cpu_id: returns the value of the CPU number this component |
220 | * is associated to. | |
a06ae860 | 221 | * @trace_id: returns the value of the component's trace ID as known |
882d5e11 | 222 | * to the HW. |
1d27ff5a | 223 | * @enable: enables tracing for a source. |
a06ae860 PP |
224 | * @disable: disables tracing for a source. |
225 | */ | |
226 | struct coresight_ops_source { | |
52210c87 | 227 | int (*cpu_id)(struct coresight_device *csdev); |
a06ae860 | 228 | int (*trace_id)(struct coresight_device *csdev); |
882d5e11 | 229 | int (*enable)(struct coresight_device *csdev, |
68905d73 MP |
230 | struct perf_event *event, u32 mode); |
231 | void (*disable)(struct coresight_device *csdev, | |
232 | struct perf_event *event); | |
a06ae860 PP |
233 | }; |
234 | ||
8a091d84 SP |
235 | /** |
236 | * struct coresight_ops_helper - Operations for a helper device. | |
237 | * | |
238 | * All operations could pass in a device specific data, which could | |
239 | * help the helper device to determine what to do. | |
240 | * | |
241 | * @enable : Enable the device | |
242 | * @disable : Disable the device | |
243 | */ | |
244 | struct coresight_ops_helper { | |
245 | int (*enable)(struct coresight_device *csdev, void *data); | |
246 | int (*disable)(struct coresight_device *csdev, void *data); | |
247 | }; | |
248 | ||
a06ae860 PP |
249 | struct coresight_ops { |
250 | const struct coresight_ops_sink *sink_ops; | |
251 | const struct coresight_ops_link *link_ops; | |
252 | const struct coresight_ops_source *source_ops; | |
8a091d84 | 253 | const struct coresight_ops_helper *helper_ops; |
a06ae860 PP |
254 | }; |
255 | ||
256 | #ifdef CONFIG_CORESIGHT | |
257 | extern struct coresight_device * | |
258 | coresight_register(struct coresight_desc *desc); | |
259 | extern void coresight_unregister(struct coresight_device *csdev); | |
260 | extern int coresight_enable(struct coresight_device *csdev); | |
261 | extern void coresight_disable(struct coresight_device *csdev); | |
a06ae860 PP |
262 | extern int coresight_timeout(void __iomem *addr, u32 offset, |
263 | int position, int value); | |
2478a6ae SP |
264 | |
265 | extern int coresight_claim_device(void __iomem *base); | |
266 | extern int coresight_claim_device_unlocked(void __iomem *base); | |
267 | ||
268 | extern void coresight_disclaim_device(void __iomem *base); | |
269 | extern void coresight_disclaim_device_unlocked(void __iomem *base); | |
270 | ||
a06ae860 PP |
271 | #else |
272 | static inline struct coresight_device * | |
273 | coresight_register(struct coresight_desc *desc) { return NULL; } | |
274 | static inline void coresight_unregister(struct coresight_device *csdev) {} | |
275 | static inline int | |
276 | coresight_enable(struct coresight_device *csdev) { return -ENOSYS; } | |
277 | static inline void coresight_disable(struct coresight_device *csdev) {} | |
a06ae860 PP |
278 | static inline int coresight_timeout(void __iomem *addr, u32 offset, |
279 | int position, int value) { return 1; } | |
2478a6ae SP |
280 | static inline int coresight_claim_device_unlocked(void __iomem *base) |
281 | { | |
282 | return -EINVAL; | |
283 | } | |
284 | ||
285 | static inline int coresight_claim_device(void __iomem *base) | |
286 | { | |
287 | return -EINVAL; | |
288 | } | |
289 | ||
290 | static inline void coresight_disclaim_device(void __iomem *base) {} | |
291 | static inline void coresight_disclaim_device_unlocked(void __iomem *base) {} | |
292 | ||
c61c4b5d MP |
293 | #endif |
294 | ||
a06ae860 | 295 | #ifdef CONFIG_OF |
c56cdd7a | 296 | extern int of_coresight_get_cpu(const struct device_node *node); |
f42fe520 LY |
297 | extern struct coresight_platform_data * |
298 | of_get_coresight_platform_data(struct device *dev, | |
299 | const struct device_node *node); | |
c61c4b5d | 300 | #else |
c56cdd7a LY |
301 | static inline int of_coresight_get_cpu(const struct device_node *node) |
302 | { return 0; } | |
a06ae860 | 303 | static inline struct coresight_platform_data *of_get_coresight_platform_data( |
f42fe520 | 304 | struct device *dev, const struct device_node *node) { return NULL; } |
a06ae860 | 305 | #endif |
a06ae860 PP |
306 | |
307 | #endif |