[mirror_ubuntu-jammy-kernel.git] / include / linux / coresight.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2012, The Linux Foundation. All rights reserved.
 */

#ifndef _LINUX_CORESIGHT_H
#define _LINUX_CORESIGHT_H

#include <linux/device.h>
#include <linux/io.h>
#include <linux/perf_event.h>
#include <linux/sched.h>

/* Peripheral id registers (0xFD0-0xFEC) */
#define CORESIGHT_PERIPHIDR4	0xfd0
#define CORESIGHT_PERIPHIDR5	0xfd4
#define CORESIGHT_PERIPHIDR6	0xfd8
#define CORESIGHT_PERIPHIDR7	0xfdC
#define CORESIGHT_PERIPHIDR0	0xfe0
#define CORESIGHT_PERIPHIDR1	0xfe4
#define CORESIGHT_PERIPHIDR2	0xfe8
#define CORESIGHT_PERIPHIDR3	0xfeC
/* Component id registers (0xFF0-0xFFC) */
#define CORESIGHT_COMPIDR0	0xff0
#define CORESIGHT_COMPIDR1	0xff4
#define CORESIGHT_COMPIDR2	0xff8
#define CORESIGHT_COMPIDR3	0xffC

#define ETM_ARCH_V3_3		0x23
#define ETM_ARCH_V3_5		0x25
#define PFT_ARCH_V1_0		0x30
#define PFT_ARCH_V1_1		0x31

#define CORESIGHT_UNLOCK	0xc5acce55

extern struct bus_type coresight_bustype;

enum coresight_dev_type {
	CORESIGHT_DEV_TYPE_NONE,
	CORESIGHT_DEV_TYPE_SINK,
	CORESIGHT_DEV_TYPE_LINK,
	CORESIGHT_DEV_TYPE_LINKSINK,
	CORESIGHT_DEV_TYPE_SOURCE,
	CORESIGHT_DEV_TYPE_HELPER,
	CORESIGHT_DEV_TYPE_ECT,
};

enum coresight_dev_subtype_sink {
	CORESIGHT_DEV_SUBTYPE_SINK_NONE,
	CORESIGHT_DEV_SUBTYPE_SINK_PORT,
	CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
	CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
	CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,
};

enum coresight_dev_subtype_link {
	CORESIGHT_DEV_SUBTYPE_LINK_NONE,
	CORESIGHT_DEV_SUBTYPE_LINK_MERG,
	CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
	CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
};

enum coresight_dev_subtype_source {
	CORESIGHT_DEV_SUBTYPE_SOURCE_NONE,
	CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
	CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
	CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
};

enum coresight_dev_subtype_helper {
	CORESIGHT_DEV_SUBTYPE_HELPER_NONE,
	CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
};

/* Embedded Cross Trigger (ECT) sub-types */
enum coresight_dev_subtype_ect {
	CORESIGHT_DEV_SUBTYPE_ECT_NONE,
	CORESIGHT_DEV_SUBTYPE_ECT_CTI,
};

/**
 * union coresight_dev_subtype - further characterisation of a type
 * @sink_subtype:	type of sink this component is, as defined
 *			by @coresight_dev_subtype_sink.
 * @link_subtype:	type of link this component is, as defined
 *			by @coresight_dev_subtype_link.
 * @source_subtype:	type of source this component is, as defined
 *			by @coresight_dev_subtype_source.
 * @helper_subtype:	type of helper this component is, as defined
 *			by @coresight_dev_subtype_helper.
 * @ect_subtype:        type of cross trigger this component is, as
 *			defined by @coresight_dev_subtype_ect
 */
union coresight_dev_subtype {
	/* We have some devices which acts as LINK and SINK */
	struct {
		enum coresight_dev_subtype_sink sink_subtype;
		enum coresight_dev_subtype_link link_subtype;
	};
	enum coresight_dev_subtype_source source_subtype;
	enum coresight_dev_subtype_helper helper_subtype;
	enum coresight_dev_subtype_ect ect_subtype;
};

/**
 * struct coresight_platform_data - data harvested from the firmware
 * specification.
 *
 * @nr_inport:	Number of elements for the input connections.
 * @nr_outport:	Number of elements for the output connections.
 * @conns:	Sparse array of nr_outport connections from this component.
 */
struct coresight_platform_data {
	int nr_inport;
	int nr_outport;
	struct coresight_connection *conns;
};

/**
 * struct csdev_access - Abstraction of a CoreSight device access.
 *
 * @io_mem	: True if the device has memory mapped I/O
 * @base	: When io_mem == true, base address of the component
 * @read	: Read from the given "offset" of the given instance.
 * @write	: Write "val" to the given "offset".
 */
struct csdev_access {
	bool io_mem;
	union {
		void __iomem *base;
		struct {
			u64 (*read)(u32 offset, bool relaxed, bool _64bit);
			void (*write)(u64 val, u32 offset, bool relaxed,
				      bool _64bit);
		};
	};
};

#define CSDEV_ACCESS_IOMEM(_addr)		\
	((struct csdev_access)	{		\
		.io_mem		= true,		\
		.base		= (_addr),	\
	})

/**
 * struct coresight_desc - description of a component required from drivers
 * @type:	as defined by @coresight_dev_type.
 * @subtype:	as defined by @coresight_dev_subtype.
 * @ops:	generic operations for this component, as defined
 *		by @coresight_ops.
 * @pdata:	platform data collected from DT.
 * @dev:	The device entity associated to this component.
 * @groups:	operations specific to this component. These will end up
 *		in the component's sysfs sub-directory.
 * @name:	name for the coresight device, also shown under sysfs.
 * @access:	Describe access to the device
 */
struct coresight_desc {
	enum coresight_dev_type type;
	union coresight_dev_subtype subtype;
	const struct coresight_ops *ops;
	struct coresight_platform_data *pdata;
	struct device *dev;
	const struct attribute_group **groups;
	const char *name;
	struct csdev_access access;
};

/**
 * struct coresight_connection - representation of a single connection
 * @outport:	a connection's output port number.
 * @child_port:	remote component's port number @output is connected to.
 * @chid_fwnode: remote component's fwnode handle.
 * @child_dev:	a @coresight_device representation of the component
		connected to @outport.
 * @link: Representation of the connection as a sysfs link.
 */
struct coresight_connection {
	int outport;
	int child_port;
	struct fwnode_handle *child_fwnode;
	struct coresight_device *child_dev;
	struct coresight_sysfs_link *link;
};

/**
 * struct coresight_sysfs_link - representation of a connection in sysfs.
 * @orig:		Originating (master) coresight device for the link.
 * @orig_name:		Name to use for the link orig->target.
 * @target:		Target (slave) coresight device for the link.
 * @target_name:	Name to use for the link target->orig.
 */
struct coresight_sysfs_link {
	struct coresight_device *orig;
	const char *orig_name;
	struct coresight_device *target;
	const char *target_name;
};

/**
 * struct coresight_device - representation of a device as used by the framework
 * @pdata:	Platform data with device connections associated to this device.
 * @type:	as defined by @coresight_dev_type.
 * @subtype:	as defined by @coresight_dev_subtype.
 * @ops:	generic operations for this component, as defined
 *		by @coresight_ops.
 * @access:	Device i/o access abstraction for this device.
 * @dev:	The device entity associated to this component.
 * @refcnt:	keep track of what is in use.
 * @orphan:	true if the component has connections that haven't been linked.
 * @enable:	'true' if component is currently part of an active path.
 * @activated:	'true' only if a _sink_ has been activated.  A sink can be
 *		activated but not yet enabled.  Enabling for a _sink_
 *		happens when a source has been selected and a path is enabled
 *		from source to that sink.
 * @ea:		Device attribute for sink representation under PMU directory.
 * @def_sink:	cached reference to default sink found for this device.
 * @ect_dev:	Associated cross trigger device. Not part of the trace data
 *		path or connections.
 * @nr_links:   number of sysfs links created to other components from this
 *		device. These will appear in the "connections" group.
 * @has_conns_grp: Have added a "connections" group for sysfs links.
 */
struct coresight_device {
	struct coresight_platform_data *pdata;
	enum coresight_dev_type type;
	union coresight_dev_subtype subtype;
	const struct coresight_ops *ops;
	struct csdev_access access;
	struct device dev;
	atomic_t *refcnt;
	bool orphan;
	bool enable;	/* true only if configured as part of a path */
	/* sink specific fields */
	bool activated;	/* true only if a sink is part of a path */
	struct dev_ext_attribute *ea;
	struct coresight_device *def_sink;
	/* cross trigger handling */
	struct coresight_device *ect_dev;
	/* sysfs links between components */
	int nr_links;
	bool has_conns_grp;
	bool ect_enabled; /* true only if associated ect device is enabled */
};

/*
 * coresight_dev_list - Mapping for devices to "name" index for device
 * names.
 *
 * @nr_idx:		Number of entries already allocated.
 * @pfx:		Prefix pattern for device name.
 * @fwnode_list:	Array of fwnode_handles associated with each allocated
 *			index, upto nr_idx entries.
 */
struct coresight_dev_list {
	int			nr_idx;
	const char		*pfx;
	struct fwnode_handle	**fwnode_list;
};

#define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx)				\
static struct coresight_dev_list (var) = {				\
						.pfx = dev_pfx,		\
						.nr_idx = 0,		\
						.fwnode_list = NULL,	\
}

#define to_coresight_device(d) container_of(d, struct coresight_device, dev)

#define source_ops(csdev)	csdev->ops->source_ops
#define sink_ops(csdev)		csdev->ops->sink_ops
#define link_ops(csdev)		csdev->ops->link_ops
#define helper_ops(csdev)	csdev->ops->helper_ops
#define ect_ops(csdev)		csdev->ops->ect_ops

/**
 * struct coresight_ops_sink - basic operations for a sink
 * Operations available for sinks
 * @enable:		enables the sink.
 * @disable:		disables the sink.
 * @alloc_buffer:	initialises perf's ring buffer for trace collection.
 * @free_buffer:	release memory allocated in @get_config.
 * @update_buffer:	update buffer pointers after a trace session.
 */
struct coresight_ops_sink {
	int (*enable)(struct coresight_device *csdev, u32 mode, void *data);
	int (*disable)(struct coresight_device *csdev);
	void *(*alloc_buffer)(struct coresight_device *csdev,
			      struct perf_event *event, void **pages,
			      int nr_pages, bool overwrite);
	void (*free_buffer)(void *config);
	unsigned long (*update_buffer)(struct coresight_device *csdev,
			      struct perf_output_handle *handle,
			      void *sink_config);
};

/**
 * struct coresight_ops_link - basic operations for a link
 * Operations available for links.
 * @enable:	enables flow between iport and oport.
 * @disable:	disables flow between iport and oport.
 */
struct coresight_ops_link {
	int (*enable)(struct coresight_device *csdev, int iport, int oport);
	void (*disable)(struct coresight_device *csdev, int iport, int oport);
};

/**
 * struct coresight_ops_source - basic operations for a source
 * Operations available for sources.
 * @cpu_id:	returns the value of the CPU number this component
 *		is associated to.
 * @trace_id:	returns the value of the component's trace ID as known
 *		to the HW.
 * @enable:	enables tracing for a source.
 * @disable:	disables tracing for a source.
 */
struct coresight_ops_source {
	int (*cpu_id)(struct coresight_device *csdev);
	int (*trace_id)(struct coresight_device *csdev);
	int (*enable)(struct coresight_device *csdev,
		      struct perf_event *event,  u32 mode);
	void (*disable)(struct coresight_device *csdev,
			struct perf_event *event);
};

/**
 * struct coresight_ops_helper - Operations for a helper device.
 *
 * All operations could pass in a device specific data, which could
 * help the helper device to determine what to do.
 *
 * @enable	: Enable the device
 * @disable	: Disable the device
 */
struct coresight_ops_helper {
	int (*enable)(struct coresight_device *csdev, void *data);
	int (*disable)(struct coresight_device *csdev, void *data);
};

/**
 * struct coresight_ops_ect - Ops for an embedded cross trigger device
 *
 * @enable	: Enable the device
 * @disable	: Disable the device
 */
struct coresight_ops_ect {
	int (*enable)(struct coresight_device *csdev);
	int (*disable)(struct coresight_device *csdev);
};

struct coresight_ops {
	const struct coresight_ops_sink *sink_ops;
	const struct coresight_ops_link *link_ops;
	const struct coresight_ops_source *source_ops;
	const struct coresight_ops_helper *helper_ops;
	const struct coresight_ops_ect *ect_ops;
};

#if IS_ENABLED(CONFIG_CORESIGHT)

static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa,
					      u32 offset)
{
	if (likely(csa->io_mem))
		return readl_relaxed(csa->base + offset);

	return csa->read(offset, true, false);
}

static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset)
{
	if (likely(csa->io_mem))
		return readl(csa->base + offset);

	return csa->read(offset, false, false);
}

static inline void csdev_access_relaxed_write32(struct csdev_access *csa,
						u32 val, u32 offset)
{
	if (likely(csa->io_mem))
		writel_relaxed(val, csa->base + offset);
	else
		csa->write(val, offset, true, false);
}

static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset)
{
	if (likely(csa->io_mem))
		writel(val, csa->base + offset);
	else
		csa->write(val, offset, false, false);
}

#ifdef CONFIG_64BIT

static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
					      u32 offset)
{
	if (likely(csa->io_mem))
		return readq_relaxed(csa->base + offset);

	return csa->read(offset, true, true);
}

static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
{
	if (likely(csa->io_mem))
		return readq(csa->base + offset);

	return csa->read(offset, false, true);
}

static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
						u64 val, u32 offset)
{
	if (likely(csa->io_mem))
		writeq_relaxed(val, csa->base + offset);
	else
		csa->write(val, offset, true, true);
}

static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
{
	if (likely(csa->io_mem))
		writeq(val, csa->base + offset);
	else
		csa->write(val, offset, false, true);
}

#else	/* !CONFIG_64BIT */

static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
					      u32 offset)
{
	WARN_ON(1);
	return 0;
}

static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
{
	WARN_ON(1);
	return 0;
}

static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
						u64 val, u32 offset)
{
	WARN_ON(1);
}

static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
{
	WARN_ON(1);
}
#endif	/* CONFIG_64BIT */

static inline bool coresight_is_percpu_source(struct coresight_device *csdev)
{
	return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) &&
	       (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC);
}

static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)
{
	return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) &&
	       (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM);
}

extern struct coresight_device *
coresight_register(struct coresight_desc *desc);
extern void coresight_unregister(struct coresight_device *csdev);
extern int coresight_enable(struct coresight_device *csdev);
extern void coresight_disable(struct coresight_device *csdev);
extern int coresight_timeout(struct csdev_access *csa, u32 offset,
			     int position, int value);

extern int coresight_claim_device(struct coresight_device *csdev);
extern int coresight_claim_device_unlocked(struct coresight_device *csdev);

extern void coresight_disclaim_device(struct coresight_device *csdev);
extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev);
extern char *coresight_alloc_device_name(struct coresight_dev_list *devs,
					 struct device *dev);

extern bool coresight_loses_context_with_cpu(struct device *dev);

u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset);
u32 coresight_read32(struct coresight_device *csdev, u32 offset);
void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset);
void coresight_relaxed_write32(struct coresight_device *csdev,
			       u32 val, u32 offset);
u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset);
u64 coresight_read64(struct coresight_device *csdev, u32 offset);
void coresight_relaxed_write64(struct coresight_device *csdev,
			       u64 val, u32 offset);
void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset);

#else
static inline struct coresight_device *
coresight_register(struct coresight_desc *desc) { return NULL; }
static inline void coresight_unregister(struct coresight_device *csdev) {}
static inline int
coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
static inline void coresight_disable(struct coresight_device *csdev) {}

static inline int coresight_timeout(struct csdev_access *csa, u32 offset,
				    int position, int value)
{
	return 1;
}

static inline int coresight_claim_device_unlocked(struct coresight_device *csdev)
{
	return -EINVAL;
}

static inline int coresight_claim_device(struct coresight_device *csdev)
{
	return -EINVAL;
}

static inline void coresight_disclaim_device(struct coresight_device *csdev) {}
static inline void coresight_disclaim_device_unlocked(struct coresight_device *csdev) {}

static inline bool coresight_loses_context_with_cpu(struct device *dev)
{
	return false;
}

static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset)
{
	WARN_ON_ONCE(1);
	return 0;
}

static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset)
{
	WARN_ON_ONCE(1);
	return 0;
}

static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset)
{
}

static inline void coresight_relaxed_write32(struct coresight_device *csdev,
					     u32 val, u32 offset)
{
}

static inline u64 coresight_relaxed_read64(struct coresight_device *csdev,
					   u32 offset)
{
	WARN_ON_ONCE(1);
	return 0;
}

static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset)
{
	WARN_ON_ONCE(1);
	return 0;
}

static inline void coresight_relaxed_write64(struct coresight_device *csdev,
					     u64 val, u32 offset)
{
}

static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset)
{
}

#endif		/* IS_ENABLED(CONFIG_CORESIGHT) */

extern int coresight_get_cpu(struct device *dev);

struct coresight_platform_data *coresight_get_platform_data(struct device *dev);

#endif		/* _LINUX_COREISGHT_H */
Commit	Line	Data
ad0dfdfd MP	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Copyright (c) 2012, The Linux Foundation. All rights reserved.
a06ae860 PP	4	*/
	5
	6	#ifndef _LINUX_CORESIGHT_H
	7	#define _LINUX_CORESIGHT_H
	8
	9	#include <linux/device.h>
6e736c60	10	#include <linux/io.h>
882d5e11	11	#include <linux/perf_event.h>
ff63ec13	12	#include <linux/sched.h>
a06ae860 PP	13
	14	/* Peripheral id registers (0xFD0-0xFEC) */
	15	#define CORESIGHT_PERIPHIDR4 0xfd0
	16	#define CORESIGHT_PERIPHIDR5 0xfd4
	17	#define CORESIGHT_PERIPHIDR6 0xfd8
	18	#define CORESIGHT_PERIPHIDR7 0xfdC
	19	#define CORESIGHT_PERIPHIDR0 0xfe0
	20	#define CORESIGHT_PERIPHIDR1 0xfe4
	21	#define CORESIGHT_PERIPHIDR2 0xfe8
	22	#define CORESIGHT_PERIPHIDR3 0xfeC
	23	/* Component id registers (0xFF0-0xFFC) */
	24	#define CORESIGHT_COMPIDR0 0xff0
	25	#define CORESIGHT_COMPIDR1 0xff4
	26	#define CORESIGHT_COMPIDR2 0xff8
	27	#define CORESIGHT_COMPIDR3 0xffC
	28
	29	#define ETM_ARCH_V3_3 0x23
	30	#define ETM_ARCH_V3_5 0x25
	31	#define PFT_ARCH_V1_0 0x30
	32	#define PFT_ARCH_V1_1 0x31
	33
	34	#define CORESIGHT_UNLOCK 0xc5acce55
	35
	36	extern struct bus_type coresight_bustype;
	37
	38	enum coresight_dev_type {
	39	CORESIGHT_DEV_TYPE_NONE,
	40	CORESIGHT_DEV_TYPE_SINK,
	41	CORESIGHT_DEV_TYPE_LINK,
	42	CORESIGHT_DEV_TYPE_LINKSINK,
	43	CORESIGHT_DEV_TYPE_SOURCE,
8a091d84	44	CORESIGHT_DEV_TYPE_HELPER,
835d722b	45	CORESIGHT_DEV_TYPE_ECT,
a06ae860 PP	46	};
	47
	48	enum coresight_dev_subtype_sink {
	49	CORESIGHT_DEV_SUBTYPE_SINK_NONE,
	50	CORESIGHT_DEV_SUBTYPE_SINK_PORT,
	51	CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
0336bdfd	52	CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
2cd87a7b	53	CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,
a06ae860 PP	54	};
	55
	56	enum coresight_dev_subtype_link {
	57	CORESIGHT_DEV_SUBTYPE_LINK_NONE,
	58	CORESIGHT_DEV_SUBTYPE_LINK_MERG,
	59	CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
	60	CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
	61	};
	62
	63	enum coresight_dev_subtype_source {
	64	CORESIGHT_DEV_SUBTYPE_SOURCE_NONE,
	65	CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
	66	CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
	67	CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
	68	};
	69
8a091d84 SP	70	enum coresight_dev_subtype_helper {
8a091d84 SP	71	CORESIGHT_DEV_SUBTYPE_HELPER_NONE,
fcacb5c1	72	CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
8a091d84 SP	73	};
8a091d84 SP	74
835d722b ML	75	/* Embedded Cross Trigger (ECT) sub-types */
	76	enum coresight_dev_subtype_ect {
	77	CORESIGHT_DEV_SUBTYPE_ECT_NONE,
	78	CORESIGHT_DEV_SUBTYPE_ECT_CTI,
	79	};
	80
a06ae860	81	/**
00b78e8b	82	* union coresight_dev_subtype - further characterisation of a type
a06ae860	83	* @sink_subtype: type of sink this component is, as defined
00b78e8b	84	* by @coresight_dev_subtype_sink.
a06ae860	85	* @link_subtype: type of link this component is, as defined
00b78e8b	86	* by @coresight_dev_subtype_link.
a06ae860	87	* @source_subtype: type of source this component is, as defined
00b78e8b	88	* by @coresight_dev_subtype_source.
8a091d84 SP	89	* @helper_subtype: type of helper this component is, as defined
8a091d84 SP	90	* by @coresight_dev_subtype_helper.
835d722b ML	91	* @ect_subtype: type of cross trigger this component is, as
835d722b ML	92	* defined by @coresight_dev_subtype_ect
a06ae860	93	*/
00b78e8b SP	94	union coresight_dev_subtype {
	95	/* We have some devices which acts as LINK and SINK */
	96	struct {
	97	enum coresight_dev_subtype_sink sink_subtype;
	98	enum coresight_dev_subtype_link link_subtype;
	99	};
a06ae860	100	enum coresight_dev_subtype_source source_subtype;
8a091d84	101	enum coresight_dev_subtype_helper helper_subtype;
835d722b	102	enum coresight_dev_subtype_ect ect_subtype;
a06ae860 PP	103	};
	104
	105	/**
d375b356 SP	106	* struct coresight_platform_data - data harvested from the firmware
	107	* specification.
	108	*
	109	* @nr_inport: Number of elements for the input connections.
	110	* @nr_outport: Number of elements for the output connections.
	111	* @conns: Sparse array of nr_outport connections from this component.
a06ae860 PP	112	*/
a06ae860 PP	113	struct coresight_platform_data {
a06ae860	114	int nr_inport;
a06ae860	115	int nr_outport;
c2c72941	116	struct coresight_connection *conns;
a06ae860 PP	117	};
a06ae860 PP	118
6e736c60 SP	119	/**
	120	* struct csdev_access - Abstraction of a CoreSight device access.
	121	*
	122	* @io_mem : True if the device has memory mapped I/O
	123	* @base : When io_mem == true, base address of the component
	124	* @read : Read from the given "offset" of the given instance.
	125	* @write : Write "val" to the given "offset".
	126	*/
	127	struct csdev_access {
	128	bool io_mem;
	129	union {
	130	void __iomem *base;
	131	struct {
	132	u64 (*read)(u32 offset, bool relaxed, bool _64bit);
	133	void (*write)(u64 val, u32 offset, bool relaxed,
	134	bool _64bit);
	135	};
	136	};
	137	};
	138
	139	#define CSDEV_ACCESS_IOMEM(_addr) \
	140	((struct csdev_access) { \
	141	.io_mem = true, \
	142	.base = (_addr), \
	143	})
	144
a06ae860 PP	145	/**
	146	* struct coresight_desc - description of a component required from drivers
	147	* @type: as defined by @coresight_dev_type.
	148	* @subtype: as defined by @coresight_dev_subtype.
	149	* @ops: generic operations for this component, as defined
2ede79a6	150	* by @coresight_ops.
a06ae860 PP	151	* @pdata: platform data collected from DT.
a06ae860 PP	152	* @dev: The device entity associated to this component.
8ee885a9	153	* @groups: operations specific to this component. These will end up
2ede79a6 SP	154	* in the component's sysfs sub-directory.
2ede79a6 SP	155	* @name: name for the coresight device, also shown under sysfs.
6e736c60	156	* @access: Describe access to the device
a06ae860 PP	157	*/
	158	struct coresight_desc {
	159	enum coresight_dev_type type;
00b78e8b	160	union coresight_dev_subtype subtype;
a06ae860 PP	161	const struct coresight_ops *ops;
	162	struct coresight_platform_data *pdata;
	163	struct device *dev;
	164	const struct attribute_group **groups;
2ede79a6	165	const char *name;
6e736c60	166	struct csdev_access access;
a06ae860 PP	167	};
	168
	169	/**
	170	* struct coresight_connection - representation of a single connection
a06ae860	171	* @outport: a connection's output port number.
a06ae860	172	* @child_port: remote component's port number @output is connected to.
37ea1ffd	173	* @chid_fwnode: remote component's fwnode handle.
a06ae860 PP	174	* @child_dev: a @coresight_device representation of the component
a06ae860 PP	175	connected to @outport.
8a7365c2	176	* @link: Representation of the connection as a sysfs link.
a06ae860 PP	177	*/
	178	struct coresight_connection {
	179	int outport;
a06ae860	180	int child_port;
37ea1ffd	181	struct fwnode_handle *child_fwnode;
a06ae860	182	struct coresight_device *child_dev;
8a7365c2	183	struct coresight_sysfs_link *link;
a06ae860 PP	184	};
a06ae860 PP	185
80961525 ML	186	/**
	187	* struct coresight_sysfs_link - representation of a connection in sysfs.
	188	* @orig: Originating (master) coresight device for the link.
	189	* @orig_name: Name to use for the link orig->target.
	190	* @target: Target (slave) coresight device for the link.
	191	* @target_name: Name to use for the link target->orig.
	192	*/
	193	struct coresight_sysfs_link {
	194	struct coresight_device *orig;
	195	const char *orig_name;
	196	struct coresight_device *target;
	197	const char *target_name;
	198	};
	199
a06ae860 PP	200	/**
a06ae860 PP	201	* struct coresight_device - representation of a device as used by the framework
b77e3ed0	202	* @pdata: Platform data with device connections associated to this device.
a06ae860 PP	203	* @type: as defined by @coresight_dev_type.
	204	* @subtype: as defined by @coresight_dev_subtype.
	205	* @ops: generic operations for this component, as defined
6e736c60 SP	206	* by @coresight_ops.
6e736c60 SP	207	* @access: Device i/o access abstraction for this device.
a06ae860 PP	208	* @dev: The device entity associated to this component.
a06ae860 PP	209	* @refcnt: keep track of what is in use.
a06ae860 PP	210	* @orphan: true if the component has connections that haven't been linked.
	211	* @enable: 'true' if component is currently part of an active path.
	212	* @activated: 'true' only if a _sink_ has been activated. A sink can be
bb8e370b	213	* activated but not yet enabled. Enabling for a _sink_
d061cd73 ML	214	* happens when a source has been selected and a path is enabled
d061cd73 ML	215	* from source to that sink.
bb8e370b	216	* @ea: Device attribute for sink representation under PMU directory.
0336bdfd	217	* @def_sink: cached reference to default sink found for this device.
177af828 ML	218	* @ect_dev: Associated cross trigger device. Not part of the trace data
177af828 ML	219	* path or connections.
80961525 ML	220	* @nr_links: number of sysfs links created to other components from this
	221	* device. These will appear in the "connections" group.
	222	* @has_conns_grp: Have added a "connections" group for sysfs links.
a06ae860 PP	223	*/
a06ae860 PP	224	struct coresight_device {
b77e3ed0	225	struct coresight_platform_data *pdata;
a06ae860	226	enum coresight_dev_type type;
00b78e8b	227	union coresight_dev_subtype subtype;
a06ae860	228	const struct coresight_ops *ops;
6e736c60	229	struct csdev_access access;
a06ae860 PP	230	struct device dev;
a06ae860 PP	231	atomic_t *refcnt;
a06ae860 PP	232	bool orphan;
a06ae860 PP	233	bool enable; /* true only if configured as part of a path */
bb8e370b	234	/* sink specific fields */
a06ae860	235	bool activated; /* true only if a sink is part of a path */
bb8e370b	236	struct dev_ext_attribute *ea;
0336bdfd	237	struct coresight_device *def_sink;
177af828 ML	238	/* cross trigger handling */
177af828 ML	239	struct coresight_device *ect_dev;
80961525 ML	240	/* sysfs links between components */
	241	int nr_links;
	242	bool has_conns_grp;
f2ccc7b7	243	bool ect_enabled; /* true only if associated ect device is enabled */
a06ae860 PP	244	};
a06ae860 PP	245
0f5f9b6b SP	246	/*
	247	* coresight_dev_list - Mapping for devices to "name" index for device
	248	* names.
	249	*
	250	* @nr_idx: Number of entries already allocated.
	251	* @pfx: Prefix pattern for device name.
	252	* @fwnode_list: Array of fwnode_handles associated with each allocated
	253	* index, upto nr_idx entries.
	254	*/
	255	struct coresight_dev_list {
	256	int nr_idx;
	257	const char *pfx;
	258	struct fwnode_handle **fwnode_list;
	259	};
	260
	261	#define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \
	262	static struct coresight_dev_list (var) = { \
	263	.pfx = dev_pfx, \
	264	.nr_idx = 0, \
	265	.fwnode_list = NULL, \
	266	}
	267
a06ae860 PP	268	#define to_coresight_device(d) container_of(d, struct coresight_device, dev)
	269
	270	#define source_ops(csdev) csdev->ops->source_ops
	271	#define sink_ops(csdev) csdev->ops->sink_ops
	272	#define link_ops(csdev) csdev->ops->link_ops
8a091d84	273	#define helper_ops(csdev) csdev->ops->helper_ops
835d722b	274	#define ect_ops(csdev) csdev->ops->ect_ops
a06ae860	275
a06ae860 PP	276	/**
	277	* struct coresight_ops_sink - basic operations for a sink
	278	* Operations available for sinks
2997aa40 MP	279	* @enable: enables the sink.
	280	* @disable: disables the sink.
	281	* @alloc_buffer: initialises perf's ring buffer for trace collection.
	282	* @free_buffer: release memory allocated in @get_config.
2997aa40	283	* @update_buffer: update buffer pointers after a trace session.
a06ae860 PP	284	*/
a06ae860 PP	285	struct coresight_ops_sink {
3d6e8935	286	int (enable)(struct coresight_device csdev, u32 mode, void *data);
6c817a95	287	int (disable)(struct coresight_device csdev);
a0f08a6a MP	288	void (alloc_buffer)(struct coresight_device *csdev,
	289	struct perf_event event, void *pages,
	290	int nr_pages, bool overwrite);
2997aa40	291	void (free_buffer)(void config);
7ec786ad	292	unsigned long (update_buffer)(struct coresight_device csdev,
2997aa40 MP	293	struct perf_output_handle *handle,
2997aa40 MP	294	void *sink_config);
a06ae860 PP	295	};
	296
	297	/**
	298	* struct coresight_ops_link - basic operations for a link
	299	* Operations available for links.
	300	* @enable: enables flow between iport and oport.
	301	* @disable: disables flow between iport and oport.
	302	*/
	303	struct coresight_ops_link {
	304	int (enable)(struct coresight_device csdev, int iport, int oport);
	305	void (disable)(struct coresight_device csdev, int iport, int oport);
	306	};
	307
	308	/**
	309	* struct coresight_ops_source - basic operations for a source
	310	* Operations available for sources.
52210c87 MP	311	* @cpu_id: returns the value of the CPU number this component
52210c87 MP	312	* is associated to.
a06ae860	313	* @trace_id: returns the value of the component's trace ID as known
882d5e11	314	* to the HW.
1d27ff5a	315	* @enable: enables tracing for a source.
a06ae860 PP	316	* @disable: disables tracing for a source.
	317	*/
	318	struct coresight_ops_source {
52210c87	319	int (cpu_id)(struct coresight_device csdev);
a06ae860	320	int (trace_id)(struct coresight_device csdev);
882d5e11	321	int (enable)(struct coresight_device csdev,
68905d73 MP	322	struct perf_event *event, u32 mode);
	323	void (disable)(struct coresight_device csdev,
	324	struct perf_event *event);
a06ae860 PP	325	};
a06ae860 PP	326
8a091d84 SP	327	/**
	328	* struct coresight_ops_helper - Operations for a helper device.
	329	*
	330	* All operations could pass in a device specific data, which could
	331	* help the helper device to determine what to do.
	332	*
	333	* @enable : Enable the device
	334	* @disable : Disable the device
	335	*/
	336	struct coresight_ops_helper {
	337	int (enable)(struct coresight_device csdev, void *data);
	338	int (disable)(struct coresight_device csdev, void *data);
	339	};
	340
835d722b ML	341	/**
	342	* struct coresight_ops_ect - Ops for an embedded cross trigger device
	343	*
	344	* @enable : Enable the device
	345	* @disable : Disable the device
	346	*/
	347	struct coresight_ops_ect {
	348	int (enable)(struct coresight_device csdev);
	349	int (disable)(struct coresight_device csdev);
	350	};
	351
a06ae860 PP	352	struct coresight_ops {
	353	const struct coresight_ops_sink *sink_ops;
	354	const struct coresight_ops_link *link_ops;
	355	const struct coresight_ops_source *source_ops;
8a091d84	356	const struct coresight_ops_helper *helper_ops;
835d722b	357	const struct coresight_ops_ect *ect_ops;
a06ae860 PP	358	};
a06ae860 PP	359
b8127113	360	#if IS_ENABLED(CONFIG_CORESIGHT)
6e736c60 SP	361
	362	static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa,
	363	u32 offset)
	364	{
	365	if (likely(csa->io_mem))
	366	return readl_relaxed(csa->base + offset);
	367
	368	return csa->read(offset, true, false);
	369	}
	370
	371	static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset)
	372	{
	373	if (likely(csa->io_mem))
	374	return readl(csa->base + offset);
	375
	376	return csa->read(offset, false, false);
	377	}
	378
	379	static inline void csdev_access_relaxed_write32(struct csdev_access *csa,
	380	u32 val, u32 offset)
	381	{
	382	if (likely(csa->io_mem))
	383	writel_relaxed(val, csa->base + offset);
	384	else
	385	csa->write(val, offset, true, false);
	386	}
	387
	388	static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset)
	389	{
	390	if (likely(csa->io_mem))
	391	writel(val, csa->base + offset);
	392	else
	393	csa->write(val, offset, false, false);
	394	}
	395
	396	#ifdef CONFIG_64BIT
	397
	398	static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
	399	u32 offset)
	400	{
	401	if (likely(csa->io_mem))
	402	return readq_relaxed(csa->base + offset);
	403
	404	return csa->read(offset, true, true);
	405	}
	406
	407	static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
	408	{
	409	if (likely(csa->io_mem))
	410	return readq(csa->base + offset);
	411
	412	return csa->read(offset, false, true);
	413	}
	414
	415	static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
	416	u64 val, u32 offset)
	417	{
	418	if (likely(csa->io_mem))
	419	writeq_relaxed(val, csa->base + offset);
	420	else
	421	csa->write(val, offset, true, true);
	422	}
	423
	424	static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
425	{
426	if (likely(csa->io_mem))
427	writeq(val, csa->base + offset);
428	else
429	csa->write(val, offset, false, true);
430	}
431
432	#else /* !CONFIG_64BIT */
433
434	static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
435	u32 offset)
436	{
437	WARN_ON(1);
438	return 0;
439	}
440
441	static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
442	{
443	WARN_ON(1);
444	return 0;
445	}
446
447	static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
448	u64 val, u32 offset)
449	{
450	WARN_ON(1);
451	}
452
453	static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
454	{
455	WARN_ON(1);
456	}
457	#endif /* CONFIG_64BIT */
458
2cd87a7b AK	459	static inline bool coresight_is_percpu_source(struct coresight_device *csdev)
	460	{
	461	return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) &&
	462	(csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC);
	463	}
	464
	465	static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)
	466	{
	467	return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) &&
	468	(csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM);
	469	}
	470
a06ae860 PP	471	extern struct coresight_device *
	472	coresight_register(struct coresight_desc *desc);
	473	extern void coresight_unregister(struct coresight_device *csdev);
	474	extern int coresight_enable(struct coresight_device *csdev);
	475	extern void coresight_disable(struct coresight_device *csdev);
02005282	476	extern int coresight_timeout(struct csdev_access *csa, u32 offset,
a06ae860	477	int position, int value);
2478a6ae	478
8ce00296 SP	479	extern int coresight_claim_device(struct coresight_device *csdev);
8ce00296 SP	480	extern int coresight_claim_device_unlocked(struct coresight_device *csdev);
2478a6ae	481
8ce00296 SP	482	extern void coresight_disclaim_device(struct coresight_device *csdev);
8ce00296 SP	483	extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev);
0f5f9b6b SP	484	extern char coresight_alloc_device_name(struct coresight_dev_list devs,
0f5f9b6b SP	485	struct device *dev);
f188b5e7 AM	486
f188b5e7 AM	487	extern bool coresight_loses_context_with_cpu(struct device *dev);
6e736c60 SP	488
	489	u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset);
	490	u32 coresight_read32(struct coresight_device *csdev, u32 offset);
	491	void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset);
	492	void coresight_relaxed_write32(struct coresight_device *csdev,
	493	u32 val, u32 offset);
	494	u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset);
	495	u64 coresight_read64(struct coresight_device *csdev, u32 offset);
	496	void coresight_relaxed_write64(struct coresight_device *csdev,
	497	u64 val, u32 offset);
	498	void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset);
	499
a06ae860 PP	500	#else
	501	static inline struct coresight_device *
	502	coresight_register(struct coresight_desc *desc) { return NULL; }
	503	static inline void coresight_unregister(struct coresight_device *csdev) {}
	504	static inline int
	505	coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
	506	static inline void coresight_disable(struct coresight_device *csdev) {}
02005282 SP	507
	508	static inline int coresight_timeout(struct csdev_access *csa, u32 offset,
	509	int position, int value)
	510	{
	511	return 1;
	512	}
	513
8ce00296	514	static inline int coresight_claim_device_unlocked(struct coresight_device *csdev)
2478a6ae SP	515	{
	516	return -EINVAL;
	517	}
	518
8ce00296	519	static inline int coresight_claim_device(struct coresight_device *csdev)
2478a6ae SP	520	{
	521	return -EINVAL;
	522	}
	523
8ce00296 SP	524	static inline void coresight_disclaim_device(struct coresight_device *csdev) {}
8ce00296 SP	525	static inline void coresight_disclaim_device_unlocked(struct coresight_device *csdev) {}
2478a6ae	526
f188b5e7 AM	527	static inline bool coresight_loses_context_with_cpu(struct device *dev)
	528	{
	529	return false;
	530	}
6e736c60 SP	531
	532	static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset)
	533	{
	534	WARN_ON_ONCE(1);
	535	return 0;
	536	}
	537
	538	static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset)
	539	{
	540	WARN_ON_ONCE(1);
	541	return 0;
	542	}
	543
	544	static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset)
	545	{
	546	}
	547
	548	static inline void coresight_relaxed_write32(struct coresight_device *csdev,
	549	u32 val, u32 offset)
	550	{
	551	}
	552
	553	static inline u64 coresight_relaxed_read64(struct coresight_device *csdev,
	554	u32 offset)
	555	{
	556	WARN_ON_ONCE(1);
	557	return 0;
	558	}
	559
	560	static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset)
	561	{
	562	WARN_ON_ONCE(1);
	563	return 0;
	564	}
	565
	566	static inline void coresight_relaxed_write64(struct coresight_device *csdev,
	567	u64 val, u32 offset)
	568	{
	569	}
	570
	571	static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset)
	572	{
	573	}
	574
	575	#endif /* IS_ENABLED(CONFIG_CORESIGHT) */
c61c4b5d	576
91824db2	577	extern int coresight_get_cpu(struct device *dev);
a06ae860	578
f03631da SP	579	struct coresight_platform_data coresight_get_platform_data(struct device dev);
f03631da SP	580
6e736c60	581	#endif /* _LINUX_COREISGHT_H */