[mirror_ubuntu-jammy-kernel.git] / include / linux / coresight.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2012, The Linux Foundation. All rights reserved.
 */

#ifndef _LINUX_CORESIGHT_H
#define _LINUX_CORESIGHT_H

#include <linux/device.h>
#include <linux/perf_event.h>
#include <linux/sched.h>

/* Peripheral id registers (0xFD0-0xFEC) */
#define CORESIGHT_PERIPHIDR4	0xfd0
#define CORESIGHT_PERIPHIDR5	0xfd4
#define CORESIGHT_PERIPHIDR6	0xfd8
#define CORESIGHT_PERIPHIDR7	0xfdC
#define CORESIGHT_PERIPHIDR0	0xfe0
#define CORESIGHT_PERIPHIDR1	0xfe4
#define CORESIGHT_PERIPHIDR2	0xfe8
#define CORESIGHT_PERIPHIDR3	0xfeC
/* Component id registers (0xFF0-0xFFC) */
#define CORESIGHT_COMPIDR0	0xff0
#define CORESIGHT_COMPIDR1	0xff4
#define CORESIGHT_COMPIDR2	0xff8
#define CORESIGHT_COMPIDR3	0xffC

#define ETM_ARCH_V3_3		0x23
#define ETM_ARCH_V3_5		0x25
#define PFT_ARCH_V1_0		0x30
#define PFT_ARCH_V1_1		0x31

#define CORESIGHT_UNLOCK	0xc5acce55

extern struct bus_type coresight_bustype;

enum coresight_dev_type {
	CORESIGHT_DEV_TYPE_NONE,
	CORESIGHT_DEV_TYPE_SINK,
	CORESIGHT_DEV_TYPE_LINK,
	CORESIGHT_DEV_TYPE_LINKSINK,
	CORESIGHT_DEV_TYPE_SOURCE,
	CORESIGHT_DEV_TYPE_HELPER,
};

enum coresight_dev_subtype_sink {
	CORESIGHT_DEV_SUBTYPE_SINK_NONE,
	CORESIGHT_DEV_SUBTYPE_SINK_PORT,
	CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
};

enum coresight_dev_subtype_link {
	CORESIGHT_DEV_SUBTYPE_LINK_NONE,
	CORESIGHT_DEV_SUBTYPE_LINK_MERG,
	CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
	CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
};

enum coresight_dev_subtype_source {
	CORESIGHT_DEV_SUBTYPE_SOURCE_NONE,
	CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
	CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
	CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
};

enum coresight_dev_subtype_helper {
	CORESIGHT_DEV_SUBTYPE_HELPER_NONE,
	CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
};

/**
 * union coresight_dev_subtype - further characterisation of a type
 * @sink_subtype:	type of sink this component is, as defined
 *			by @coresight_dev_subtype_sink.
 * @link_subtype:	type of link this component is, as defined
 *			by @coresight_dev_subtype_link.
 * @source_subtype:	type of source this component is, as defined
 *			by @coresight_dev_subtype_source.
 * @helper_subtype:	type of helper this component is, as defined
 *			by @coresight_dev_subtype_helper.
 */
union coresight_dev_subtype {
	/* We have some devices which acts as LINK and SINK */
	struct {
		enum coresight_dev_subtype_sink sink_subtype;
		enum coresight_dev_subtype_link link_subtype;
	};
	enum coresight_dev_subtype_source source_subtype;
	enum coresight_dev_subtype_helper helper_subtype;
};

/**
 * struct coresight_platform_data - data harvested from the DT specification
 * @nr_inport:	number of input ports for this component.
 * @nr_outport:	number of output ports for this component.
 * @conns:	Array of nr_outport connections from this component
 */
struct coresight_platform_data {
	int nr_inport;
	int nr_outport;
	struct coresight_connection *conns;
};

/**
 * struct coresight_desc - description of a component required from drivers
 * @type:	as defined by @coresight_dev_type.
 * @subtype:	as defined by @coresight_dev_subtype.
 * @ops:	generic operations for this component, as defined
 *		by @coresight_ops.
 * @pdata:	platform data collected from DT.
 * @dev:	The device entity associated to this component.
 * @groups:	operations specific to this component. These will end up
 *		in the component's sysfs sub-directory.
 * @name:	name for the coresight device, also shown under sysfs.
 */
struct coresight_desc {
	enum coresight_dev_type type;
	union coresight_dev_subtype subtype;
	const struct coresight_ops *ops;
	struct coresight_platform_data *pdata;
	struct device *dev;
	const struct attribute_group **groups;
	const char *name;
};

/**
 * struct coresight_connection - representation of a single connection
 * @outport:	a connection's output port number.
 * @child_port:	remote component's port number @output is connected to.
 * @chid_fwnode: remote component's fwnode handle.
 * @child_dev:	a @coresight_device representation of the component
		connected to @outport.
 */
struct coresight_connection {
	int outport;
	int child_port;
	struct fwnode_handle *child_fwnode;
	struct coresight_device *child_dev;
};

/**
 * struct coresight_device - representation of a device as used by the framework
 * @pdata:	Platform data with device connections associated to this device.
 * @type:	as defined by @coresight_dev_type.
 * @subtype:	as defined by @coresight_dev_subtype.
 * @ops:	generic operations for this component, as defined
		by @coresight_ops.
 * @dev:	The device entity associated to this component.
 * @refcnt:	keep track of what is in use.
 * @orphan:	true if the component has connections that haven't been linked.
 * @enable:	'true' if component is currently part of an active path.
 * @activated:	'true' only if a _sink_ has been activated.  A sink can be
 *		activated but not yet enabled.  Enabling for a _sink_
 *		appens when a source has been selected for that it.
 * @ea:		Device attribute for sink representation under PMU directory.
 */
struct coresight_device {
	struct coresight_platform_data *pdata;
	enum coresight_dev_type type;
	union coresight_dev_subtype subtype;
	const struct coresight_ops *ops;
	struct device dev;
	atomic_t *refcnt;
	bool orphan;
	bool enable;	/* true only if configured as part of a path */
	/* sink specific fields */
	bool activated;	/* true only if a sink is part of a path */
	struct dev_ext_attribute *ea;
};

/*
 * coresight_dev_list - Mapping for devices to "name" index for device
 * names.
 *
 * @nr_idx:		Number of entries already allocated.
 * @pfx:		Prefix pattern for device name.
 * @fwnode_list:	Array of fwnode_handles associated with each allocated
 *			index, upto nr_idx entries.
 */
struct coresight_dev_list {
	int			nr_idx;
	const char		*pfx;
	struct fwnode_handle	**fwnode_list;
};

#define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx)				\
static struct coresight_dev_list (var) = {				\
						.pfx = dev_pfx,		\
						.nr_idx = 0,		\
						.fwnode_list = NULL,	\
}

#define to_coresight_device(d) container_of(d, struct coresight_device, dev)

#define source_ops(csdev)	csdev->ops->source_ops
#define sink_ops(csdev)		csdev->ops->sink_ops
#define link_ops(csdev)		csdev->ops->link_ops
#define helper_ops(csdev)	csdev->ops->helper_ops

/**
 * struct coresight_ops_sink - basic operations for a sink
 * Operations available for sinks
 * @enable:		enables the sink.
 * @disable:		disables the sink.
 * @alloc_buffer:	initialises perf's ring buffer for trace collection.
 * @free_buffer:	release memory allocated in @get_config.
 * @update_buffer:	update buffer pointers after a trace session.
 */
struct coresight_ops_sink {
	int (*enable)(struct coresight_device *csdev, u32 mode, void *data);
	int (*disable)(struct coresight_device *csdev);
	void *(*alloc_buffer)(struct coresight_device *csdev,
			      struct perf_event *event, void **pages,
			      int nr_pages, bool overwrite);
	void (*free_buffer)(void *config);
	unsigned long (*update_buffer)(struct coresight_device *csdev,
			      struct perf_output_handle *handle,
			      void *sink_config);
};

/**
 * struct coresight_ops_link - basic operations for a link
 * Operations available for links.
 * @enable:	enables flow between iport and oport.
 * @disable:	disables flow between iport and oport.
 */
struct coresight_ops_link {
	int (*enable)(struct coresight_device *csdev, int iport, int oport);
	void (*disable)(struct coresight_device *csdev, int iport, int oport);
};

/**
 * struct coresight_ops_source - basic operations for a source
 * Operations available for sources.
 * @cpu_id:	returns the value of the CPU number this component
 *		is associated to.
 * @trace_id:	returns the value of the component's trace ID as known
 *		to the HW.
 * @enable:	enables tracing for a source.
 * @disable:	disables tracing for a source.
 */
struct coresight_ops_source {
	int (*cpu_id)(struct coresight_device *csdev);
	int (*trace_id)(struct coresight_device *csdev);
	int (*enable)(struct coresight_device *csdev,
		      struct perf_event *event,  u32 mode);
	void (*disable)(struct coresight_device *csdev,
			struct perf_event *event);
};

/**
 * struct coresight_ops_helper - Operations for a helper device.
 *
 * All operations could pass in a device specific data, which could
 * help the helper device to determine what to do.
 *
 * @enable	: Enable the device
 * @disable	: Disable the device
 */
struct coresight_ops_helper {
	int (*enable)(struct coresight_device *csdev, void *data);
	int (*disable)(struct coresight_device *csdev, void *data);
};

struct coresight_ops {
	const struct coresight_ops_sink *sink_ops;
	const struct coresight_ops_link *link_ops;
	const struct coresight_ops_source *source_ops;
	const struct coresight_ops_helper *helper_ops;
};

#ifdef CONFIG_CORESIGHT
extern struct coresight_device *
coresight_register(struct coresight_desc *desc);
extern void coresight_unregister(struct coresight_device *csdev);
extern int coresight_enable(struct coresight_device *csdev);
extern void coresight_disable(struct coresight_device *csdev);
extern int coresight_timeout(void __iomem *addr, u32 offset,
			     int position, int value);

extern int coresight_claim_device(void __iomem *base);
extern int coresight_claim_device_unlocked(void __iomem *base);

extern void coresight_disclaim_device(void __iomem *base);
extern void coresight_disclaim_device_unlocked(void __iomem *base);
extern char *coresight_alloc_device_name(struct coresight_dev_list *devs,
					 struct device *dev);
#else
static inline struct coresight_device *
coresight_register(struct coresight_desc *desc) { return NULL; }
static inline void coresight_unregister(struct coresight_device *csdev) {}
static inline int
coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
static inline void coresight_disable(struct coresight_device *csdev) {}
static inline int coresight_timeout(void __iomem *addr, u32 offset,
				     int position, int value) { return 1; }
static inline int coresight_claim_device_unlocked(void __iomem *base)
{
	return -EINVAL;
}

static inline int coresight_claim_device(void __iomem *base)
{
	return -EINVAL;
}

static inline void coresight_disclaim_device(void __iomem *base) {}
static inline void coresight_disclaim_device_unlocked(void __iomem *base) {}

#endif

extern int coresight_get_cpu(struct device *dev);

struct coresight_platform_data *coresight_get_platform_data(struct device *dev);

#endif
Commit	Line	Data
ad0dfdfd MP	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Copyright (c) 2012, The Linux Foundation. All rights reserved.
a06ae860 PP	4	*/
	5
	6	#ifndef _LINUX_CORESIGHT_H
	7	#define _LINUX_CORESIGHT_H
	8
	9	#include <linux/device.h>
882d5e11	10	#include <linux/perf_event.h>
ff63ec13	11	#include <linux/sched.h>
a06ae860 PP	12
	13	/* Peripheral id registers (0xFD0-0xFEC) */
	14	#define CORESIGHT_PERIPHIDR4 0xfd0
	15	#define CORESIGHT_PERIPHIDR5 0xfd4
	16	#define CORESIGHT_PERIPHIDR6 0xfd8
	17	#define CORESIGHT_PERIPHIDR7 0xfdC
	18	#define CORESIGHT_PERIPHIDR0 0xfe0
	19	#define CORESIGHT_PERIPHIDR1 0xfe4
	20	#define CORESIGHT_PERIPHIDR2 0xfe8
	21	#define CORESIGHT_PERIPHIDR3 0xfeC
	22	/* Component id registers (0xFF0-0xFFC) */
	23	#define CORESIGHT_COMPIDR0 0xff0
	24	#define CORESIGHT_COMPIDR1 0xff4
	25	#define CORESIGHT_COMPIDR2 0xff8
	26	#define CORESIGHT_COMPIDR3 0xffC
	27
	28	#define ETM_ARCH_V3_3 0x23
	29	#define ETM_ARCH_V3_5 0x25
	30	#define PFT_ARCH_V1_0 0x30
	31	#define PFT_ARCH_V1_1 0x31
	32
	33	#define CORESIGHT_UNLOCK 0xc5acce55
	34
	35	extern struct bus_type coresight_bustype;
	36
	37	enum coresight_dev_type {
	38	CORESIGHT_DEV_TYPE_NONE,
	39	CORESIGHT_DEV_TYPE_SINK,
	40	CORESIGHT_DEV_TYPE_LINK,
	41	CORESIGHT_DEV_TYPE_LINKSINK,
	42	CORESIGHT_DEV_TYPE_SOURCE,
8a091d84	43	CORESIGHT_DEV_TYPE_HELPER,
a06ae860 PP	44	};
	45
	46	enum coresight_dev_subtype_sink {
	47	CORESIGHT_DEV_SUBTYPE_SINK_NONE,
	48	CORESIGHT_DEV_SUBTYPE_SINK_PORT,
	49	CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
	50	};
	51
	52	enum coresight_dev_subtype_link {
	53	CORESIGHT_DEV_SUBTYPE_LINK_NONE,
	54	CORESIGHT_DEV_SUBTYPE_LINK_MERG,
	55	CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
	56	CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
	57	};
	58
	59	enum coresight_dev_subtype_source {
	60	CORESIGHT_DEV_SUBTYPE_SOURCE_NONE,
	61	CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
	62	CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
	63	CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
	64	};
	65
8a091d84 SP	66	enum coresight_dev_subtype_helper {
8a091d84 SP	67	CORESIGHT_DEV_SUBTYPE_HELPER_NONE,
fcacb5c1	68	CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
8a091d84 SP	69	};
8a091d84 SP	70
a06ae860	71	/**
00b78e8b	72	* union coresight_dev_subtype - further characterisation of a type
a06ae860	73	* @sink_subtype: type of sink this component is, as defined
00b78e8b	74	* by @coresight_dev_subtype_sink.
a06ae860	75	* @link_subtype: type of link this component is, as defined
00b78e8b	76	* by @coresight_dev_subtype_link.
a06ae860	77	* @source_subtype: type of source this component is, as defined
00b78e8b	78	* by @coresight_dev_subtype_source.
8a091d84 SP	79	* @helper_subtype: type of helper this component is, as defined
8a091d84 SP	80	* by @coresight_dev_subtype_helper.
a06ae860	81	*/
00b78e8b SP	82	union coresight_dev_subtype {
	83	/* We have some devices which acts as LINK and SINK */
	84	struct {
	85	enum coresight_dev_subtype_sink sink_subtype;
	86	enum coresight_dev_subtype_link link_subtype;
	87	};
a06ae860	88	enum coresight_dev_subtype_source source_subtype;
8a091d84	89	enum coresight_dev_subtype_helper helper_subtype;
a06ae860 PP	90	};
	91
	92	/**
	93	* struct coresight_platform_data - data harvested from the DT specification
a06ae860	94	* @nr_inport: number of input ports for this component.
a06ae860	95	* @nr_outport: number of output ports for this component.
c2c72941	96	* @conns: Array of nr_outport connections from this component
a06ae860 PP	97	*/
a06ae860 PP	98	struct coresight_platform_data {
a06ae860	99	int nr_inport;
a06ae860	100	int nr_outport;
c2c72941	101	struct coresight_connection *conns;
a06ae860 PP	102	};
	103
	104	/**
	105	* struct coresight_desc - description of a component required from drivers
	106	* @type: as defined by @coresight_dev_type.
	107	* @subtype: as defined by @coresight_dev_subtype.
	108	* @ops: generic operations for this component, as defined
2ede79a6	109	* by @coresight_ops.
a06ae860 PP	110	* @pdata: platform data collected from DT.
a06ae860 PP	111	* @dev: The device entity associated to this component.
8ee885a9	112	* @groups: operations specific to this component. These will end up
2ede79a6 SP	113	* in the component's sysfs sub-directory.
2ede79a6 SP	114	* @name: name for the coresight device, also shown under sysfs.
a06ae860 PP	115	*/
	116	struct coresight_desc {
	117	enum coresight_dev_type type;
00b78e8b	118	union coresight_dev_subtype subtype;
a06ae860 PP	119	const struct coresight_ops *ops;
	120	struct coresight_platform_data *pdata;
	121	struct device *dev;
	122	const struct attribute_group **groups;
2ede79a6	123	const char *name;
a06ae860 PP	124	};
	125
	126	/**
	127	* struct coresight_connection - representation of a single connection
a06ae860	128	* @outport: a connection's output port number.
a06ae860	129	* @child_port: remote component's port number @output is connected to.
37ea1ffd	130	* @chid_fwnode: remote component's fwnode handle.
a06ae860 PP	131	* @child_dev: a @coresight_device representation of the component
	132	connected to @outport.
	133	*/
	134	struct coresight_connection {
	135	int outport;
a06ae860	136	int child_port;
37ea1ffd	137	struct fwnode_handle *child_fwnode;
a06ae860 PP	138	struct coresight_device *child_dev;
	139	};
	140
	141	/**
	142	* struct coresight_device - representation of a device as used by the framework
b77e3ed0	143	* @pdata: Platform data with device connections associated to this device.
a06ae860 PP	144	* @type: as defined by @coresight_dev_type.
	145	* @subtype: as defined by @coresight_dev_subtype.
	146	* @ops: generic operations for this component, as defined
	147	by @coresight_ops.
	148	* @dev: The device entity associated to this component.
	149	* @refcnt: keep track of what is in use.
a06ae860 PP	150	* @orphan: true if the component has connections that haven't been linked.
	151	* @enable: 'true' if component is currently part of an active path.
	152	* @activated: 'true' only if a _sink_ has been activated. A sink can be
bb8e370b MP	153	* activated but not yet enabled. Enabling for a _sink_
	154	* appens when a source has been selected for that it.
	155	* @ea: Device attribute for sink representation under PMU directory.
a06ae860 PP	156	*/
a06ae860 PP	157	struct coresight_device {
b77e3ed0	158	struct coresight_platform_data *pdata;
a06ae860	159	enum coresight_dev_type type;
00b78e8b	160	union coresight_dev_subtype subtype;
a06ae860 PP	161	const struct coresight_ops *ops;
	162	struct device dev;
	163	atomic_t *refcnt;
a06ae860 PP	164	bool orphan;
a06ae860 PP	165	bool enable; /* true only if configured as part of a path */
bb8e370b	166	/* sink specific fields */
a06ae860	167	bool activated; /* true only if a sink is part of a path */
bb8e370b	168	struct dev_ext_attribute *ea;
a06ae860 PP	169	};
a06ae860 PP	170
0f5f9b6b SP	171	/*
	172	* coresight_dev_list - Mapping for devices to "name" index for device
	173	* names.
	174	*
	175	* @nr_idx: Number of entries already allocated.
	176	* @pfx: Prefix pattern for device name.
	177	* @fwnode_list: Array of fwnode_handles associated with each allocated
	178	* index, upto nr_idx entries.
	179	*/
	180	struct coresight_dev_list {
	181	int nr_idx;
	182	const char *pfx;
	183	struct fwnode_handle **fwnode_list;
	184	};
	185
	186	#define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \
	187	static struct coresight_dev_list (var) = { \
	188	.pfx = dev_pfx, \
	189	.nr_idx = 0, \
	190	.fwnode_list = NULL, \
	191	}
	192
a06ae860 PP	193	#define to_coresight_device(d) container_of(d, struct coresight_device, dev)
	194
	195	#define source_ops(csdev) csdev->ops->source_ops
	196	#define sink_ops(csdev) csdev->ops->sink_ops
	197	#define link_ops(csdev) csdev->ops->link_ops
8a091d84	198	#define helper_ops(csdev) csdev->ops->helper_ops
a06ae860	199
a06ae860 PP	200	/**
	201	* struct coresight_ops_sink - basic operations for a sink
	202	* Operations available for sinks
2997aa40 MP	203	* @enable: enables the sink.
	204	* @disable: disables the sink.
	205	* @alloc_buffer: initialises perf's ring buffer for trace collection.
	206	* @free_buffer: release memory allocated in @get_config.
2997aa40	207	* @update_buffer: update buffer pointers after a trace session.
a06ae860 PP	208	*/
a06ae860 PP	209	struct coresight_ops_sink {
3d6e8935	210	int (enable)(struct coresight_device csdev, u32 mode, void *data);
6c817a95	211	int (disable)(struct coresight_device csdev);
a0f08a6a MP	212	void (alloc_buffer)(struct coresight_device *csdev,
	213	struct perf_event event, void *pages,
	214	int nr_pages, bool overwrite);
2997aa40	215	void (free_buffer)(void config);
7ec786ad	216	unsigned long (update_buffer)(struct coresight_device csdev,
2997aa40 MP	217	struct perf_output_handle *handle,
2997aa40 MP	218	void *sink_config);
a06ae860 PP	219	};
	220
	221	/**
	222	* struct coresight_ops_link - basic operations for a link
	223	* Operations available for links.
	224	* @enable: enables flow between iport and oport.
	225	* @disable: disables flow between iport and oport.
	226	*/
	227	struct coresight_ops_link {
	228	int (enable)(struct coresight_device csdev, int iport, int oport);
	229	void (disable)(struct coresight_device csdev, int iport, int oport);
	230	};
	231
	232	/**
	233	* struct coresight_ops_source - basic operations for a source
	234	* Operations available for sources.
52210c87 MP	235	* @cpu_id: returns the value of the CPU number this component
52210c87 MP	236	* is associated to.
a06ae860	237	* @trace_id: returns the value of the component's trace ID as known
882d5e11	238	* to the HW.
1d27ff5a	239	* @enable: enables tracing for a source.
a06ae860 PP	240	* @disable: disables tracing for a source.
	241	*/
	242	struct coresight_ops_source {
52210c87	243	int (cpu_id)(struct coresight_device csdev);
a06ae860	244	int (trace_id)(struct coresight_device csdev);
882d5e11	245	int (enable)(struct coresight_device csdev,
68905d73 MP	246	struct perf_event *event, u32 mode);
	247	void (disable)(struct coresight_device csdev,
	248	struct perf_event *event);
a06ae860 PP	249	};
a06ae860 PP	250
8a091d84 SP	251	/**
	252	* struct coresight_ops_helper - Operations for a helper device.
	253	*
	254	* All operations could pass in a device specific data, which could
	255	* help the helper device to determine what to do.
	256	*
	257	* @enable : Enable the device
	258	* @disable : Disable the device
	259	*/
	260	struct coresight_ops_helper {
	261	int (enable)(struct coresight_device csdev, void *data);
	262	int (disable)(struct coresight_device csdev, void *data);
	263	};
	264
a06ae860 PP	265	struct coresight_ops {
	266	const struct coresight_ops_sink *sink_ops;
	267	const struct coresight_ops_link *link_ops;
	268	const struct coresight_ops_source *source_ops;
8a091d84	269	const struct coresight_ops_helper *helper_ops;
a06ae860 PP	270	};
	271
	272	#ifdef CONFIG_CORESIGHT
	273	extern struct coresight_device *
	274	coresight_register(struct coresight_desc *desc);
	275	extern void coresight_unregister(struct coresight_device *csdev);
	276	extern int coresight_enable(struct coresight_device *csdev);
	277	extern void coresight_disable(struct coresight_device *csdev);
a06ae860 PP	278	extern int coresight_timeout(void __iomem *addr, u32 offset,
a06ae860 PP	279	int position, int value);
2478a6ae SP	280
	281	extern int coresight_claim_device(void __iomem *base);
	282	extern int coresight_claim_device_unlocked(void __iomem *base);
	283
	284	extern void coresight_disclaim_device(void __iomem *base);
	285	extern void coresight_disclaim_device_unlocked(void __iomem *base);
0f5f9b6b SP	286	extern char coresight_alloc_device_name(struct coresight_dev_list devs,
0f5f9b6b SP	287	struct device *dev);
a06ae860 PP	288	#else
	289	static inline struct coresight_device *
	290	coresight_register(struct coresight_desc *desc) { return NULL; }
	291	static inline void coresight_unregister(struct coresight_device *csdev) {}
	292	static inline int
	293	coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
	294	static inline void coresight_disable(struct coresight_device *csdev) {}
a06ae860 PP	295	static inline int coresight_timeout(void __iomem *addr, u32 offset,
a06ae860 PP	296	int position, int value) { return 1; }
2478a6ae SP	297	static inline int coresight_claim_device_unlocked(void __iomem *base)
	298	{
	299	return -EINVAL;
	300	}
	301
	302	static inline int coresight_claim_device(void __iomem *base)
	303	{
	304	return -EINVAL;
	305	}
	306
	307	static inline void coresight_disclaim_device(void __iomem *base) {}
	308	static inline void coresight_disclaim_device_unlocked(void __iomem *base) {}
	309
c61c4b5d MP	310	#endif
c61c4b5d MP	311
91824db2	312	extern int coresight_get_cpu(struct device *dev);
a06ae860	313
f03631da SP	314	struct coresight_platform_data coresight_get_platform_data(struct device dev);
f03631da SP	315
a06ae860	316	#endif