[mirror_ubuntu-hirsute-kernel.git] / include / linux / cper.h

/*
 * UEFI Common Platform Error Record
 *
 * Copyright (C) 2010, Intel Corp.
 *	Author: Huang Ying <ying.huang@intel.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version
 * 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#ifndef LINUX_CPER_H
#define LINUX_CPER_H

#include <linux/uuid.h>
#include <linux/trace_seq.h>

/* CPER record signature and the size */
#define CPER_SIG_RECORD				"CPER"
#define CPER_SIG_SIZE				4
/* Used in signature_end field in struct cper_record_header */
#define CPER_SIG_END				0xffffffff

/*
 * CPER record header revision, used in revision field in struct
 * cper_record_header
 */
#define CPER_RECORD_REV				0x0100

/*
 * CPER record length contains the CPER fields which are relevant for further
 * handling of a memory error in userspace (we don't carry all the fields
 * defined in the UEFI spec because some of them don't make any sense.)
 * Currently, a length of 256 should be more than enough.
 */
#define CPER_REC_LEN					256
/*
 * Severity definition for error_severity in struct cper_record_header
 * and section_severity in struct cper_section_descriptor
 */
enum {
	CPER_SEV_RECOVERABLE,
	CPER_SEV_FATAL,
	CPER_SEV_CORRECTED,
	CPER_SEV_INFORMATIONAL,
};

/*
 * Validation bits definition for validation_bits in struct
 * cper_record_header. If set, corresponding fields in struct
 * cper_record_header contain valid information.
 */
#define CPER_VALID_PLATFORM_ID			0x0001
#define CPER_VALID_TIMESTAMP			0x0002
#define CPER_VALID_PARTITION_ID			0x0004

/*
 * Notification type used to generate error record, used in
 * notification_type in struct cper_record_header.  These UUIDs are defined
 * in the UEFI spec v2.7, sec N.2.1.
 */

/* Corrected Machine Check */
#define CPER_NOTIFY_CMC							\
	GUID_INIT(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4,	\
		  0xEB, 0xD4, 0xF8, 0x90)
/* Corrected Platform Error */
#define CPER_NOTIFY_CPE							\
	GUID_INIT(0x4E292F96, 0xD843, 0x4a55, 0xA8, 0xC2, 0xD4, 0x81,	\
		  0xF2, 0x7E, 0xBE, 0xEE)
/* Machine Check Exception */
#define CPER_NOTIFY_MCE							\
	GUID_INIT(0xE8F56FFE, 0x919C, 0x4cc5, 0xBA, 0x88, 0x65, 0xAB,	\
		  0xE1, 0x49, 0x13, 0xBB)
/* PCI Express Error */
#define CPER_NOTIFY_PCIE						\
	GUID_INIT(0xCF93C01F, 0x1A16, 0x4dfc, 0xB8, 0xBC, 0x9C, 0x4D,	\
		  0xAF, 0x67, 0xC1, 0x04)
/* INIT Record (for IPF) */
#define CPER_NOTIFY_INIT						\
	GUID_INIT(0xCC5263E8, 0x9308, 0x454a, 0x89, 0xD0, 0x34, 0x0B,	\
		  0xD3, 0x9B, 0xC9, 0x8E)
/* Non-Maskable Interrupt */
#define CPER_NOTIFY_NMI							\
	GUID_INIT(0x5BAD89FF, 0xB7E6, 0x42c9, 0x81, 0x4A, 0xCF, 0x24,	\
		  0x85, 0xD6, 0xE9, 0x8A)
/* BOOT Error Record */
#define CPER_NOTIFY_BOOT						\
	GUID_INIT(0x3D61A466, 0xAB40, 0x409a, 0xA6, 0x98, 0xF3, 0x62,	\
		  0xD4, 0x64, 0xB3, 0x8F)
/* DMA Remapping Error */
#define CPER_NOTIFY_DMAR						\
	GUID_INIT(0x667DD791, 0xC6B3, 0x4c27, 0x8A, 0x6B, 0x0F, 0x8E,	\
		  0x72, 0x2D, 0xEB, 0x41)

/*
 * Flags bits definitions for flags in struct cper_record_header
 * If set, the error has been recovered
 */
#define CPER_HW_ERROR_FLAGS_RECOVERED		0x1
/* If set, the error is for previous boot */
#define CPER_HW_ERROR_FLAGS_PREVERR		0x2
/* If set, the error is injected for testing */
#define CPER_HW_ERROR_FLAGS_SIMULATED		0x4

/*
 * CPER section header revision, used in revision field in struct
 * cper_section_descriptor
 */
#define CPER_SEC_REV				0x0100

/*
 * Validation bits definition for validation_bits in struct
 * cper_section_descriptor. If set, corresponding fields in struct
 * cper_section_descriptor contain valid information.
 */
#define CPER_SEC_VALID_FRU_ID			0x1
#define CPER_SEC_VALID_FRU_TEXT			0x2

/*
 * Flags bits definitions for flags in struct cper_section_descriptor
 *
 * If set, the section is associated with the error condition
 * directly, and should be focused on
 */
#define CPER_SEC_PRIMARY			0x0001
/*
 * If set, the error was not contained within the processor or memory
 * hierarchy and the error may have propagated to persistent storage
 * or network
 */
#define CPER_SEC_CONTAINMENT_WARNING		0x0002
/* If set, the component must be re-initialized or re-enabled prior to use */
#define CPER_SEC_RESET				0x0004
/* If set, Linux may choose to discontinue use of the resource */
#define CPER_SEC_ERROR_THRESHOLD_EXCEEDED	0x0008
/*
 * If set, resource could not be queried for error information due to
 * conflicts with other system software or resources. Some fields of
 * the section will be invalid
 */
#define CPER_SEC_RESOURCE_NOT_ACCESSIBLE	0x0010
/*
 * If set, action has been taken to ensure error containment (such as
 * poisoning data), but the error has not been fully corrected and the
 * data has not been consumed. Linux may choose to take further
 * corrective action before the data is consumed
 */
#define CPER_SEC_LATENT_ERROR			0x0020

/*
 * Section type definitions, used in section_type field in struct
 * cper_section_descriptor.  These UUIDs are defined in the UEFI spec
 * v2.7, sec N.2.2.
 */

/* Processor Generic */
#define CPER_SEC_PROC_GENERIC						\
	GUID_INIT(0x9876CCAD, 0x47B4, 0x4bdb, 0xB6, 0x5E, 0x16, 0xF1,	\
		  0x93, 0xC4, 0xF3, 0xDB)
/* Processor Specific: X86/X86_64 */
#define CPER_SEC_PROC_IA						\
	GUID_INIT(0xDC3EA0B0, 0xA144, 0x4797, 0xB9, 0x5B, 0x53, 0xFA,	\
		  0x24, 0x2B, 0x6E, 0x1D)
/* Processor Specific: IA64 */
#define CPER_SEC_PROC_IPF						\
	GUID_INIT(0xE429FAF1, 0x3CB7, 0x11D4, 0x0B, 0xCA, 0x07, 0x00,	\
		  0x80, 0xC7, 0x3C, 0x88, 0x81)
/* Processor Specific: ARM */
#define CPER_SEC_PROC_ARM						\
	GUID_INIT(0xE19E3D16, 0xBC11, 0x11E4, 0x9C, 0xAA, 0xC2, 0x05,	\
		  0x1D, 0x5D, 0x46, 0xB0)
/* Platform Memory */
#define CPER_SEC_PLATFORM_MEM						\
	GUID_INIT(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83,	\
		  0xED, 0x7C, 0x83, 0xB1)
#define CPER_SEC_PCIE							\
	GUID_INIT(0xD995E954, 0xBBC1, 0x430F, 0xAD, 0x91, 0xB4, 0x4D,	\
		  0xCB, 0x3C, 0x6F, 0x35)
/* Firmware Error Record Reference */
#define CPER_SEC_FW_ERR_REC_REF						\
	GUID_INIT(0x81212A96, 0x09ED, 0x4996, 0x94, 0x71, 0x8D, 0x72,	\
		  0x9C, 0x8E, 0x69, 0xED)
/* PCI/PCI-X Bus */
#define CPER_SEC_PCI_X_BUS						\
	GUID_INIT(0xC5753963, 0x3B84, 0x4095, 0xBF, 0x78, 0xED, 0xDA,	\
		  0xD3, 0xF9, 0xC9, 0xDD)
/* PCI Component/Device */
#define CPER_SEC_PCI_DEV						\
	GUID_INIT(0xEB5E4685, 0xCA66, 0x4769, 0xB6, 0xA2, 0x26, 0x06,	\
		  0x8B, 0x00, 0x13, 0x26)
#define CPER_SEC_DMAR_GENERIC						\
	GUID_INIT(0x5B51FEF7, 0xC79D, 0x4434, 0x8F, 0x1B, 0xAA, 0x62,	\
		  0xDE, 0x3E, 0x2C, 0x64)
/* Intel VT for Directed I/O specific DMAr */
#define CPER_SEC_DMAR_VT						\
	GUID_INIT(0x71761D37, 0x32B2, 0x45cd, 0xA7, 0xD0, 0xB0, 0xFE,	\
		  0xDD, 0x93, 0xE8, 0xCF)
/* IOMMU specific DMAr */
#define CPER_SEC_DMAR_IOMMU						\
	GUID_INIT(0x036F84E1, 0x7F37, 0x428c, 0xA7, 0x9E, 0x57, 0x5F,	\
		  0xDF, 0xAA, 0x84, 0xEC)

#define CPER_PROC_VALID_TYPE			0x0001
#define CPER_PROC_VALID_ISA			0x0002
#define CPER_PROC_VALID_ERROR_TYPE		0x0004
#define CPER_PROC_VALID_OPERATION		0x0008
#define CPER_PROC_VALID_FLAGS			0x0010
#define CPER_PROC_VALID_LEVEL			0x0020
#define CPER_PROC_VALID_VERSION			0x0040
#define CPER_PROC_VALID_BRAND_INFO		0x0080
#define CPER_PROC_VALID_ID			0x0100
#define CPER_PROC_VALID_TARGET_ADDRESS		0x0200
#define CPER_PROC_VALID_REQUESTOR_ID		0x0400
#define CPER_PROC_VALID_RESPONDER_ID		0x0800
#define CPER_PROC_VALID_IP			0x1000

#define CPER_MEM_VALID_ERROR_STATUS		0x0001
#define CPER_MEM_VALID_PA			0x0002
#define CPER_MEM_VALID_PA_MASK			0x0004
#define CPER_MEM_VALID_NODE			0x0008
#define CPER_MEM_VALID_CARD			0x0010
#define CPER_MEM_VALID_MODULE			0x0020
#define CPER_MEM_VALID_BANK			0x0040
#define CPER_MEM_VALID_DEVICE			0x0080
#define CPER_MEM_VALID_ROW			0x0100
#define CPER_MEM_VALID_COLUMN			0x0200
#define CPER_MEM_VALID_BIT_POSITION		0x0400
#define CPER_MEM_VALID_REQUESTOR_ID		0x0800
#define CPER_MEM_VALID_RESPONDER_ID		0x1000
#define CPER_MEM_VALID_TARGET_ID		0x2000
#define CPER_MEM_VALID_ERROR_TYPE		0x4000
#define CPER_MEM_VALID_RANK_NUMBER		0x8000
#define CPER_MEM_VALID_CARD_HANDLE		0x10000
#define CPER_MEM_VALID_MODULE_HANDLE		0x20000

#define CPER_PCIE_VALID_PORT_TYPE		0x0001
#define CPER_PCIE_VALID_VERSION			0x0002
#define CPER_PCIE_VALID_COMMAND_STATUS		0x0004
#define CPER_PCIE_VALID_DEVICE_ID		0x0008
#define CPER_PCIE_VALID_SERIAL_NUMBER		0x0010
#define CPER_PCIE_VALID_BRIDGE_CONTROL_STATUS	0x0020
#define CPER_PCIE_VALID_CAPABILITY		0x0040
#define CPER_PCIE_VALID_AER_INFO		0x0080

#define CPER_PCIE_SLOT_SHIFT			3

#define CPER_ARM_VALID_MPIDR			BIT(0)
#define CPER_ARM_VALID_AFFINITY_LEVEL		BIT(1)
#define CPER_ARM_VALID_RUNNING_STATE		BIT(2)
#define CPER_ARM_VALID_VENDOR_INFO		BIT(3)

#define CPER_ARM_INFO_VALID_MULTI_ERR		BIT(0)
#define CPER_ARM_INFO_VALID_FLAGS		BIT(1)
#define CPER_ARM_INFO_VALID_ERR_INFO		BIT(2)
#define CPER_ARM_INFO_VALID_VIRT_ADDR		BIT(3)
#define CPER_ARM_INFO_VALID_PHYSICAL_ADDR	BIT(4)

#define CPER_ARM_INFO_FLAGS_FIRST		BIT(0)
#define CPER_ARM_INFO_FLAGS_LAST		BIT(1)
#define CPER_ARM_INFO_FLAGS_PROPAGATED		BIT(2)
#define CPER_ARM_INFO_FLAGS_OVERFLOW		BIT(3)

#define CPER_ARM_CACHE_ERROR			0
#define CPER_ARM_TLB_ERROR			1
#define CPER_ARM_BUS_ERROR			2
#define CPER_ARM_VENDOR_ERROR			3
#define CPER_ARM_MAX_TYPE			CPER_ARM_VENDOR_ERROR

#define CPER_ARM_ERR_VALID_TRANSACTION_TYPE	BIT(0)
#define CPER_ARM_ERR_VALID_OPERATION_TYPE	BIT(1)
#define CPER_ARM_ERR_VALID_LEVEL		BIT(2)
#define CPER_ARM_ERR_VALID_PROC_CONTEXT_CORRUPT	BIT(3)
#define CPER_ARM_ERR_VALID_CORRECTED		BIT(4)
#define CPER_ARM_ERR_VALID_PRECISE_PC		BIT(5)
#define CPER_ARM_ERR_VALID_RESTARTABLE_PC	BIT(6)
#define CPER_ARM_ERR_VALID_PARTICIPATION_TYPE	BIT(7)
#define CPER_ARM_ERR_VALID_TIME_OUT		BIT(8)
#define CPER_ARM_ERR_VALID_ADDRESS_SPACE	BIT(9)
#define CPER_ARM_ERR_VALID_MEM_ATTRIBUTES	BIT(10)
#define CPER_ARM_ERR_VALID_ACCESS_MODE		BIT(11)

#define CPER_ARM_ERR_TRANSACTION_SHIFT		16
#define CPER_ARM_ERR_TRANSACTION_MASK		GENMASK(1,0)
#define CPER_ARM_ERR_OPERATION_SHIFT		18
#define CPER_ARM_ERR_OPERATION_MASK		GENMASK(3,0)
#define CPER_ARM_ERR_LEVEL_SHIFT		22
#define CPER_ARM_ERR_LEVEL_MASK			GENMASK(2,0)
#define CPER_ARM_ERR_PC_CORRUPT_SHIFT		25
#define CPER_ARM_ERR_PC_CORRUPT_MASK		GENMASK(0,0)
#define CPER_ARM_ERR_CORRECTED_SHIFT		26
#define CPER_ARM_ERR_CORRECTED_MASK		GENMASK(0,0)
#define CPER_ARM_ERR_PRECISE_PC_SHIFT		27
#define CPER_ARM_ERR_PRECISE_PC_MASK		GENMASK(0,0)
#define CPER_ARM_ERR_RESTARTABLE_PC_SHIFT	28
#define CPER_ARM_ERR_RESTARTABLE_PC_MASK	GENMASK(0,0)
#define CPER_ARM_ERR_PARTICIPATION_TYPE_SHIFT	29
#define CPER_ARM_ERR_PARTICIPATION_TYPE_MASK	GENMASK(1,0)
#define CPER_ARM_ERR_TIME_OUT_SHIFT		31
#define CPER_ARM_ERR_TIME_OUT_MASK		GENMASK(0,0)
#define CPER_ARM_ERR_ADDRESS_SPACE_SHIFT	32
#define CPER_ARM_ERR_ADDRESS_SPACE_MASK		GENMASK(1,0)
#define CPER_ARM_ERR_MEM_ATTRIBUTES_SHIFT	34
#define CPER_ARM_ERR_MEM_ATTRIBUTES_MASK	GENMASK(8,0)
#define CPER_ARM_ERR_ACCESS_MODE_SHIFT		43
#define CPER_ARM_ERR_ACCESS_MODE_MASK		GENMASK(0,0)

/*
 * All tables and structs must be byte-packed to match CPER
 * specification, since the tables are provided by the system BIOS
 */
#pragma pack(1)

/* Record Header, UEFI v2.7 sec N.2.1 */
struct cper_record_header {
	char	signature[CPER_SIG_SIZE];	/* must be CPER_SIG_RECORD */
	u16	revision;			/* must be CPER_RECORD_REV */
	u32	signature_end;			/* must be CPER_SIG_END */
	u16	section_count;
	u32	error_severity;
	u32	validation_bits;
	u32	record_length;
	u64	timestamp;
	guid_t	platform_id;
	guid_t	partition_id;
	guid_t	creator_id;
	guid_t	notification_type;
	u64	record_id;
	u32	flags;
	u64	persistence_information;
	u8	reserved[12];			/* must be zero */
};

/* Section Descriptor, UEFI v2.7 sec N.2.2 */
struct cper_section_descriptor {
	u32	section_offset;		/* Offset in bytes of the
					 *  section body from the base
					 *  of the record header */
	u32	section_length;
	u16	revision;		/* must be CPER_RECORD_REV */
	u8	validation_bits;
	u8	reserved;		/* must be zero */
	u32	flags;
	guid_t	section_type;
	guid_t	fru_id;
	u32	section_severity;
	u8	fru_text[20];
};

/* Generic Processor Error Section, UEFI v2.7 sec N.2.4.1 */
struct cper_sec_proc_generic {
	u64	validation_bits;
	u8	proc_type;
	u8	proc_isa;
	u8	proc_error_type;
	u8	operation;
	u8	flags;
	u8	level;
	u16	reserved;
	u64	cpu_version;
	char	cpu_brand[128];
	u64	proc_id;
	u64	target_addr;
	u64	requestor_id;
	u64	responder_id;
	u64	ip;
};

/* IA32/X64 Processor Error Section, UEFI v2.7 sec N.2.4.2 */
struct cper_sec_proc_ia {
	u64	validation_bits;
	u64	lapic_id;
	u8	cpuid[48];
};

/* IA32/X64 Processor Error Information Structure, UEFI v2.7 sec N.2.4.2.1 */
struct cper_ia_err_info {
	guid_t	err_type;
	u64	validation_bits;
	u64	check_info;
	u64	target_id;
	u64	requestor_id;
	u64	responder_id;
	u64	ip;
};

/* IA32/X64 Processor Context Information Structure, UEFI v2.7 sec N.2.4.2.2 */
struct cper_ia_proc_ctx {
	u16	reg_ctx_type;
	u16	reg_arr_size;
	u32	msr_addr;
	u64	mm_reg_addr;
};

/* ARM Processor Error Section, UEFI v2.7 sec N.2.4.4 */
struct cper_sec_proc_arm {
	u32	validation_bits;
	u16	err_info_num;		/* Number of Processor Error Info */
	u16	context_info_num;	/* Number of Processor Context Info Records*/
	u32	section_length;
	u8	affinity_level;
	u8	reserved[3];		/* must be zero */
	u64	mpidr;
	u64	midr;
	u32	running_state;		/* Bit 0 set - Processor running. PSCI = 0 */
	u32	psci_state;
};

/* ARM Processor Error Information Structure, UEFI v2.7 sec N.2.4.4.1 */
struct cper_arm_err_info {
	u8	version;
	u8	length;
	u16	validation_bits;
	u8	type;
	u16	multiple_error;
	u8	flags;
	u64	error_info;
	u64	virt_fault_addr;
	u64	physical_fault_addr;
};

/* ARM Processor Context Information Structure, UEFI v2.7 sec N.2.4.4.2 */
struct cper_arm_ctx_info {
	u16	version;
	u16	type;
	u32	size;
};

/* Old Memory Error Section, UEFI v2.1, v2.2 */
struct cper_sec_mem_err_old {
	u64	validation_bits;
	u64	error_status;
	u64	physical_addr;
	u64	physical_addr_mask;
	u16	node;
	u16	card;
	u16	module;
	u16	bank;
	u16	device;
	u16	row;
	u16	column;
	u16	bit_pos;
	u64	requestor_id;
	u64	responder_id;
	u64	target_id;
	u8	error_type;
};

/* Memory Error Section (UEFI >= v2.3), UEFI v2.7 sec N.2.5 */
struct cper_sec_mem_err {
	u64	validation_bits;
	u64	error_status;
	u64	physical_addr;
	u64	physical_addr_mask;
	u16	node;
	u16	card;
	u16	module;
	u16	bank;
	u16	device;
	u16	row;
	u16	column;
	u16	bit_pos;
	u64	requestor_id;
	u64	responder_id;
	u64	target_id;
	u8	error_type;
	u8	reserved;
	u16	rank;
	u16	mem_array_handle;	/* "card handle" in UEFI 2.4 */
	u16	mem_dev_handle;		/* "module handle" in UEFI 2.4 */
};

struct cper_mem_err_compact {
	u64	validation_bits;
	u16	node;
	u16	card;
	u16	module;
	u16	bank;
	u16	device;
	u16	row;
	u16	column;
	u16	bit_pos;
	u64	requestor_id;
	u64	responder_id;
	u64	target_id;
	u16	rank;
	u16	mem_array_handle;
	u16	mem_dev_handle;
};

/* PCI Express Error Section, UEFI v2.7 sec N.2.7 */
struct cper_sec_pcie {
	u64		validation_bits;
	u32		port_type;
	struct {
		u8	minor;
		u8	major;
		u8	reserved[2];
	}		version;
	u16		command;
	u16		status;
	u32		reserved;
	struct {
		u16	vendor_id;
		u16	device_id;
		u8	class_code[3];
		u8	function;
		u8	device;
		u16	segment;
		u8	bus;
		u8	secondary_bus;
		u16	slot;
		u8	reserved;
	}		device_id;
	struct {
		u32	lower;
		u32	upper;
	}		serial_number;
	struct {
		u16	secondary_status;
		u16	control;
	}		bridge;
	u8	capability[60];
	u8	aer_info[96];
};

/* Reset to default packing */
#pragma pack()

extern const char *const cper_proc_error_type_strs[4];

u64 cper_next_record_id(void);
const char *cper_severity_str(unsigned int);
const char *cper_mem_err_type_str(unsigned int);
void cper_print_bits(const char *prefix, unsigned int bits,
		     const char * const strs[], unsigned int strs_size);
void cper_mem_err_pack(const struct cper_sec_mem_err *,
		       struct cper_mem_err_compact *);
const char *cper_mem_err_unpack(struct trace_seq *,
				struct cper_mem_err_compact *);
void cper_print_proc_arm(const char *pfx,
			 const struct cper_sec_proc_arm *proc);
void cper_print_proc_ia(const char *pfx,
			const struct cper_sec_proc_ia *proc);

#endif
Commit	Line	Data
06d65dea HY	1	/*
	2	* UEFI Common Platform Error Record
	3	*
	4	* Copyright (C) 2010, Intel Corp.
	5	* Author: Huang Ying <ying.huang@intel.com>
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License version
	9	* 2 as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
	21	#ifndef LINUX_CPER_H
	22	#define LINUX_CPER_H
	23
	24	#include <linux/uuid.h>
2dfb7d51	25	#include <linux/trace_seq.h>
06d65dea HY	26
	27	/* CPER record signature and the size */
	28	#define CPER_SIG_RECORD "CPER"
	29	#define CPER_SIG_SIZE 4
	30	/* Used in signature_end field in struct cper_record_header */
	31	#define CPER_SIG_END 0xffffffff
	32
	33	/*
	34	* CPER record header revision, used in revision field in struct
	35	* cper_record_header
	36	*/
	37	#define CPER_RECORD_REV 0x0100
	38
3760cd20 CG	39	/*
	40	* CPER record length contains the CPER fields which are relevant for further
	41	* handling of a memory error in userspace (we don't carry all the fields
	42	* defined in the UEFI spec because some of them don't make any sense.)
	43	* Currently, a length of 256 should be more than enough.
	44	*/
	45	#define CPER_REC_LEN 256
06d65dea	46	/*
12fa4f47	47	* Severity definition for error_severity in struct cper_record_header
06d65dea HY	48	* and section_severity in struct cper_section_descriptor
06d65dea HY	49	*/
c9aa308f HY	50	enum {
	51	CPER_SEV_RECOVERABLE,
	52	CPER_SEV_FATAL,
	53	CPER_SEV_CORRECTED,
	54	CPER_SEV_INFORMATIONAL,
	55	};
06d65dea HY	56
06d65dea HY	57	/*
12fa4f47	58	* Validation bits definition for validation_bits in struct
06d65dea HY	59	* cper_record_header. If set, corresponding fields in struct
06d65dea HY	60	* cper_record_header contain valid information.
06d65dea HY	61	*/
06d65dea HY	62	#define CPER_VALID_PLATFORM_ID 0x0001
06d65dea	63	#define CPER_VALID_TIMESTAMP 0x0002
06d65dea HY	64	#define CPER_VALID_PARTITION_ID 0x0004
	65
	66	/*
	67	* Notification type used to generate error record, used in
12fa4f47 BH	68	* notification_type in struct cper_record_header. These UUIDs are defined
12fa4f47 BH	69	* in the UEFI spec v2.7, sec N.2.1.
06d65dea	70	*/
12fa4f47 BH	71
12fa4f47 BH	72	/* Corrected Machine Check */
06d65dea	73	#define CPER_NOTIFY_CMC \
c0020756 AS	74	GUID_INIT(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4, \
c0020756 AS	75	0xEB, 0xD4, 0xF8, 0x90)
06d65dea HY	76	/* Corrected Platform Error */
06d65dea HY	77	#define CPER_NOTIFY_CPE \
c0020756 AS	78	GUID_INIT(0x4E292F96, 0xD843, 0x4a55, 0xA8, 0xC2, 0xD4, 0x81, \
c0020756 AS	79	0xF2, 0x7E, 0xBE, 0xEE)
06d65dea HY	80	/* Machine Check Exception */
06d65dea HY	81	#define CPER_NOTIFY_MCE \
c0020756 AS	82	GUID_INIT(0xE8F56FFE, 0x919C, 0x4cc5, 0xBA, 0x88, 0x65, 0xAB, \
c0020756 AS	83	0xE1, 0x49, 0x13, 0xBB)
06d65dea HY	84	/* PCI Express Error */
06d65dea HY	85	#define CPER_NOTIFY_PCIE \
c0020756 AS	86	GUID_INIT(0xCF93C01F, 0x1A16, 0x4dfc, 0xB8, 0xBC, 0x9C, 0x4D, \
c0020756 AS	87	0xAF, 0x67, 0xC1, 0x04)
06d65dea HY	88	/* INIT Record (for IPF) */
06d65dea HY	89	#define CPER_NOTIFY_INIT \
c0020756 AS	90	GUID_INIT(0xCC5263E8, 0x9308, 0x454a, 0x89, 0xD0, 0x34, 0x0B, \
c0020756 AS	91	0xD3, 0x9B, 0xC9, 0x8E)
06d65dea HY	92	/* Non-Maskable Interrupt */
06d65dea HY	93	#define CPER_NOTIFY_NMI \
c0020756 AS	94	GUID_INIT(0x5BAD89FF, 0xB7E6, 0x42c9, 0x81, 0x4A, 0xCF, 0x24, \
c0020756 AS	95	0x85, 0xD6, 0xE9, 0x8A)
06d65dea HY	96	/* BOOT Error Record */
06d65dea HY	97	#define CPER_NOTIFY_BOOT \
c0020756 AS	98	GUID_INIT(0x3D61A466, 0xAB40, 0x409a, 0xA6, 0x98, 0xF3, 0x62, \
c0020756 AS	99	0xD4, 0x64, 0xB3, 0x8F)
06d65dea HY	100	/* DMA Remapping Error */
06d65dea HY	101	#define CPER_NOTIFY_DMAR \
c0020756 AS	102	GUID_INIT(0x667DD791, 0xC6B3, 0x4c27, 0x8A, 0x6B, 0x0F, 0x8E, \
c0020756 AS	103	0x72, 0x2D, 0xEB, 0x41)
06d65dea HY	104
	105	/*
	106	* Flags bits definitions for flags in struct cper_record_header
	107	* If set, the error has been recovered
	108	*/
	109	#define CPER_HW_ERROR_FLAGS_RECOVERED 0x1
	110	/* If set, the error is for previous boot */
	111	#define CPER_HW_ERROR_FLAGS_PREVERR 0x2
	112	/* If set, the error is injected for testing */
	113	#define CPER_HW_ERROR_FLAGS_SIMULATED 0x4
	114
	115	/*
	116	* CPER section header revision, used in revision field in struct
	117	* cper_section_descriptor
	118	*/
	119	#define CPER_SEC_REV 0x0100
	120
	121	/*
12fa4f47	122	* Validation bits definition for validation_bits in struct
06d65dea HY	123	* cper_section_descriptor. If set, corresponding fields in struct
06d65dea HY	124	* cper_section_descriptor contain valid information.
06d65dea HY	125	*/
06d65dea HY	126	#define CPER_SEC_VALID_FRU_ID 0x1
06d65dea HY	127	#define CPER_SEC_VALID_FRU_TEXT 0x2
	128
	129	/*
	130	* Flags bits definitions for flags in struct cper_section_descriptor
	131	*
	132	* If set, the section is associated with the error condition
	133	* directly, and should be focused on
	134	*/
	135	#define CPER_SEC_PRIMARY 0x0001
	136	/*
	137	* If set, the error was not contained within the processor or memory
	138	* hierarchy and the error may have propagated to persistent storage
	139	* or network
	140	*/
	141	#define CPER_SEC_CONTAINMENT_WARNING 0x0002
	142	/* If set, the component must be re-initialized or re-enabled prior to use */
	143	#define CPER_SEC_RESET 0x0004
	144	/* If set, Linux may choose to discontinue use of the resource */
	145	#define CPER_SEC_ERROR_THRESHOLD_EXCEEDED 0x0008
	146	/*
	147	* If set, resource could not be queried for error information due to
	148	* conflicts with other system software or resources. Some fields of
	149	* the section will be invalid
	150	*/
	151	#define CPER_SEC_RESOURCE_NOT_ACCESSIBLE 0x0010
	152	/*
	153	* If set, action has been taken to ensure error containment (such as
	154	* poisoning data), but the error has not been fully corrected and the
	155	* data has not been consumed. Linux may choose to take further
	156	* corrective action before the data is consumed
	157	*/
	158	#define CPER_SEC_LATENT_ERROR 0x0020
	159
	160	/*
	161	* Section type definitions, used in section_type field in struct
12fa4f47 BH	162	* cper_section_descriptor. These UUIDs are defined in the UEFI spec
12fa4f47 BH	163	* v2.7, sec N.2.2.
06d65dea	164	*/
12fa4f47 BH	165
12fa4f47 BH	166	/* Processor Generic */
06d65dea	167	#define CPER_SEC_PROC_GENERIC \
c0020756 AS	168	GUID_INIT(0x9876CCAD, 0x47B4, 0x4bdb, 0xB6, 0x5E, 0x16, 0xF1, \
c0020756 AS	169	0x93, 0xC4, 0xF3, 0xDB)
06d65dea HY	170	/* Processor Specific: X86/X86_64 */
06d65dea HY	171	#define CPER_SEC_PROC_IA \
c0020756 AS	172	GUID_INIT(0xDC3EA0B0, 0xA144, 0x4797, 0xB9, 0x5B, 0x53, 0xFA, \
c0020756 AS	173	0x24, 0x2B, 0x6E, 0x1D)
06d65dea HY	174	/* Processor Specific: IA64 */
06d65dea HY	175	#define CPER_SEC_PROC_IPF \
c0020756 AS	176	GUID_INIT(0xE429FAF1, 0x3CB7, 0x11D4, 0x0B, 0xCA, 0x07, 0x00, \
c0020756 AS	177	0x80, 0xC7, 0x3C, 0x88, 0x81)
2f74f09b TB	178	/* Processor Specific: ARM */
2f74f09b TB	179	#define CPER_SEC_PROC_ARM \
c0020756 AS	180	GUID_INIT(0xE19E3D16, 0xBC11, 0x11E4, 0x9C, 0xAA, 0xC2, 0x05, \
c0020756 AS	181	0x1D, 0x5D, 0x46, 0xB0)
06d65dea HY	182	/* Platform Memory */
06d65dea HY	183	#define CPER_SEC_PLATFORM_MEM \
c0020756 AS	184	GUID_INIT(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83, \
c0020756 AS	185	0xED, 0x7C, 0x83, 0xB1)
06d65dea	186	#define CPER_SEC_PCIE \
c0020756 AS	187	GUID_INIT(0xD995E954, 0xBBC1, 0x430F, 0xAD, 0x91, 0xB4, 0x4D, \
c0020756 AS	188	0xCB, 0x3C, 0x6F, 0x35)
06d65dea HY	189	/* Firmware Error Record Reference */
06d65dea HY	190	#define CPER_SEC_FW_ERR_REC_REF \
c0020756 AS	191	GUID_INIT(0x81212A96, 0x09ED, 0x4996, 0x94, 0x71, 0x8D, 0x72, \
c0020756 AS	192	0x9C, 0x8E, 0x69, 0xED)
06d65dea HY	193	/* PCI/PCI-X Bus */
06d65dea HY	194	#define CPER_SEC_PCI_X_BUS \
c0020756 AS	195	GUID_INIT(0xC5753963, 0x3B84, 0x4095, 0xBF, 0x78, 0xED, 0xDA, \
c0020756 AS	196	0xD3, 0xF9, 0xC9, 0xDD)
06d65dea HY	197	/* PCI Component/Device */
06d65dea HY	198	#define CPER_SEC_PCI_DEV \
c0020756 AS	199	GUID_INIT(0xEB5E4685, 0xCA66, 0x4769, 0xB6, 0xA2, 0x26, 0x06, \
c0020756 AS	200	0x8B, 0x00, 0x13, 0x26)
06d65dea	201	#define CPER_SEC_DMAR_GENERIC \
c0020756 AS	202	GUID_INIT(0x5B51FEF7, 0xC79D, 0x4434, 0x8F, 0x1B, 0xAA, 0x62, \
c0020756 AS	203	0xDE, 0x3E, 0x2C, 0x64)
06d65dea HY	204	/* Intel VT for Directed I/O specific DMAr */
06d65dea HY	205	#define CPER_SEC_DMAR_VT \
c0020756 AS	206	GUID_INIT(0x71761D37, 0x32B2, 0x45cd, 0xA7, 0xD0, 0xB0, 0xFE, \
c0020756 AS	207	0xDD, 0x93, 0xE8, 0xCF)
06d65dea HY	208	/* IOMMU specific DMAr */
06d65dea HY	209	#define CPER_SEC_DMAR_IOMMU \
c0020756 AS	210	GUID_INIT(0x036F84E1, 0x7F37, 0x428c, 0xA7, 0x9E, 0x57, 0x5F, \
c0020756 AS	211	0xDF, 0xAA, 0x84, 0xEC)
06d65dea	212
c9aa308f HY	213	#define CPER_PROC_VALID_TYPE 0x0001
	214	#define CPER_PROC_VALID_ISA 0x0002
	215	#define CPER_PROC_VALID_ERROR_TYPE 0x0004
	216	#define CPER_PROC_VALID_OPERATION 0x0008
	217	#define CPER_PROC_VALID_FLAGS 0x0010
	218	#define CPER_PROC_VALID_LEVEL 0x0020
	219	#define CPER_PROC_VALID_VERSION 0x0040
	220	#define CPER_PROC_VALID_BRAND_INFO 0x0080
	221	#define CPER_PROC_VALID_ID 0x0100
	222	#define CPER_PROC_VALID_TARGET_ADDRESS 0x0200
	223	#define CPER_PROC_VALID_REQUESTOR_ID 0x0400
	224	#define CPER_PROC_VALID_RESPONDER_ID 0x0800
	225	#define CPER_PROC_VALID_IP 0x1000
	226
	227	#define CPER_MEM_VALID_ERROR_STATUS 0x0001
147de147 CG	228	#define CPER_MEM_VALID_PA 0x0002
147de147 CG	229	#define CPER_MEM_VALID_PA_MASK 0x0004
c9aa308f HY	230	#define CPER_MEM_VALID_NODE 0x0008
	231	#define CPER_MEM_VALID_CARD 0x0010
	232	#define CPER_MEM_VALID_MODULE 0x0020
	233	#define CPER_MEM_VALID_BANK 0x0040
	234	#define CPER_MEM_VALID_DEVICE 0x0080
	235	#define CPER_MEM_VALID_ROW 0x0100
	236	#define CPER_MEM_VALID_COLUMN 0x0200
	237	#define CPER_MEM_VALID_BIT_POSITION 0x0400
	238	#define CPER_MEM_VALID_REQUESTOR_ID 0x0800
	239	#define CPER_MEM_VALID_RESPONDER_ID 0x1000
	240	#define CPER_MEM_VALID_TARGET_ID 0x2000
	241	#define CPER_MEM_VALID_ERROR_TYPE 0x4000
147de147 CG	242	#define CPER_MEM_VALID_RANK_NUMBER 0x8000
	243	#define CPER_MEM_VALID_CARD_HANDLE 0x10000
	244	#define CPER_MEM_VALID_MODULE_HANDLE 0x20000
c9aa308f HY	245
	246	#define CPER_PCIE_VALID_PORT_TYPE 0x0001
	247	#define CPER_PCIE_VALID_VERSION 0x0002
	248	#define CPER_PCIE_VALID_COMMAND_STATUS 0x0004
	249	#define CPER_PCIE_VALID_DEVICE_ID 0x0008
	250	#define CPER_PCIE_VALID_SERIAL_NUMBER 0x0010
	251	#define CPER_PCIE_VALID_BRIDGE_CONTROL_STATUS 0x0020
	252	#define CPER_PCIE_VALID_CAPABILITY 0x0040
	253	#define CPER_PCIE_VALID_AER_INFO 0x0080
	254
	255	#define CPER_PCIE_SLOT_SHIFT 3
	256
2f74f09b TB	257	#define CPER_ARM_VALID_MPIDR BIT(0)
	258	#define CPER_ARM_VALID_AFFINITY_LEVEL BIT(1)
	259	#define CPER_ARM_VALID_RUNNING_STATE BIT(2)
	260	#define CPER_ARM_VALID_VENDOR_INFO BIT(3)
	261
	262	#define CPER_ARM_INFO_VALID_MULTI_ERR BIT(0)
	263	#define CPER_ARM_INFO_VALID_FLAGS BIT(1)
	264	#define CPER_ARM_INFO_VALID_ERR_INFO BIT(2)
	265	#define CPER_ARM_INFO_VALID_VIRT_ADDR BIT(3)
	266	#define CPER_ARM_INFO_VALID_PHYSICAL_ADDR BIT(4)
	267
	268	#define CPER_ARM_INFO_FLAGS_FIRST BIT(0)
	269	#define CPER_ARM_INFO_FLAGS_LAST BIT(1)
	270	#define CPER_ARM_INFO_FLAGS_PROPAGATED BIT(2)
	271	#define CPER_ARM_INFO_FLAGS_OVERFLOW BIT(3)
	272
301f55b1 TB	273	#define CPER_ARM_CACHE_ERROR 0
	274	#define CPER_ARM_TLB_ERROR 1
	275	#define CPER_ARM_BUS_ERROR 2
	276	#define CPER_ARM_VENDOR_ERROR 3
	277	#define CPER_ARM_MAX_TYPE CPER_ARM_VENDOR_ERROR
	278
	279	#define CPER_ARM_ERR_VALID_TRANSACTION_TYPE BIT(0)
	280	#define CPER_ARM_ERR_VALID_OPERATION_TYPE BIT(1)
	281	#define CPER_ARM_ERR_VALID_LEVEL BIT(2)
	282	#define CPER_ARM_ERR_VALID_PROC_CONTEXT_CORRUPT BIT(3)
	283	#define CPER_ARM_ERR_VALID_CORRECTED BIT(4)
	284	#define CPER_ARM_ERR_VALID_PRECISE_PC BIT(5)
	285	#define CPER_ARM_ERR_VALID_RESTARTABLE_PC BIT(6)
	286	#define CPER_ARM_ERR_VALID_PARTICIPATION_TYPE BIT(7)
	287	#define CPER_ARM_ERR_VALID_TIME_OUT BIT(8)
	288	#define CPER_ARM_ERR_VALID_ADDRESS_SPACE BIT(9)
	289	#define CPER_ARM_ERR_VALID_MEM_ATTRIBUTES BIT(10)
	290	#define CPER_ARM_ERR_VALID_ACCESS_MODE BIT(11)
	291
	292	#define CPER_ARM_ERR_TRANSACTION_SHIFT 16
	293	#define CPER_ARM_ERR_TRANSACTION_MASK GENMASK(1,0)
	294	#define CPER_ARM_ERR_OPERATION_SHIFT 18
	295	#define CPER_ARM_ERR_OPERATION_MASK GENMASK(3,0)
	296	#define CPER_ARM_ERR_LEVEL_SHIFT 22
	297	#define CPER_ARM_ERR_LEVEL_MASK GENMASK(2,0)
	298	#define CPER_ARM_ERR_PC_CORRUPT_SHIFT 25
	299	#define CPER_ARM_ERR_PC_CORRUPT_MASK GENMASK(0,0)
	300	#define CPER_ARM_ERR_CORRECTED_SHIFT 26
	301	#define CPER_ARM_ERR_CORRECTED_MASK GENMASK(0,0)
	302	#define CPER_ARM_ERR_PRECISE_PC_SHIFT 27
	303	#define CPER_ARM_ERR_PRECISE_PC_MASK GENMASK(0,0)
	304	#define CPER_ARM_ERR_RESTARTABLE_PC_SHIFT 28
	305	#define CPER_ARM_ERR_RESTARTABLE_PC_MASK GENMASK(0,0)
	306	#define CPER_ARM_ERR_PARTICIPATION_TYPE_SHIFT 29
	307	#define CPER_ARM_ERR_PARTICIPATION_TYPE_MASK GENMASK(1,0)
	308	#define CPER_ARM_ERR_TIME_OUT_SHIFT 31
	309	#define CPER_ARM_ERR_TIME_OUT_MASK GENMASK(0,0)
	310	#define CPER_ARM_ERR_ADDRESS_SPACE_SHIFT 32
	311	#define CPER_ARM_ERR_ADDRESS_SPACE_MASK GENMASK(1,0)
	312	#define CPER_ARM_ERR_MEM_ATTRIBUTES_SHIFT 34
	313	#define CPER_ARM_ERR_MEM_ATTRIBUTES_MASK GENMASK(8,0)
	314	#define CPER_ARM_ERR_ACCESS_MODE_SHIFT 43
	315	#define CPER_ARM_ERR_ACCESS_MODE_MASK GENMASK(0,0)
	316
06d65dea HY	317	/*
	318	* All tables and structs must be byte-packed to match CPER
	319	* specification, since the tables are provided by the system BIOS
	320	*/
	321	#pragma pack(1)
	322
12fa4f47	323	/* Record Header, UEFI v2.7 sec N.2.1 */
06d65dea HY	324	struct cper_record_header {
06d65dea HY	325	char signature[CPER_SIG_SIZE]; /* must be CPER_SIG_RECORD */
113fb03e BH	326	u16 revision; /* must be CPER_RECORD_REV */
	327	u32 signature_end; /* must be CPER_SIG_END */
	328	u16 section_count;
	329	u32 error_severity;
	330	u32 validation_bits;
	331	u32 record_length;
	332	u64 timestamp;
c0020756 AS	333	guid_t platform_id;
	334	guid_t partition_id;
	335	guid_t creator_id;
	336	guid_t notification_type;
113fb03e BH	337	u64 record_id;
	338	u32 flags;
	339	u64 persistence_information;
	340	u8 reserved[12]; /* must be zero */
06d65dea HY	341	};
06d65dea HY	342
12fa4f47	343	/* Section Descriptor, UEFI v2.7 sec N.2.2 */
06d65dea	344	struct cper_section_descriptor {
113fb03e	345	u32 section_offset; /* Offset in bytes of the
06d65dea HY	346	* section body from the base
06d65dea HY	347	* of the record header */
113fb03e BH	348	u32 section_length;
	349	u16 revision; /* must be CPER_RECORD_REV */
	350	u8 validation_bits;
	351	u8 reserved; /* must be zero */
	352	u32 flags;
c0020756 AS	353	guid_t section_type;
c0020756 AS	354	guid_t fru_id;
113fb03e BH	355	u32 section_severity;
113fb03e BH	356	u8 fru_text[20];
06d65dea HY	357	};
06d65dea HY	358
12fa4f47	359	/* Generic Processor Error Section, UEFI v2.7 sec N.2.4.1 */
06d65dea	360	struct cper_sec_proc_generic {
113fb03e BH	361	u64 validation_bits;
	362	u8 proc_type;
	363	u8 proc_isa;
	364	u8 proc_error_type;
	365	u8 operation;
	366	u8 flags;
	367	u8 level;
	368	u16 reserved;
	369	u64 cpu_version;
06d65dea	370	char cpu_brand[128];
113fb03e BH	371	u64 proc_id;
	372	u64 target_addr;
	373	u64 requestor_id;
	374	u64 responder_id;
	375	u64 ip;
06d65dea HY	376	};
06d65dea HY	377
12fa4f47	378	/* IA32/X64 Processor Error Section, UEFI v2.7 sec N.2.4.2 */
06d65dea	379	struct cper_sec_proc_ia {
113fb03e BH	380	u64 validation_bits;
	381	u64 lapic_id;
	382	u8 cpuid[48];
06d65dea HY	383	};
06d65dea HY	384
12fa4f47	385	/* IA32/X64 Processor Error Information Structure, UEFI v2.7 sec N.2.4.2.1 */
06d65dea	386	struct cper_ia_err_info {
c0020756	387	guid_t err_type;
113fb03e BH	388	u64 validation_bits;
	389	u64 check_info;
	390	u64 target_id;
	391	u64 requestor_id;
	392	u64 responder_id;
	393	u64 ip;
06d65dea HY	394	};
06d65dea HY	395
12fa4f47	396	/* IA32/X64 Processor Context Information Structure, UEFI v2.7 sec N.2.4.2.2 */
06d65dea	397	struct cper_ia_proc_ctx {
113fb03e BH	398	u16 reg_ctx_type;
	399	u16 reg_arr_size;
	400	u32 msr_addr;
	401	u64 mm_reg_addr;
06d65dea HY	402	};
06d65dea HY	403
12fa4f47	404	/* ARM Processor Error Section, UEFI v2.7 sec N.2.4.4 */
2f74f09b	405	struct cper_sec_proc_arm {
113fb03e BH	406	u32 validation_bits;
	407	u16 err_info_num; /* Number of Processor Error Info */
	408	u16 context_info_num; /* Number of Processor Context Info Records*/
	409	u32 section_length;
	410	u8 affinity_level;
	411	u8 reserved[3]; /* must be zero */
	412	u64 mpidr;
	413	u64 midr;
	414	u32 running_state; /* Bit 0 set - Processor running. PSCI = 0 */
	415	u32 psci_state;
2f74f09b TB	416	};
2f74f09b TB	417
12fa4f47	418	/* ARM Processor Error Information Structure, UEFI v2.7 sec N.2.4.4.1 */
2f74f09b	419	struct cper_arm_err_info {
113fb03e BH	420	u8 version;
	421	u8 length;
	422	u16 validation_bits;
	423	u8 type;
	424	u16 multiple_error;
	425	u8 flags;
	426	u64 error_info;
	427	u64 virt_fault_addr;
	428	u64 physical_fault_addr;
2f74f09b TB	429	};
2f74f09b TB	430
12fa4f47	431	/* ARM Processor Context Information Structure, UEFI v2.7 sec N.2.4.4.2 */
2f74f09b	432	struct cper_arm_ctx_info {
113fb03e BH	433	u16 version;
	434	u16 type;
	435	u32 size;
2f74f09b TB	436	};
2f74f09b TB	437
12fa4f47	438	/* Old Memory Error Section, UEFI v2.1, v2.2 */
4c62360d	439	struct cper_sec_mem_err_old {
113fb03e BH	440	u64 validation_bits;
	441	u64 error_status;
	442	u64 physical_addr;
	443	u64 physical_addr_mask;
	444	u16 node;
	445	u16 card;
	446	u16 module;
	447	u16 bank;
	448	u16 device;
	449	u16 row;
	450	u16 column;
	451	u16 bit_pos;
	452	u64 requestor_id;
	453	u64 responder_id;
	454	u64 target_id;
	455	u8 error_type;
4c62360d TL	456	};
4c62360d TL	457
12fa4f47	458	/* Memory Error Section (UEFI >= v2.3), UEFI v2.7 sec N.2.5 */
06d65dea	459	struct cper_sec_mem_err {
113fb03e BH	460	u64 validation_bits;
	461	u64 error_status;
	462	u64 physical_addr;
	463	u64 physical_addr_mask;
	464	u16 node;
	465	u16 card;
	466	u16 module;
	467	u16 bank;
	468	u16 device;
	469	u16 row;
	470	u16 column;
	471	u16 bit_pos;
	472	u64 requestor_id;
	473	u64 responder_id;
	474	u64 target_id;
	475	u8 error_type;
	476	u8 reserved;
	477	u16 rank;
	478	u16 mem_array_handle; /* "card handle" in UEFI 2.4 */
	479	u16 mem_dev_handle; /* "module handle" in UEFI 2.4 */
06d65dea HY	480	};
06d65dea HY	481
2dfb7d51	482	struct cper_mem_err_compact {
113fb03e BH	483	u64 validation_bits;
	484	u16 node;
	485	u16 card;
	486	u16 module;
	487	u16 bank;
	488	u16 device;
	489	u16 row;
	490	u16 column;
	491	u16 bit_pos;
	492	u64 requestor_id;
	493	u64 responder_id;
	494	u64 target_id;
	495	u16 rank;
	496	u16 mem_array_handle;
	497	u16 mem_dev_handle;
2dfb7d51 CG	498	};
2dfb7d51 CG	499
12fa4f47	500	/* PCI Express Error Section, UEFI v2.7 sec N.2.7 */
c9aa308f	501	struct cper_sec_pcie {
113fb03e BH	502	u64 validation_bits;
113fb03e BH	503	u32 port_type;
c9aa308f	504	struct {
113fb03e BH	505	u8 minor;
	506	u8 major;
	507	u8 reserved[2];
c9aa308f	508	} version;
113fb03e BH	509	u16 command;
	510	u16 status;
	511	u32 reserved;
c9aa308f	512	struct {
113fb03e BH	513	u16 vendor_id;
	514	u16 device_id;
	515	u8 class_code[3];
	516	u8 function;
	517	u8 device;
	518	u16 segment;
	519	u8 bus;
	520	u8 secondary_bus;
	521	u16 slot;
	522	u8 reserved;
c9aa308f HY	523	} device_id;
c9aa308f HY	524	struct {
113fb03e BH	525	u32 lower;
113fb03e BH	526	u32 upper;
c9aa308f HY	527	} serial_number;
c9aa308f HY	528	struct {
113fb03e BH	529	u16 secondary_status;
113fb03e BH	530	u16 control;
c9aa308f	531	} bridge;
113fb03e BH	532	u8 capability[60];
113fb03e BH	533	u8 aer_info[96];
c9aa308f HY	534	};
c9aa308f HY	535
06d65dea HY	536	/* Reset to default packing */
	537	#pragma pack()
	538
12fa4f47	539	extern const char *const cper_proc_error_type_strs[4];
c6d8c8ef	540
06d65dea	541	u64 cper_next_record_id(void);
3760cd20 CG	542	const char *cper_severity_str(unsigned int);
3760cd20 CG	543	const char *cper_mem_err_type_str(unsigned int);
c413d768	544	void cper_print_bits(const char *prefix, unsigned int bits,
88f074f4	545	const char * const strs[], unsigned int strs_size);
2dfb7d51 CG	546	void cper_mem_err_pack(const struct cper_sec_mem_err *,
	547	struct cper_mem_err_compact *);
	548	const char cper_mem_err_unpack(struct trace_seq ,
	549	struct cper_mem_err_compact *);
c6d8c8ef TB	550	void cper_print_proc_arm(const char *pfx,
c6d8c8ef TB	551	const struct cper_sec_proc_arm *proc);
f9e1bdb9 YG	552	void cper_print_proc_ia(const char *pfx,
f9e1bdb9 YG	553	const struct cper_sec_proc_ia *proc);
06d65dea HY	554
06d65dea HY	555	#endif